JPH02130131U - - Google Patents
Info
- Publication number
- JPH02130131U JPH02130131U JP3939989U JP3939989U JPH02130131U JP H02130131 U JPH02130131 U JP H02130131U JP 3939989 U JP3939989 U JP 3939989U JP 3939989 U JP3939989 U JP 3939989U JP H02130131 U JPH02130131 U JP H02130131U
- Authority
- JP
- Japan
- Prior art keywords
- output
- signal
- staircase
- down counter
- comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図はこの考案に係るＡ／Ｄ変換器の一実施
例を示すブロツク図、第２図はこの考案に係るＡ
／Ｄ変換器の他の実施例を示すブロツク図、第３
図は第２図の実際の回路を示す回路図、第４図は
第３図の動作説明図、第５図は従来のＡ／Ｄ変換
器の一例を示すブロツク図である、
１……コンパレータ、１０……アツプ・ダウン
カウンタ、１１……抵抗ラダー。
Figure 1 is a block diagram showing an embodiment of the A/D converter according to this invention, and Figure 2 is an A/D converter according to this invention.
Block diagram showing another embodiment of the /D converter, No. 3
The figure is a circuit diagram showing the actual circuit of Fig. 2, Fig. 4 is an explanatory diagram of the operation of Fig. 3, and Fig. 5 is a block diagram showing an example of a conventional A/D converter. 1... Comparator , 10... Up/down counter, 11... Resistance ladder.
Claims (1)
波信号を基準信号として他端子に入力して双方の
信号を比較するコンパレータ１と、このコンパレ
ータ１の出力に基づいてクロツク信号をカウント
アツプまたはカウントダウンするアツプ・ダウン
カウンタ１０と、このアツプ・ダウンカウンタの
出力に基づいて前記階段波信号を出力する階段波
信号出力回路１１とを備え、前記アツプ・ダウン
カウンタ１０出力を前記アナログ入力信号に対す
るデジタル信号として出力するＡ／Ｄ変換器。 A comparator 1 which inputs an analog input signal to one terminal and inputs a staircase wave signal as a reference signal to the other terminal to compare both signals, and counts up or counts down a clock signal based on the output of this comparator 1. It comprises an up/down counter 10 and a staircase signal output circuit 11 that outputs the staircase signal based on the output of the up/down counter, and outputs the output of the up/down counter 10 as a digital signal corresponding to the analog input signal. A/D converter for output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3939989U JPH02130131U (en) | 1989-04-03 | 1989-04-03 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3939989U JPH02130131U (en) | 1989-04-03 | 1989-04-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02130131U true JPH02130131U (en) | 1990-10-26 |
Family
ID=31548276
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3939989U Pending JPH02130131U (en) | 1989-04-03 | 1989-04-03 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02130131U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012120082A (en) * | 2010-12-03 | 2012-06-21 | Toyota Central R&D Labs Inc | Composite circuit of chopper amplification and digital conversion |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5030987A (en) * | 1973-07-18 | 1975-03-27 | ||
| JPS51109760A (en) * | 1975-03-24 | 1976-09-28 | Hitachi Ltd | aad henkanki |
| JPS59226514A (en) * | 1983-06-08 | 1984-12-19 | Sony Corp | A-d converter |
| JPS6037938B2 (en) * | 1980-12-29 | 1985-08-29 | 富士通株式会社 | information processing equipment |
-
1989
- 1989-04-03 JP JP3939989U patent/JPH02130131U/ja active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5030987A (en) * | 1973-07-18 | 1975-03-27 | ||
| JPS51109760A (en) * | 1975-03-24 | 1976-09-28 | Hitachi Ltd | aad henkanki |
| JPS6037938B2 (en) * | 1980-12-29 | 1985-08-29 | 富士通株式会社 | information processing equipment |
| JPS59226514A (en) * | 1983-06-08 | 1984-12-19 | Sony Corp | A-d converter |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012120082A (en) * | 2010-12-03 | 2012-06-21 | Toyota Central R&D Labs Inc | Composite circuit of chopper amplification and digital conversion |
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