JPH02114657A - Multilayer interconnection structure of semiconductor device - Google Patents

Abstract

PURPOSE:To alleviate stress such as film stress, thermal stress, and the like which acts on a first layer wiring so as to prevent the occurrence of defects in the first layer wiring by a method wherein an electrically non-connected dummy wiring is formed between the first layer wirings under a second layer wiring. CONSTITUTION:A first interlaminar insulating film 12 of a Si oxide film or the like is formed on a field oxide film 11 through a CVD method or the like, and two or more first layer wirings 13a and 13b of Al or the like d1 in width are formed at a specified interval of d2 through an evaporation method or the like. An electrically non-connected dummy wiring 14 of Al or the line with a width of d3 is selectively formed at a position separate from the first layer wirings 13a and 13b by a specified space d4. The dummy wiring 14 is formed together with, for instance, the first layer wirings 13a and 13b at the same time. An insulating inorganic coating film 15 of PSG or the like is formed on the first interlaminar insulating film 12 by SOG, and a second interlaminar insulating film is 16 of Si oxide or the like is formed thereon through a CVD method or the like.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a multilayer wiring structure of a semiconductor device such as a semiconductor integrated circuit.

(Prior art) Conventionally, as a technology in this field, for example, as shown in Fig. 2 (
There were items like those shown in a> and (b).

The configuration will be explained below.

FIGS. 2(a) and 2(b) are diagrams showing an example of a configuration of a multilayer wiring structure of a conventional semiconductor device, in which FIG. 2(a) is a plan view, and FIG. 2(b) is an A-A line thereof. It is an enlarged sectional view.

In this semiconductor device, for example, an N10
In the case of an S transistor, a source/'train region (not shown) is formed. A field oxide film 2 is formed on the Si substrate 1, and a portion of the field oxide film 2 is removed by etching, and a gate oxide film and a gate electrode (not shown) are successively formed in that region.

A first interlayer insulating film 3 such as a Si oxide film is formed on the field oxide 11!2, and A, I!2 is formed thereon. A plurality of first layer wirings 4 having a width W1 made of (aluminum)
a4b and 4c are arranged at a predetermined interval w2 (>wl). On the first interlayer insulating film 3, an SOG for flattening the stepped portion is provided.
(Spin On Glass) by PSG (
An inorganic coating 'plA5' such as phosphorus glass is formed, and a second interlayer insulating film 6 such as a Si oxide film is formed thereon. On the second interlayer insulation M6, a width w3 (>w
2>, the second layer wiring 7 has the first layer wiring 4a, 4b,
4c, and a passivation film such as a Si nitride film (surface protection M
)8 is coated.

1st. The second layer wirings 4a, 4b, 4c, and 7 are connected to a source/train region or a gate electrode (not shown), and the first layer wirings 4a, 4b, 4c, and 7 are connected to a source/train region or a gate electrode (not shown). Second layer wiring 4a, 4b.

By applying a voltage to 4c and 7, the MOS transistor operates.

In this type of multilayer wiring structure, the first layer wiring 4a.

Inorganic coating llA3 and second interlayer insulating film 6 on 4b and 4c
Since the second layer wiring 7 is formed in a layered manner via the semiconductor device, the wiring area of the semiconductor device can be reduced, and the degree of integration of the semiconductor device within the chip can be improved.

(Problems to be Solved by the Invention) To be more specific, the multilayer wiring structure of the semiconductor device having the above configuration has the following problems.

In the manufacturing process of the semiconductor device with the above configuration, if the second layer wiring 7 is subjected to heat treatment called sinking in order to make good ohmic contact, in the subsequent manufacturing process, the inorganic coating T71A5, the second interlayer insulating film 6, and the stress inherent in the second layer wiring 7 mainly affects each first layer wiring 4a, 4b.

It is locally concentrated at the edge portion 9 where the top surface and side surface of 4c are joined. As a result, the first layer wiring 4a.

Defects may occur in 4b and 4c, and if this condition worsens, there is a risk of wire breakage. At this time, since each of the first layer wirings 4a, 4b, and 4c is formed in various shapes, the above-mentioned stress is caused by It is estimated that the first layer wirings 4b and 4c, which are shorter than the wiring 4a, are excessively concentrated and failures such as disconnections occur more frequently.

By the way, if there is a defect in the first layer wirings 4a, 4b, 4c, electrical, thermal, or mechanical damage applied to the semiconductor device during the manufacturing process after sintering the second layer wiring 7 or during the operation of the semiconductor device. This will encourage the occurrence of migration due to stress (11τ utility). Migration includes, for example, electromigration, where a high-density electron flow flowing through a wiring pattern causes a phenomenon such as wire breakage at a location where the grain boundary size of the wiring layer suddenly changes, and similar phenomenon is caused by mechanical stress, etc. There are stress induced miglucidins, and when these occur, the reliability of semiconductor devices is significantly reduced.

The present invention solves the first problem that the prior art had.
The present invention provides a multi-node wiring structure for a semiconductor device that solves the problem that the reliability of the semiconductor device is lowered due to the occurrence of defects in the layered wiring.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides that several first layer wirings are formed on a substrate on which a semiconductor element is formed,
In a multilayer wiring structure of a semiconductor device in which a second layer wiring is formed on the first layer wiring in a direction intersecting the first layer wiring via an interlayer insulating film, One or more electrically unconnected dummy wirings are formed between each first layer wiring.

(Function) According to the present invention, since the multilayer wiring structure of the semiconductor device is configured as described above, the dummy wiring formed between each first layer wiring has an interlayer insulating film, a second layer wiring, etc. It has the function of absorbing various stresses such as mechanical stress due to stress caused by the semiconductor device, and thermal stress applied to the semiconductor device due to sinking of the second layer wiring. In this case, stress absorption in the dummy wiring is mainly performed at the edge portion where the top surface and side surface of the dummy wiring join, so if the number of dummy wirings arranged between each first layer wiring is increased, It becomes possible to further disperse stress and increase the amount of absorption, further enhancing its function. This makes it possible to reduce various types of stress locally concentrated at the edge portions of the first layer wiring, and to prevent defects from occurring in the first layer wiring due to the stress. Therefore, the above problem can be solved.

(Embodiment) FIGS. 1(a) and 1(b) are diagrams showing a multilayer wiring structure of a semiconductor device according to a first embodiment of the present invention, and FIG. 1(a) is a plan view, and FIG. b) is a sectional view taken along the line B-B.

In this semiconductor device, source/drain regions (not shown) are formed in the Si substrate 10 in the field region Y in the case of a MOS transistor, for example. Si
A field oxide film 11 is formed on the substrate 10, and a portion of the field oxide film 11 is removed by etching, and a gate oxide film and a gate electrode (not shown) are sequentially formed in that region.

A first interlayer insulating film 12 made of a Si oxide film or the like is formed on the field oxidation Mll using a CVD method (chemical vapor deposition method) or the like, and a width dl made of Afl or the like is formed thereon by a vapor deposition method or the like. (for example, about 3 μm or less), the plurality of first layer wirings 13a13b are arranged at a predetermined interval d2 (for example, about 3 μm or less).
(approximately 20 tzm or more). Between the first layer wirings 13a and 13b, an electrically unconnected dummy wiring 14 having a width d3 (for example, about 20 μm or less) made of A or the like is located between the first layer wiring 13a.

13b at a predetermined distance d4 (for example, less than about 20 μm). For example, the dummy wiring 14 is formed at the same time as the first layer wirings 13a and 13b.

An insulating inorganic coating film 15 such as PSG is formed on the first interlayer insulating film 12 using SOG, and a second interlayer insulating film 16 made of a Si oxide film or the like is formed thereon using a CVD method or the like. It is formed. SOG is a film that utilizes the fluidity of glass at a temperature of about 1000°C.
When forming on the interlayer insulating film 12, first layer wiring 13a, 13b, and dummy wiring 111), the base film is flattened by applying liquid PSG or the like to the base film and fixing the PSG or the like. The aim is to

On the second interlayer insulating film 16, a width d5 (
For example, the second layer wiring 17 having a thickness of about 80 μm or more)
1 mm so as to be almost orthogonal to the first layer wiring 13a, 13b.
It has been extended to a certain extent.

Here, the length d6 of the dummy wiring 14 is the length d6 of the second layer wiring 1
The length is approximately the same as the width d5 of No.7. These first. The second layer wirings 13a, 13b17 are connected to gate electrodes (not shown) or source/drain regions via through holes (not shown). Furthermore, in order to stabilize and protect the surface of the semiconductor device, a passivation film made of a Si nitride film or the like is formed on the first layer wiring 17 using a CVD method or the like. A18 is coated.

In the above configuration, the first. Second layer wiring 13a13b,
When a voltage is applied to 17, a voltage of GaI is applied to the gate electrode, the source/train region becomes conductive, and M
The operation of the OS transistor is performed.

This embodiment has the following advantages.

Each first layer wiring 1: By arranging the dummy wiring 14 between 3a and 13b, each first layer wiring 13a.

Various stresses applied to 13b, for example, 1a-free coating film 1
5. Various types of mechanical stress due to stress inherent in the second interlayer insulating film 16 and the second layer wiring 17, thermal stress due to temperature cycle stress caused by repeatedly applying various heat treatments to the semiconductor device, etc. can relieve stress. In other words, in the past, mainly the first layer wiring 1
3a.

This is because the stress locally concentrated on the edge portions 19a and 19L+ of the dummy wiring 13b can be dispersed to the edge portion 20 of the dummy wiring 1=1.
It becomes possible to prevent the occurrence of defects in a and 13b. In this case, the effect can be expected even more in the first layer wiring 13b, where the unit length of the groove/notch portions 19a and L9b is shorter than that of the first layer wiring 13a, and thus tends to be damaged. As a result, first layer wiring 13a, 13b
This makes it possible to prevent damage to the semiconductor device, such as breakage, and thereby improve the reliability of the semiconductor device, such as migration resistance.

Next, a second embodiment of the present invention will be described.

FIGS. 3(a) and 3(b) are diagrams showing a multilayer wiring structure of a semiconductor device according to a second embodiment of the present invention, in which FIG. 3(a) is a plan view and FIG. 3(b) is a plan view. It is a sectional view taken along the line CC, and elements common to those in FIGS. 1(a) and 1(b) are given the same reference numerals.

This semiconductor device is different from those shown in FIGS. 1(a) and 1(b) in that a plurality of (for example, three) dummy wirings 14a are formed between each first layer wiring 13a, 1'3b. In this case, there is a predetermined distance D? (for example, about 20μ) between each first layer wiring 13a, 13b and the dummy wiring 14a.
m) is set, and a predetermined interval d8 (for example, less than about 20 μm) is set between each dummy wiring 14a.

Even with such a structure, almost the same advantages as in the first embodiment can be obtained, and in addition, in this case, the dummy wiring 1.4
By forming a plurality of wires 13a, the total length of the edge portions 20a increases, so that stress can be further distributed compared to the first embodiment. , 13b can be expected to be more effective in alleviating the stress concentration on them.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. Examples of such modifications include the following.

■ The above embodiment is based on the first example. Second layer wiring 13a.

13b and 17, the semiconductor device may have a multilayer wiring structure having three or more layers of wiring.

(2) The number of dummy wires 14 and 14a arranged between each of the first layer wires 13a and 13b is the same as the number of dummy wires 14 and 14a arranged between the first layer wires 13a and 13b. The number of wires in the second embodiment is not limited to one or three, and it is also possible to set the number to other numbers.

Further, the length d6 of the dummy wiring 14.14a is set to be approximately the same as the width d5 of the second layer wiring 17, but the length d6 can be made longer or shorter as necessary.

■ 1st. Aρ
The pond material may be -8i-Cu (copper) or the like.

■ 1st. Although the structure between the second layer wirings 13a, 13b, and 17 was the inorganic coating film 15/second interlayer insulating film 16, the first.
Depending on changes in the shape of the second layer wirings 13a, 13b, 17, etc., for example, the second interlayer insulating film 167' inorganic coating film 15, or the second interlayer insulating film 16/inorganic coating film 15/second interlayer insulating film 16 It is also possible to do this.

(Effects of the Invention) As described in detail above, according to the present invention, dummy wiring that is electrically unconnected between each first layer wiring immediately below the second layer wiring is formed. Film layer added to wiring 1-
Stresses such as stress and heat stress are alleviated, making it possible to prevent large losses in the first layer wiring, thereby improving reliability such as migration resistance in semiconductor devices. can be expected.

[Brief explanation of the drawing]

1(a) and (b) are diagrams showing a multilayer wiring structure of a semiconductor device according to the first embodiment of the present invention, and FIG. 2(a) and (
b) is a diagram showing the multilayer wiring structure of a conventional semiconductor device;
Figures (a) and (b) are diagrams showing a multilayer wiring structure of a semiconductor device according to a second embodiment of the present invention. 10 ・----S i substrate (substrate), 13a, t3
b...First layer wiring, 16...Second @ interlayer insulating film (interlayer insulating film), 17...Second layer wiring, 1
4.14a...Dummy wiring.

Claims (1)

[Claims] A plurality of first layer wirings are formed on a substrate on which a semiconductor element is formed, and a plurality of first layer wirings are formed on the first layer wirings and intersect with the first layer wirings via an interlayer insulating film. A multilayer wiring structure of a semiconductor device in which a second layer wiring is formed in a direction such that an electrically unconnected dummy wiring is formed between each of the first layer wirings directly below the second layer wiring. multilayer wiring structure of semiconductor devices.