JPH0196960A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a polycrystalline Si MOS field effect transistor having the high breakdown strength of a gate insulating film and less leakage current from its gate electrode by forming the gate insulating film by chemical vapor depositing (CVD) or chemical vapor depositing and then heat treating in an oxidative atmosphere. CONSTITUTION:A thermal oxide film 32 and a polycrystalline Si pattern 33 are formed on a P-type Si substrate 31. Then, an Si3N4 film is deposited 25nm by a CVD method with the thermal decomposition of SiH4 gas and NH3 gas, and then thermally oxidized to form a gate insulating film 34. Thereafter, a gate electrode 35, a PSG film 36 and aluminum wirings 37 are formed. Thus, a polycrystalline Si MOS transistor in which its insulating breakdown strength is improved is obtained as compared with the case that an oxide film having the same thickness as that is employed as the gate insulating film.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to a semiconductor device suitable for improving the gate insulating film breakdown voltage of a polycrystalline SiM OS field effect transistor. The present invention relates to a semiconductor device and its manufacturing method.

[Conventional technology]

IEE, Electron Device Letter ED-L-5 (1984) pp. 468-470 (IEEE II ElectronDe
vice 1etti EDL-5, p, 468
(1984), a thermal oxide film has conventionally been widely used as a gate insulating film of a polycrystalline 51MO8 field effect transistor.

[Problem that the invention seeks to solve]

The above conventional technology does not consider the withstand voltage of the gate insulating film of the polycrystalline 51MO8 field effect transistor.
When a thermal oxide film on polycrystalline Si is used as a gate insulating film, there is a problem in that its dielectric strength is low. Therefore, if the gate insulating film is made thinner in order to increase the mutual conductance of the IMOS transistor, there is a problem in that leakage current from the gate electrode increases. Further, if a gate insulating film is formed by thermal oxidation on a gate electrode made of polycrystalline Si containing a high concentration of impurities, the deterioration of the gate insulating film becomes even greater.

An object of the present invention is to provide a polycrystalline 51MO8 field effect transistor with a high gate insulating film breakdown voltage and extremely low leakage current from the gate electrode, and a method for manufacturing the same.

[Means for solving interlayer points]

The above purpose is to eliminate unevenness at the interface between polycrystalline Si and the insulating film,
This is achieved by forming an insulating film of varying thickness on the top surface, side surfaces, and corner portions of the polycrystalline Si pattern to suppress concentration of the electric field.

To this end, in the present invention, instead of the conventional thermal oxidation film, the gate insulating film is formed of a chemical vapor deposition (CVD) film or a two-layer film in which thermal oxidation is performed after CVD film deposition.

[Effect]

In thermal oxidation of polycrystalline Si, (1) Since oxygen diffuses through the grain boundaries of polycrystalline Si and oxidation progresses, the interface between polycrystalline Si and the oxide film has many irregularities.

■Since the oxidation rate is plane orientation dependent, the film thickness varies depending on the plane orientation.

■The film thickness at the corners of the polycrystalline Si pattern becomes thinner.

For the above reasons, the dielectric strength deteriorates.

Therefore, if a CVD film is used instead of a thermal oxide film, the interface between the polycrystalline Si and the insulating film is smooth because oxidation of grain boundaries does not occur. Furthermore, there is no effect of surface orientation, and the film thickness does not become thinner at the corner portions. Therefore, an extremely uniform film thickness can be obtained.

Due to the above effects, the dielectric strength voltage is improved.

Further, by performing heat treatment in an oxidizing atmosphere after depositing the insulating film by the CVD method, defects can be reduced and the drop in breakdown voltage can be reduced.

〔Example〕

Embodiments of the present invention will be described below with reference to FIGS. 1 to 4.

Example 1 A p-type Si substrate 11 is prepared and thermally oxidized to form a 300 nm 5i
ft film 12 is formed. On top of that, low pressure vapor phase chemical growth (L
A polycrystalline Si film 13 of 1100n is formed by the PGVD method, and CCQ a is formed using a photoresist pattern as a mask.
A polycrystalline Si pattern is formed by dry etching using gas. A 5ins film 14 is deposited to a thickness of 30 nm by a CVD method using thermal decomposition of 5illa gas and NzO gas. Subsequently, B ions are implanted into the polycrystalline Si at 20 KeV with a dose of 1×10 LZC,-2 (first
Figure A).

Next, a 350 nm polycrystalline Sj film is formed by the LPGVD method, and phosphorus diffusion is performed at 875° C. using POCQδ.

Gate electrode 15 is formed by dry etching using CCU 4 gas using the photoresist pattern as a mask. Next, using the self-alignment method using the gate electrode as a mask, As was applied at a dose of 5 x 10 steps at 5 cm at 70 KeV.
''!Ion implantation is performed to form n-type high concentration impurity layers for the source and drain (FIG. 1B).

After heat treatment at 900'C for 60 minutes in a N2 gas atmosphere, a PSG film (phosphosilicate glass) 16 was formed using the CVD method.
A contact hole is formed with a thickness of 0.5 μm by a dry etching method using CHFa gas using the photoresist pattern as a mask. Furthermore, the film thickness is 0.9 μm
After depositing AQ17 of
0℃.

Heat treatment is performed for 30 minutes (FIG. 1C).

In the polycrystalline 51MO8 type transistor manufactured according to this example, the source and drain were grounded, a voltage was applied to the gate electrode, and the leakage current of the gate oxide film was measured, and the voltage was 20 V when the current was 10 nA. When a thermal oxide film of the same thickness at 900°C is used as the gate oxide film, the withstand voltage obtained with the same tI setting is 10V, and C
By using the VD oxide film, we were able to double the breakdown voltage.

Example 2 First, a P-type Si substrate 2 was manufactured using the same manufacturing method as in Example 1.
1, a thermal oxide film 22. A polycrystalline Si pattern 23 is formed. Next, a 25 nm thick 5iOz film was deposited by CVD, followed by thermal oxidation at 900°C to form a Si○2 film 2.
The film thickness of No. 4 is 30 nm.

Hereinafter, the gate electrode 25 is manufactured using the same manufacturing method as in Example 1.
．． PSG film 26. Afl wiring 27 is formed and polycrystalline S
An iMOS type transistor was manufactured.

In this example, as in Example 1, a high breakdown voltage of the gate oxide film was achieved. Furthermore, the capacitor area is 0.01c
m'', the drop in withstand pressure was reduced to 1% or less compared to 5% in Example 1.

Example 3 First, by the same manufacturing method as Example 1 and Example 2,
A thermal oxide film 32 is formed on a p-type Si substrate 31. A polycrystalline Si pattern 33 is formed. Next, S i H4 gas and N Ha
A 5iaNa film was formed by a CVD method using gas thermal decomposition.
5 nm deposited followed by 900°C.

A gate insulating film 34 is formed by thermal oxidation for 20 minutes.

Hereinafter, the gate electrode 35. PSG film 36. AQ wiring 37 was formed to manufacture a polycrystalline 51MO8 type transistor.

In this example, the breakdown voltage of the gate insulating film was 15V.

Also, the drain voltage is 0. IV, the mutual conductance was 5 x 10" (mhos) when the channel length and channel width were 2 μm and 15 μm, respectively. When an oxide film of the same thickness was used as the gate insulating film, the mutual conductance was 2
, 5 x 10''-8 (mhos), which was approximately twice as large.

Example 4 Examples 1 to 3 described above all have a structure in which a gate electrode is provided on a gate insulating film.

In contrast to this structure, this embodiment has a structure in which a gate insulating film is formed on a polycrystalline Si gate electrode containing a high concentration of impurities.

This is an example in which the dielectric strength is improved, and will be explained using FIG. 4.

First, a p-type Si substrate 41 is prepared and thermally oxidized to a thickness of 300 nm.
5iOz film 42 is formed. A 350 nm polycrystalline Si film was deposited on top of it by the LPCVD method, and P
Phosphorus is diffused using OCQ a, and a gate electrode 43 is formed by dry etching using CCQ4 gas using a photoresist pattern as a mask (FIG. 4A).

Next, 5
A 25 nm thick iOz film is deposited, and then thermal oxidation is performed at 900° C. to make the 5iOz film 44 30 nm thick. On top of that, 1100n polycrystalline S is applied by L P CV D method.
Deposit an i film 45 and use a photoresist pattern as a mask
Polycrystalline Si is processed into a predetermined shape by a dry etching method using CQ a gas. Next, by CVD method, S
x O2 film 46 is deposited to a thickness of 30 nm, and B is deposited in polycrystalline Si.
I x 10 "co+-" ion implantation is performed at 20 K e V (FIG. 4B).

Next, using the photoresist pattern 47 as a mask, 5.times.I.sub.Q "am-" ions of As are implanted at 70 KsV to form source/drain n-type high concentration impurity layers (FIG. 4C).

After heat treatment at 900° C. for 60 minutes in a N2 gas atmosphere, a PSG film of 48 tO, 5 μm thick was formed by CVD, and photoresist! - CHF using pattern as mask
Contact holes are formed by dry etching using s gas. Furthermore, a film of Al249 with a thickness of 0.9 μm was deposited, and BCQs and C were deposited using the photoresist pattern as a mask.
After forming a wiring pattern by dry etching using CQ 4 gas, heat treatment is performed at 450° C. for 30 minutes in a hydrogen atmosphere (FIG. 4D).

In this example as well, the dielectric breakdown voltage of the gate oxide film was able to be improved twice as compared to the case of using only a thermal oxide film. Moreover, in a structure like this example in which a thin gate oxide film of 30 nm or less is formed on high-concentration polycrystalline Si, it is difficult to control the film thickness with a thermal oxide film, but with this method using the CVD method, the film thickness can be reduced. control becomes easier.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, polycrystalline 5
The gate insulating film of a 1MO8 type transistor was formed by depositing a CVD film and then heat-treating it in an oxidizing atmosphere, thereby making it possible to double the dielectric strength. Furthermore, the gate insulating film formed in this manner has a low defect density and has less breakdown voltage.

Although this embodiment shows an n-channel field effect transistor, the present invention is not limited thereto, and can also be applied to a p-channel field effect transistor. Further, although the polycrystalline SiMOS transistor is formed on the Sj,02 film, it is not limited thereto, and the present invention can be applied to other conductors and semiconductors.

It is also applicable when formed on an insulator.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of the manufacturing process of Example 1 of the present invention. Figures 2 and 3 are Example 2 and Example 3, respectively.
FIG. FIG. 4 is a sectional view of the manufacturing process of Example 4 of the present invention. 11.21,31,41...p-type Si substrate, 12°2
2.32,42,47...SiO2,13,23゜3
3.45...Polycrystalline Si (active layer), 14,24°3
4.44...Gate insulating film, 15, 25, 35°43
...Polycrystalline Si gate, 16, 26, 36°48...
・PSG passivation film, 17, 27, 37.49・
...Afl.琐 l 口＋＋＋ ＋ψ 4th Σ

Claims (1)

[Claims] 1. In a polycrystalline SiMOS field effect transistor in which the source and drain regions are formed in polycrystalline Si and the current path is made of polycrystalline Si, the gate insulating film is formed by chemical vapor deposition or chemical vapor deposition. What is claimed is: 1. A semiconductor device characterized in that the semiconductor device is formed by heat-treating in an oxidizing atmosphere after forming a semiconductor device.