JPH0186328U

JPH0186328U -

Info

Publication number: JPH0186328U
Application number: JP17988987U
Authority: JP
Priority date: 1987-11-26
Filing date: 1987-11-26
Publication date: 1989-06-07

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例を示すブロツク図
、第２図はこの実施例の動作を示す信号波形図、
第３図は従来の逐次比較型Ａ／Ｄ変換回路、第４
図は第３図のＤ／Ａ変換器内の入出力変換特性図
、第５図は第３図のＡ／Ｄ変換回路の動作を示す
信号波形図である。１……Ｄ／Ａ変換器、２……逐次比較レジスタ
、３……アナログアンプ、４……入力端子、１０
……Ａ／Ｄ変換部、１１……アナログ加算器、１
２……デジタル減算器、１３……オフセツト入力
端子、１４……デジタルオフセツト値。 FIG. 1 is a block diagram showing an embodiment of this invention, and FIG. 2 is a signal waveform diagram showing the operation of this embodiment.
Figure 3 shows a conventional successive approximation type A/D conversion circuit;
3 is an input/output conversion characteristic diagram in the D/A converter of FIG. 3, and FIG. 5 is a signal waveform diagram showing the operation of the A/D conversion circuit of FIG. 3. 1... D/A converter, 2... Successive approximation register, 3... Analog amplifier, 4... Input terminal, 10
...A/D converter, 11...Analog adder, 1
2...Digital subtracter, 13...Offset input terminal, 14...Digital offset value.

Claims

[Scope of utility model registration request]

An analog adder that adds a predetermined DC offset to an analog input, and an A/D that inputs the output of this analog adder and converts it into a digital signal.
An analog-to-digital conversion circuit comprising a conversion section and a digital subtracter that subtracts a digital value corresponding to the DC offset from the digital output of the A/D conversion section.