JPH01290229A - Semiconductor wafer - Google Patents

Semiconductor wafer

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Publication number
JPH01290229A
JPH01290229A JP12111788A JP12111788A JPH01290229A JP H01290229 A JPH01290229 A JP H01290229A JP 12111788 A JP12111788 A JP 12111788A JP 12111788 A JP12111788 A JP 12111788A JP H01290229 A JPH01290229 A JP H01290229A
Authority
JP
Japan
Prior art keywords
wafer
crystal
oxygen
wafers
crystal wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12111788A
Other languages
Japanese (ja)
Inventor
Mitsuru Hanakura
満 花倉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
Original Assignee
Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meidensha Corp, Meidensha Electric Manufacturing Co Ltd filed Critical Meidensha Corp
Priority to JP12111788A priority Critical patent/JPH01290229A/en
Publication of JPH01290229A publication Critical patent/JPH01290229A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obtain a semiconductor wafer adapted to a starting material of a device high in the degree of integration by a method wherein a silicon single crystal wafer formed through an FZ method and a single crystal wafer formed through a CZ method or an MCZ method are bonded to each other into one piece. CONSTITUTION:One side of an FZ crystal wafer 1 formed through an FZ (floating zone) method whose oxygen concentration is 5X10<17>atom/cm<2> or less is optically abraded to be formed into a mirror surface 1a and concurrently, for instance, one side of a CZ crystal wafer 2 formed through an MCZ method whose oxygen concentration is 5X10<17> or more is also optically abraded to be formed into a mirror surface 2a. And, wafers 1 and 2 are directly joined together into one piece making the mirror surfaces 1a and 2a adhere to each other. Therefore, a device section is formed of an FZ crystal which scarcely contains oxygen, so that a defect caused by the separation of oxygen is prevented from occurring. By these processes, a semiconductor wafer adapted to a starting material of a device high in the degree of integration can be obtained.

Description

【発明の詳細な説明】 A、産業上の利用分野 本発明は半導体ウェハに係り、特にMOSデバイス等の
半導体素子の出発材料として好適な半導体ウェハに関す
る。
DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to semiconductor wafers, and particularly to semiconductor wafers suitable as starting materials for semiconductor elements such as MOS devices.

B9発明の概要 本発明は、デバイス製造の出発材料といて用いられるシ
リコン単結晶ウェハにおいて、FZ法によって作られた
シリコン単結晶ウェハとC2法又はMCZ法によって作
られた単結晶ウェハを接着して一体化することにより、
集積度の高いデバイスの出発材料に適した半導体ウェハ
を得るものである。
B9 Summary of the Invention The present invention is a silicon single crystal wafer used as a starting material for device manufacturing, by bonding a silicon single crystal wafer made by the FZ method and a single crystal wafer made by the C2 method or the MCZ method. By integrating,
A semiconductor wafer suitable as a starting material for highly integrated devices is obtained.

C0従来の技術 集積回路(IC)や大規模集積回路(LSI)のMOS
デバイスでは、デバイス製造の出発材料としてシリコン
単結晶ウェハが主に用いられている。シリコン単結晶ウ
ェハは、その製法により大別してC2法(Czochr
alshi法)、MCZ法およびFZ法(Floati
ng  Zone法)の3種類に分類される。ICやL
SIのMOSデバイスでは、主にC2結晶ウエハが用い
られ、一部MCZ結晶ウェハも用いられるようになって
いる。
C0 Conventional technology Integrated circuit (IC) and large-scale integrated circuit (LSI) MOS
In devices, silicon single crystal wafers are mainly used as the starting material for device manufacturing. Silicon single-crystal wafers are roughly divided into two manufacturing methods: C2 method (Czochr method)
alshi method), MCZ method and FZ method (Floati method)
It is classified into three types: ng Zone method). IC and L
In SI MOS devices, C2 crystal wafers are mainly used, and some MCZ crystal wafers are also used.

CZ結晶ウェハの特徴は結晶内の酸素濃度が高いことで
、このため機械的強度が大きいという利点を持つが、同
時にOS F (Oxidation  Induce
dStaching  Fault)を始めとする結晶
欠陥が酸素の析出物によって発生しやすく、さらに発生
した結晶欠陥部に汚染不純物が吸収され易いという大き
な欠点がある。
A CZ crystal wafer is characterized by a high oxygen concentration within the crystal, which has the advantage of high mechanical strength, but at the same time
Crystal defects such as dStaching Faults are likely to occur due to oxygen precipitates, and furthermore, contaminating impurities are likely to be absorbed into the generated crystal defects, which is a major drawback.

この欠点を解決するために、I G (Instrin
sicGeLtering)ウェハやエビ(Epita
xial  Grouth)ウェハが考案され、使用さ
れてきた。IGウェハは複雑な熱処理によりウェハ表面
近傍の層より酸素を追い出し、いわゆるデヌーデッド・
ゾーン(denuded  zone)とし、ウェハ内
部の層に酸素の析出物を発生させたものである。それ故
、IGウェハを用いて表面層にMOSデバイス等を形成
すれば、デバイス部には酸素の析出による欠陥は発生せ
ず、さらに汚染不純物はデバイス部を形成しない内部の
層に吸い取られる(ゲッタリング作用)という利点があ
る。
In order to solve this drawback, I G (Instrin
sicGeLtering) wafers and shrimp (Epita)
xial growth) wafers have been devised and used. IG wafers undergo a complex heat treatment to expel oxygen from layers near the wafer surface, resulting in so-called denuded wafers.
This is a denuded zone in which oxygen precipitates are generated in a layer inside the wafer. Therefore, if a MOS device or the like is formed on the surface layer using an IG wafer, defects due to oxygen precipitation will not occur in the device area, and contaminant impurities will be absorbed into the internal layer that does not form the device area (getter). It has the advantage of ring action).

エビウェハは、ウェハ表面に酸素を含まないエピタキシ
ャル成長層を形成することによって、■Gウェハと同様
な効果をねらったものである。
The shrimp wafer aims to achieve the same effect as the ■G wafer by forming an epitaxial growth layer that does not contain oxygen on the wafer surface.

D1発明が解決しようとする課題 1Gウエハ及びエビウェハは酸素濃度の少ない(デバイ
スを形成する)表面層の厚みが数μmと薄いため、次の
ような欠点があった。
D1 Problems to be Solved by the Invention Since the 1G wafer and shrimp wafer have a surface layer with a low oxygen concentration (forming a device) that is as thin as several μm, they have the following drawbacks.

(1a)デバイスの製造プロセスによっては、内部の酸
素析出層より逆に結晶欠陥がわき出してきて、表面層の
結晶性を損なってしまう。
(1a) Depending on the device manufacturing process, crystal defects may come out from the internal oxygen precipitated layer, impairing the crystallinity of the surface layer.

(lb)ウェハ内部の酸素が外方拡散により表面層を通
過する際に、微小な欠陥を発生させる。
(lb) When oxygen inside the wafer passes through the surface layer by outward diffusion, minute defects are generated.

以上のような欠点は、MOSデバイスの集積度が向上す
るにつれ(つまり微細化が進むにつれ)、ウェハの歩留
まりを悪くする致命的問題として注目されてきた。
As the degree of integration of MOS devices increases (that is, as miniaturization progresses), the above-mentioned drawbacks have been attracting attention as critical problems that reduce the yield of wafers.

またMCZウェハにおいても、この酸素析出物の問題に
関しては同様である。
The problem of oxygen precipitates is also the same for MCZ wafers.

FZウェハはCZウェハに比べて、酸素濃度が3桁低く
、酸素析出物という観点からはほとんど無視してよい量
しか酸素を含有していない。それでMOSデバイスの高
集積化のためにはFZ結晶ウェハが適していると思われ
る。
The FZ wafer has an oxygen concentration three orders of magnitude lower than the CZ wafer, and contains oxygen in an almost negligible amount from the viewpoint of oxygen precipitates. Therefore, FZ crystal wafers are considered suitable for increasing the integration of MOS devices.

しかしながら、FZウェハは次のような欠点のために、
従来のMOSデバイスの出発材料として、はとんど用い
られていなかった。
However, FZ wafers have the following drawbacks:
It has rarely been used as a starting material for conventional MOS devices.

(2a)酸素の含有量がきわめて少ないため、機械的強
度が弱い。
(2a) Mechanical strength is weak due to extremely low oxygen content.

(2b)酸素の含有量がきわめて少ないため、転位が発
生しやすく、さらに成長しやすい。
(2b) Since the content of oxygen is extremely low, dislocations are likely to occur and grow more easily.

(2C)IGウェハ等のように、汚染不純物をデバイス
を形成しない部分に吸いとる作用(ゲッタリング作用)
がない。
(2C) Effect of absorbing contaminant impurities into areas where devices are not formed, such as IG wafers (gettering effect)
There is no.

本発明は上述の問題点を解決したもので、その目的は、
酸素をほとんど含まないFZ結晶ウェハに、結晶内の酸
素濃度の高いCZ結晶ウェハを接着させることにより、
FZ結晶ウェハの欠点をCZ結晶ウェハで補うことがで
きる半導体ウェハを提供することである。
The present invention solves the above-mentioned problems, and its purpose is to:
By bonding a CZ crystal wafer with a high concentration of oxygen in the crystal to an FZ crystal wafer that contains almost no oxygen,
It is an object of the present invention to provide a semiconductor wafer that can compensate for the drawbacks of an FZ crystal wafer with a CZ crystal wafer.

E1課題を解決するための手段 本発明は、上述の目的を達成するために、FZ法により
製作した酸素濃度が5X10”原子/cx3以下のシリ
コン単結晶ウェハとCZ法又はMCZ法により作られた
酸素濃度が5X10”以上のシリコン単結晶ウエノ\と
を接着により一体化する。
E1 Means for Solving the Problems In order to achieve the above-mentioned objects, the present invention uses a silicon single crystal wafer with an oxygen concentration of 5x10'' atoms/cx3 or less manufactured by the FZ method and a silicon single crystal wafer manufactured by the CZ method or MCZ method. It is integrated with silicon single crystal Ueno\ with an oxygen concentration of 5 x 10'' or more by adhesion.

F5作用 デバイス部は、酸素をほとんど含有しないFZ結晶に形
成されるので、酸素の析出による欠陥が発生しない。ま
た、汚染不純物をデバイスを形成しない層(CZ結晶層
)に吸い取る作用(ゲ・ツタリング作用)をする。
Since the F5 action device portion is formed of FZ crystal containing almost no oxygen, defects due to oxygen precipitation do not occur. It also acts to absorb contaminant impurities into a layer (CZ crystal layer) that does not form a device (ge-stuttering effect).

G、実施例 以下に本発明の実施例を第1図〜第2図を参照しながら
説明する。
G. Examples Examples of the present invention will be described below with reference to FIGS. 1 and 2.

第1図(A)〜(C)は本発明の第1実施例の半導体ウ
ェハを製造する工程を示し、この実施例により半導体ウ
ェハは、第1図(A)に示すように、FZ結晶ウェハ1
の一方の面を光学研磨して表面粗さ500Å以下の鏡面
1aを形成すると共に、CZ結晶ウェハ2の一方の面を
同様に光学研磨して表面粗さ500Å以下の鏡面2aを
形成する。これらのウェハを直接接合により鏡面どうし
を密着させて接着する。具体的には、FZ結晶ウェハ1
とC2結晶ウェハ2を純水洗浄した後スピンナー乾燥し
、表面にOH基を残したまま両ウェハの鏡面どうしを第
1図(B)に示すように密着させ、200〜1200℃
の温度で加熱処理する。
FIGS. 1(A) to (C) show the steps of manufacturing a semiconductor wafer according to the first embodiment of the present invention. According to this embodiment, the semiconductor wafer is an FZ crystal wafer as shown in FIG. 1(A). 1
One side of the CZ crystal wafer 2 is optically polished to form a mirror surface 1a with a surface roughness of 500 Å or less, and one side of the CZ crystal wafer 2 is similarly optically polished to form a mirror surface 2a with a surface roughness of 500 Å or less. These wafers are directly bonded with their mirror surfaces brought into close contact with each other. Specifically, FZ crystal wafer 1
After cleaning the C2 crystal wafer 2 with pure water, it was dried using a spinner, and the mirror surfaces of both wafers were brought into close contact with each other as shown in FIG.
heat-treated at a temperature of

次に、第1図(C)に示すように、接着したFZ結晶側
を光学研磨して鏡面1bを形成する。FZウェハ1は酸
素濃度が5X1017原子/ax’以下であり、CZウ
ェハ2は酸素濃度が5X10”原子/CJI3以上であ
る。
Next, as shown in FIG. 1C, the bonded FZ crystal side is optically polished to form a mirror surface 1b. The FZ wafer 1 has an oxygen concentration of 5X1017 atoms/ax' or less, and the CZ wafer 2 has an oxygen concentration of 5X10" atoms/CJI3 or more.

さらに、本発明のその他の実施例として、以下のものが
ある。
Further, other embodiments of the present invention include the following.

(1)FZ結晶ウつノ\の代わりに、中性子照射により
抵抗率をより均一に制御したNTD−FZ結晶ウェハを
用いたもの。
(1) An NTD-FZ crystal wafer whose resistivity is more uniformly controlled by neutron irradiation is used instead of the FZ crystal Utsuno.

(2)CZウェハの代わりに、酸素濃度が5X10”原
子/ax3以上のMCZC2結晶ウェハ2いたもの。
(2) Instead of the CZ wafer, an MCZC2 crystal wafer 2 with an oxygen concentration of 5×10” atoms/ax3 or more was used.

(3)酸素濃度の差によるそり等の発生を防ぐため、第
2図に示すようにさらにFZ結晶ウつノ\3をCZウェ
ハ2に接着させたもの。
(3) In order to prevent the occurrence of warping due to the difference in oxygen concentration, FZ crystal Utsuno 3 is further bonded to the CZ wafer 2 as shown in FIG.

本発明により作成したFZ結晶とCZ結晶の合成ウェハ
を用い、FZ結晶側の面にMOSデ1<イスを形成すれ
ば以下のような効果が生ずる。
If a MOS device is formed on the FZ crystal side using a composite wafer of FZ crystal and CZ crystal produced according to the present invention, the following effects will be produced.

(3a)デバイス部は、酸素をほとんど含有しないFZ
結晶に形成されるので、酸素の析出による欠陥は発生し
ない。
(3a) The device part is made of FZ containing almost no oxygen
Since it is formed into a crystal, defects due to oxygen precipitation do not occur.

(3b)IGウェハやエピウェハと異なり、酸素をほと
んど含有しない層つまりFZ結晶層は数100μmと厚
いので、デバイスの製造プロセスにより内部の酸素析出
層(C2結晶層)より逆に結晶欠陥がデバイス部までわ
き出してこない。また同じ理由でウェハ内部(CZ結晶
部)の酸素が外方拡散によりデバイス部まで拡散してく
る事がないのでIGウェハやエビウェハのようにデバイ
ス部に微小な欠陥が発生しない。
(3b) Unlike IG wafers and epitaxial wafers, the layer containing almost no oxygen, that is, the FZ crystal layer, is as thick as several 100 μm, so the device manufacturing process causes crystal defects to occur in the device part rather than in the internal oxygen precipitated layer (C2 crystal layer). It doesn't come out until then. Further, for the same reason, oxygen inside the wafer (CZ crystal part) does not diffuse outward to the device part, so that micro defects do not occur in the device part unlike IG wafers and shrimp wafers.

(3c)酸素含有量の多いC2結晶層をもつために、機
械的強度が強い。
(3c) It has high mechanical strength because it has a C2 crystal layer with a high oxygen content.

(3d)酸素含有量の多いCZ結晶層をもつために、転
位が発生、成長しにくい。
(3d) Since it has a CZ crystal layer with a high oxygen content, it is difficult for dislocations to occur and grow.

(3e)汚染不純物をデバイスを形成しない層(CZ結
晶層)に吸いとる作用(ゲッタリング作用)がある。
(3e) There is an effect (gettering effect) of absorbing contaminant impurities into a layer (CZ crystal layer) that does not form a device.

以上の効果により、本発明によるシリコン単結晶ウェハ
は、従来用いられてきたIGウニ/%やエビウェハなど
のCZ結晶ウェハにくらべて、高集積化された(具体的
には0.5μmルール以上の集積度の)MOSデバイス
の出発材料として適している。
As a result of the above effects, the silicon single crystal wafer according to the present invention has a higher degree of integration than conventionally used CZ crystal wafers such as IG sea urchin/% and shrimp wafers (specifically, 0.5 μm rule or more). It is suitable as a starting material for MOS devices (with high integration density).

■■1発明の効果 本発明は以上の如くであって、酸素をほとんど含有しな
いFZ結晶ウェハに、結晶内の酸素濃度の高いCZ結晶
ウェハを接着させて一体としたから、集積度の高いデバ
イスの出発材料に適した半導体ウェハを得ることができ
る。
■■1 Effects of the Invention The present invention is as described above, and since a CZ crystal wafer with a high oxygen concentration in the crystal is bonded to an FZ crystal wafer containing almost no oxygen and integrated, a device with a high degree of integration can be obtained. A semiconductor wafer suitable for the starting material can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例による半導体ウェハの製作工程
を示す説明図、第2図は本発明の他の実施例による半導
体ウェハの構成図である。 ■・・・FZ結晶ウェハ、2・・・CZ結晶ウェハ、3
・・・FZ結晶ウェハ。 ■ 1.3・FZ結晶ウェハ I a、 I b・−鏡面         他′)フ
2 ・CZ結晶ウェハ 2a・鏡面 第1図 施例の半導体ウェハ 第2図 (施例による半導体ウェハ
FIG. 1 is an explanatory diagram showing the manufacturing process of a semiconductor wafer according to an embodiment of the present invention, and FIG. 2 is a diagram showing the configuration of a semiconductor wafer according to another embodiment of the present invention. ■...FZ crystal wafer, 2...CZ crystal wafer, 3
...FZ crystal wafer. ■ 1.3・FZ crystal wafer Ia, Ib・-mirror surface, etc.)

Claims (1)

【特許請求の範囲】[Claims] (1)FZ法により製作した酸素濃度が5×10^1^
7原子/cm^3以下のシリコン単結晶ウェハとCZ法
又はMCZ法により作られた酸素濃度が5×10^1^
7以上のシリコン単結晶ウェハとを接着により一体化し
たことを特徴とする半導体ウェハ。
(1) Manufactured by FZ method with oxygen concentration of 5×10^1^
Silicon single crystal wafer with 7 atoms/cm^3 or less and an oxygen concentration of 5 x 10^1^ made by CZ method or MCZ method
A semiconductor wafer characterized by being integrated with a silicon single crystal wafer of 7 or more by adhesion.
JP12111788A 1988-05-18 1988-05-18 Semiconductor wafer Pending JPH01290229A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12111788A JPH01290229A (en) 1988-05-18 1988-05-18 Semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12111788A JPH01290229A (en) 1988-05-18 1988-05-18 Semiconductor wafer

Publications (1)

Publication Number Publication Date
JPH01290229A true JPH01290229A (en) 1989-11-22

Family

ID=14803306

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12111788A Pending JPH01290229A (en) 1988-05-18 1988-05-18 Semiconductor wafer

Country Status (1)

Country Link
JP (1) JPH01290229A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5273917A (en) * 1989-08-19 1993-12-28 Fuji Electric Co., Ltd. Method for manufacturing a conductivity modulation MOSFET
US6676748B1 (en) 1999-11-17 2004-01-13 Denso Corporation Method for manufacturing semiconductor substrate
JP2005005708A (en) * 2003-06-11 2005-01-06 Soi Tec Silicon On Insulator Technologies Method for manufacturing heterogeneous structure
US7784603B2 (en) 2005-09-03 2010-08-31 Krones Ag Gripping device for containers

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01259539A (en) * 1988-04-11 1989-10-17 Fujitsu Ltd Soi substrate and manufacture thereof

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01259539A (en) * 1988-04-11 1989-10-17 Fujitsu Ltd Soi substrate and manufacture thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5273917A (en) * 1989-08-19 1993-12-28 Fuji Electric Co., Ltd. Method for manufacturing a conductivity modulation MOSFET
US6676748B1 (en) 1999-11-17 2004-01-13 Denso Corporation Method for manufacturing semiconductor substrate
US7220654B2 (en) 1999-11-17 2007-05-22 Denso Corporation Method for manufacturing semiconductor substrate
US7754580B2 (en) 1999-11-17 2010-07-13 Denso Corporation Method for manufacturing semiconductor substrate
JP2005005708A (en) * 2003-06-11 2005-01-06 Soi Tec Silicon On Insulator Technologies Method for manufacturing heterogeneous structure
US7784603B2 (en) 2005-09-03 2010-08-31 Krones Ag Gripping device for containers

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