JPH01282839A - Manufacture of element isolation - Google Patents

Manufacture of element isolation

Info

Publication number
JPH01282839A
JPH01282839A JP11319088A JP11319088A JPH01282839A JP H01282839 A JPH01282839 A JP H01282839A JP 11319088 A JP11319088 A JP 11319088A JP 11319088 A JP11319088 A JP 11319088A JP H01282839 A JPH01282839 A JP H01282839A
Authority
JP
Japan
Prior art keywords
polycrystalline silicon
oxide film
element isolation
film
nitride film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11319088A
Other languages
Japanese (ja)
Inventor
Keimei Mikoshiba
御子柴 啓明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP11319088A priority Critical patent/JPH01282839A/en
Publication of JPH01282839A publication Critical patent/JPH01282839A/en
Pending legal-status Critical Current

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  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To inhibit the generation of a bird beak by forming a polycrystalline silicon sidewall onto the side face of a nitride film. CONSTITUTION:A nitride film 3 is grown onto an silicon substrate 1 through an oxide film 2. The nitride film in an element isolation region 4 is etched, polycrystalline silicon 5 is grown, and polycrystalline silicon sidewalls 6 are shaped onto the side faces of the nitride films 3 through anisotropic silicon etching. The substrate 1 is thermally oxidized. No bird beak is generated among the nitride films 3 and the substrate 1 because the sidewalls 6 are oxidized. Protrusions 9 generated by the oxidation of the sidewalls 6 are formed to all oxide film 7. The protrusions 9 shape a flattened film 8, and are removed through etchback. Lastly, an oxide film 10 flattened to mask dimensions is formed. Accordingly, the generation of the bird beak is inhibited.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の素子分離製造方法に関し、特に1
μm以下の微細素子分離の形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing semiconductor devices with element isolation, and in particular, 1.
The present invention relates to a method for forming fine element isolation of micrometers or less.

〔従来の技術〕[Conventional technology]

従来、この種の素子分離ではLOCO8法が用いられて
いる。すなわち、第4図(a)に示すように、酸化膜2
を回してシリコン基板l上に窒fF33を設け、次に第
4図(b)に示すようにこの窒化膜3をマスクにしてシ
リコン基板1を酸化して素子分離領域を形成する。
Conventionally, the LOCO8 method has been used for this type of element isolation. That is, as shown in FIG. 4(a), the oxide film 2
Then, as shown in FIG. 4(b), the silicon substrate 1 is oxidized using the nitride film 3 as a mask to form an element isolation region.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のLOCO3法は、バーズビークと呼ばれ
る酸化膜のくい込み16が生ずるため、実効的な素子分
離領域が広がってしまい、微細な素子分離領域が形成で
きないという欠点がある。
The above-mentioned conventional LOCO3 method has the drawback that the effective element isolation region expands because the oxide film bite 16 called a bird's beak occurs, making it impossible to form a fine element isolation region.

〔課題を解決するための手段〕[Means to solve the problem]

本発明によれば、窒化膜をマスクにして選択酸化をし素
子分離領域を形成する方法において、窒化膜の側面に多
結晶シリコン側壁を設けてからシリコン基板を選択的に
酸化する工程を含む素子分離の製造方法が得られる。
According to the present invention, a method for forming an element isolation region by performing selective oxidation using a nitride film as a mask includes a step of providing a polycrystalline silicon sidewall on the side surface of a nitride film and then selectively oxidizing a silicon substrate. A separation manufacturing method is obtained.

本発明では窒化膜の側面に多結晶シリコンの側壁を設け
ておくから、この多結晶シリコンが酸化されることによ
り、バーズビークの発生が抑制される。
In the present invention, since a side wall of polycrystalline silicon is provided on the side surface of the nitride film, the occurrence of bird's beak is suppressed by oxidizing the polycrystalline silicon.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図(a)〜(g)は、本発明の第1の実施例の一製
造方法を示す断面図である。シリコン基板1上に20〜
50μm厚の酸化膜2を介して窒化膜3を成長する(第
1図(a))。窒化膜の厚さは0.1μm〜0.3μm
程度が望ましい。次に素子分離領域4の窒化膜をエツチ
ングした後(第1図(b))、多結晶シリコン5を成長
しく第1図(C乃、異方性シリコンエツチングによって
多結晶シリコン側壁6を窒化膜の側面に形成する(第1
図(d))。次にシリコン基板1を熱酸化する。熱酸化
は、多結晶シリコン側壁6が完全に酸化される程度に行
う。
FIGS. 1(a) to 1(g) are cross-sectional views showing one manufacturing method of the first embodiment of the present invention. 20~ on silicon substrate 1
A nitride film 3 is grown through an oxide film 2 with a thickness of 50 μm (FIG. 1(a)). The thickness of the nitride film is 0.1 μm to 0.3 μm
degree is desirable. Next, after etching the nitride film in the element isolation region 4 (FIG. 1(b)), the polycrystalline silicon 5 is grown. (first
Figure (d)). Next, silicon substrate 1 is thermally oxidized. The thermal oxidation is performed to such an extent that the polycrystalline silicon sidewall 6 is completely oxidized.

バーズビークは多結晶シリコン側壁が酸化されることに
より、窒化膜3と基板1の間に発生しない。
Bird's beaks do not occur between the nitride film 3 and the substrate 1 because the polycrystalline silicon sidewalls are oxidized.

酸化膜7には、多結晶シリコン側壁6が酸化されること
によって生ずる突起9ができる。この突起は平坦化膜8
を形成(第1図(f)) L、エツチングバックにより
除去できる。最後にマスク寸法通りの平坦化された酸化
膜10が形成される(第1図(g))。
Protrusions 9 are formed in the oxide film 7 due to the oxidation of the polycrystalline silicon sidewalls 6. This protrusion is the flattening film 8
(FIG. 1(f)) L can be removed by etching back. Finally, a planarized oxide film 10 having the dimensions of the mask is formed (FIG. 1(g)).

第2図(a)〜(c)は、本発明の第2の実施例の断面
図である。素子分離領域のシリコン基板1をわずか(例
えば0.1〜0.4μm)エツチングし、シリコン溝1
1を形成する。次に溝11の側面に多結晶シリコン側壁
13を形成した後、選択酸化を行い酸化膜14を形成す
る。この実施例では、あらかじめ素子分離領域をエツチ
ングしておくため、シリコン基板1に深く入り込んだ素
子分離領域が形成できる利点がある。深い分離領域は、
素子間隔が狭くなったときの分離特性を著しく改善する
。酸化膜12は多結晶シリコンエッチのストッパーとし
て設けであるが、無くても良い。酸化膜が無い方が、バ
ーズビークの発生はより抑制される。
FIGS. 2(a) to 2(c) are cross-sectional views of a second embodiment of the present invention. The silicon substrate 1 in the element isolation region is slightly etched (for example, 0.1 to 0.4 μm) to form silicon grooves 1.
form 1. Next, after forming polycrystalline silicon sidewalls 13 on the side surfaces of trench 11, selective oxidation is performed to form oxide film 14. In this embodiment, since the element isolation region is etched in advance, there is an advantage that the element isolation region can be formed deeply into the silicon substrate 1. The deep separation region is
Significantly improves isolation characteristics when the element spacing becomes narrow. Although the oxide film 12 is provided as a stopper for polycrystalline silicon etching, it may be omitted. When there is no oxide film, the occurrence of bird's beak is more suppressed.

第3図は、本発明の第3の実施例の断面図である。窒化
膜3が薄いと、多結晶シリコン側壁が形成しにくくなる
。そこで、CVD酸化膜15を窒化膜上に形成し、段差
をつけて多結晶側壁6が容易に形成できるようにする。
FIG. 3 is a sectional view of a third embodiment of the invention. If the nitride film 3 is thin, it becomes difficult to form polycrystalline silicon sidewalls. Therefore, a CVD oxide film 15 is formed on the nitride film with a step difference so that the polycrystalline sidewall 6 can be easily formed.

さらに、多結晶シリコン側壁6は、シリコン基板1に直
接接触させる。
Furthermore, the polycrystalline silicon sidewall 6 is brought into direct contact with the silicon substrate 1.

これにより、バーズビークの発生をほとんどなくすこと
ができる。
This can almost eliminate the occurrence of bird's beak.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、窒化膜の側面に多結晶シ
リコン側壁を設けることにより、バーズビークの発生を
抑えることができる効果がある。
As described above, the present invention has the effect of suppressing the occurrence of bird's beak by providing polycrystalline silicon sidewalls on the side surfaces of the nitride film.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(g)は本発明の第1の実施例を説明す
る素子断面図、第2図(a)〜(c)は本発明の第2の
実施例を説明する素子断面図、第3図は本発明の第3の
実施例を説明する素子断面図、第4図(a) 、 (b
)は従来の素子分離領域の形成方法を示す断面図である
。 1・・・・・・シリコン基板、2・・・・・・酸化膜、
3・・・・・・窒化膜、4・・・・・・素子分離領域、
5・・・・・・多結晶シリコン、6・・・・・・多結晶
シリコン側壁、7・・・・・・酸化膜、8・・・・・・
平坦化膜、9・・・・・・突起、10・・・・・・平坦
化された酸化膜、11・・・・・・シリコン溝、12・
・・・・・酸化膜、13・・・・・・多結晶シリコン側
壁、14・・・・・・酸化膜、15・・・・・・CVD
酸化膜、16・・・・・・バーズビーク。 代理人 弁理士  内 原   音 箔1国 号2図
FIGS. 1(a) to (g) are cross-sectional views of an element explaining a first embodiment of the present invention, and FIGS. 2(a) to (c) are cross-sectional views of an element explaining a second embodiment of the present invention. Figures 3 and 3 are cross-sectional views of elements explaining a third embodiment of the present invention, and Figures 4 (a) and (b).
) is a cross-sectional view showing a conventional method of forming an element isolation region. 1... Silicon substrate, 2... Oxide film,
3...Nitride film, 4...Element isolation region,
5... Polycrystalline silicon, 6... Polycrystalline silicon side wall, 7... Oxide film, 8...
Flattening film, 9... Protrusion, 10... Flattened oxide film, 11... Silicon groove, 12...
... Oxide film, 13 ... Polycrystalline silicon side wall, 14 ... Oxide film, 15 ... CVD
Oxide film, 16...Bird's beak. Agent Patent Attorney Uchihara Otohaku 1 Country No. 2 Diagram

Claims (1)

【特許請求の範囲】[Claims]  窒化膜をマスクにして選択酸化をし、素子分離領域を
形成する方法において、前記窒化膜の側面に多結晶シリ
コン側壁を設けてからシリコン基板を選択的に酸化する
工程を含むことを特徴とする素子分離の製造方法
A method of selectively oxidizing using a nitride film as a mask to form an element isolation region, the method comprising the step of providing a polycrystalline silicon sidewall on the side surface of the nitride film and then selectively oxidizing the silicon substrate. Manufacturing method for element isolation
JP11319088A 1988-05-09 1988-05-09 Manufacture of element isolation Pending JPH01282839A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11319088A JPH01282839A (en) 1988-05-09 1988-05-09 Manufacture of element isolation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11319088A JPH01282839A (en) 1988-05-09 1988-05-09 Manufacture of element isolation

Publications (1)

Publication Number Publication Date
JPH01282839A true JPH01282839A (en) 1989-11-14

Family

ID=14605838

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11319088A Pending JPH01282839A (en) 1988-05-09 1988-05-09 Manufacture of element isolation

Country Status (1)

Country Link
JP (1) JPH01282839A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4109184A1 (en) * 1990-11-17 1992-05-21 Samsung Electronics Co Ltd METHOD FOR FORMING A FIELD OXIDE LAYER OF A SEMICONDUCTOR COMPONENT
JPH08153777A (en) * 1994-11-29 1996-06-11 Nec Corp Manufacture of semiconductor device
US5629230A (en) * 1995-08-01 1997-05-13 Micron Technology, Inc. Semiconductor processing method of forming field oxide regions on a semiconductor substrate utilizing a laterally outward projecting foot portion
US5656537A (en) * 1994-11-28 1997-08-12 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a semiconductor device having SOI structure
US5753962A (en) * 1996-09-16 1998-05-19 Micron Technology, Inc. Texturized polycrystalline silicon to aid field oxide formation
US6306726B1 (en) 1999-08-30 2001-10-23 Micron Technology, Inc. Method of forming field oxide
US6417093B1 (en) 2000-10-31 2002-07-09 Lsi Logic Corporation Process for planarization of metal-filled trenches of integrated circuit structures by forming a layer of planarizable material over the metal layer prior to planarizing
US6586814B1 (en) 2000-12-11 2003-07-01 Lsi Logic Corporation Etch resistant shallow trench isolation in a semiconductor wafer
US6613651B1 (en) * 2000-09-05 2003-09-02 Lsi Logic Corporation Integrated circuit isolation system
US6617251B1 (en) 2001-06-19 2003-09-09 Lsi Logic Corporation Method of shallow trench isolation formation and planarization

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4109184A1 (en) * 1990-11-17 1992-05-21 Samsung Electronics Co Ltd METHOD FOR FORMING A FIELD OXIDE LAYER OF A SEMICONDUCTOR COMPONENT
JPH04234146A (en) * 1990-11-17 1992-08-21 Samsung Electron Co Ltd Formation method of field oxide film for semiconductor device
US5472905A (en) * 1990-11-17 1995-12-05 Samsung Electronics Co., Ltd. Method for forming a field oxide layer of a semiconductor integrated circuit device
DE4109184C2 (en) * 1990-11-17 1995-12-21 Samsung Electronics Co Ltd Method for forming a field oxide layer of a semiconductor device
US5656537A (en) * 1994-11-28 1997-08-12 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a semiconductor device having SOI structure
JPH08153777A (en) * 1994-11-29 1996-06-11 Nec Corp Manufacture of semiconductor device
US5629230A (en) * 1995-08-01 1997-05-13 Micron Technology, Inc. Semiconductor processing method of forming field oxide regions on a semiconductor substrate utilizing a laterally outward projecting foot portion
US6114218A (en) * 1996-09-16 2000-09-05 Microm Technology, Inc. Texturized polycrystalline silicon to aid field oxide formation
US5753962A (en) * 1996-09-16 1998-05-19 Micron Technology, Inc. Texturized polycrystalline silicon to aid field oxide formation
US6306726B1 (en) 1999-08-30 2001-10-23 Micron Technology, Inc. Method of forming field oxide
US6326672B1 (en) 1999-08-30 2001-12-04 Micron Technology, Inc. LOCOS fabrication processes and semiconductive material structures
US6613651B1 (en) * 2000-09-05 2003-09-02 Lsi Logic Corporation Integrated circuit isolation system
US6417093B1 (en) 2000-10-31 2002-07-09 Lsi Logic Corporation Process for planarization of metal-filled trenches of integrated circuit structures by forming a layer of planarizable material over the metal layer prior to planarizing
US6586814B1 (en) 2000-12-11 2003-07-01 Lsi Logic Corporation Etch resistant shallow trench isolation in a semiconductor wafer
US6617251B1 (en) 2001-06-19 2003-09-09 Lsi Logic Corporation Method of shallow trench isolation formation and planarization
US6949446B1 (en) 2001-06-19 2005-09-27 Lsi Logic Corporation Method of shallow trench isolation formation and planarization

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