JPH01255042A - Priority control circuit - Google Patents

Abstract

PURPOSE:To realize priority control to always uniformize service for each request origin by attaching highest priority in the request origin not receiving the service in the past by the history of an acceptance request. CONSTITUTION:When a request is accepted by a priority circuit 10, the acceptance status is stored in a history storage means 20. The storage of the acceptance status is performed in time series at every acceptance of the request. Priority order change means 30 and 40 compare the contention status of the time series data (that is, history) of the means 20 with a present request a every request and the history of its own system with that of another system, and output a suppression signal to suppress the acceptance of the system when the request of another system is not accepted after the request of its own system is accepted finally with the range of the history. In such a way, no contention is generated in the circuit 10, and the request of the system on which the highest priority order is attached by the means 30 and 40 can be accepted in spite of the fixed priority order of the system.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a priority control circuit, and particularly to a priority control circuit that allows processing requests to be accepted evenly.

[Prior art] One of the conventional priority control circuits, for example, Japanese Patent Application Laid-Open No. 55-6
It is described in Publication No. 6016. That is, this publication discloses a signal priority determining circuit comprising a high-speed circuit that outputs a permission signal by delaying an element in response to input of a request signal without using a clock.

However, this conventional prioritization circuit always responds to requests according to a fixed priority. Therefore, this conventional priority determination circuit has a drawback that if requests of high priority occur frequently, it will not be able to respond to requests of low priority.

In response to this, a circuit that can change the priority order has been proposed.

One of them is disclosed in Japanese Patent Laid-Open No. 58-72230. In other words, the publication states that in a system in which multiple devices or one device is used in common, the priority order of a centralized priority selection circuit using a priority encoder is changed at a fixed period to control usage requests. The size of the centralized priority selection circuit is characterized in that it prevents only a specific usage request with a high priority from being accepted by cyclically changing the number of requests, and performs control so that each request is accepted and processed equally. A click priority control method has been disclosed.

Furthermore, in Japanese Patent Application Laid-Open No. 57-71032, information on the request input to which the most recently responded is given to a read-only memory which is a priority order determining circuit, and the read-only memory is configured to provide information about the request input to which the immediately before responded is input. Disclosed is a priority control circuit characterized in that the priority control circuit is configured to be stored so as to select an input with the highest priority, and to output priority control information according to a predetermined priority order when there are no requests. has been done.

[Invention or problem to be solved] However, the above conventional techniques have the following drawbacks.

The priority control method disclosed in Japanese Patent Application Laid-open No. 58-72230 has no relation to the generation cycle of each request and the priority change cycle, so if multiple requests enter at the same time, in the worst case, the priority control method is There may be times when it is not possible to accept changes within the ranking change period. Therefore, depending on the relationship between the request cycle and the priority change cycle, it cannot be said that a fair service can be received. For example, if it is smaller than the request period or priority change period, and if it is larger,
The former will obviously have an advantage.

In addition, in the priority control circuit disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 57-71032, the priority order is appropriately changed according to the immediately preceding request response, so that a request of one system is shorter than a request of another system. The drawback is that the priorities are not equalized if they are entered at regular intervals.

The purpose of the present invention is to increase the priority of request sources that have not received service in the past, and to equalize the service (request reception interval - throughput) to each request source, regardless of the frequency of each request. The object of the present invention is to provide a priority control circuit that can switch priorities.

[Means for Solving the Problems] An object of the present invention is to record the reception status of requests in a priority control circuit that has a priority circuit that selects one request from among a plurality of request inputs according to a predetermined priority order. In each of the multiple systems in which a request is competing, within the range stored in the history storage means, a request from one's own system is stored in chronological order as This is achieved by configuring the system to include a priority order changing means for suppressing acceptance of requests of the system and changing the priority order when the requests of the system are not accepted.

The history storage means is configured to, for example, store the reception status of requests from immediately before to a plurality of times before, and output the reception status of each request to the priority order changing means. Specifically, it can be constructed by sequentially arranging parallel-in/parallel-out registers having inputs corresponding to each prefecture from which the Rifnis 1- is issued, the number of stages corresponding to the number of receptions to be stored as history. Further, it can be configured by arranging a serial-in/parallel-out shift register for each system that issues requests. In the former case, the number of receptions to be stored as history can be increased or decreased by increasing or decreasing the number of register stages, while in the latter case, the same can be done by increasing or decreasing the number of bits in the shift register. Something will happen.

In the history storage means, the range to be stored as history is determined based on how many previous reception situations are to be stored, taking into account the number of input requests, the cycle of each request, and the like. - Generally speaking, it is preferable to increase the number of times the request is stored as the number of input requests increases, or as the request period differs.

The priority order changing means is configured to change the priority order by selectively suppressing a plurality of competing inputs to the priority circuit in accordance with past request reception status. Specifically, for example, it is configured to include a priority determining circuit that outputs a deterrent signal, and a gate circuit that inhibits reception of the corresponding system using the deterrent signal. However, selective inhibition by this priority order changing means is equivalent to selective permission, which has the opposite relationship, and it goes without saying that the present invention includes both.

[Operation] In the present invention, when a plurality of requests conflict with each other, the priority circuit selects one of the requests according to a preset priority order. In the present invention, when the priority changing means does not work, the priority of this priority circuit works, and when the priority changing means works,
Within that range, the priority is changed.

When a request is accepted by the priority circuit, the reception status is stored in the history storage means. This reception status is stored in chronological order every time a request is accepted.

When the preset number of times of storage is reached, the reception status data is updated to new reception status data in order of priority.

The priority order changing means compares the time-series data of the receiving request 1 status stored in the history storage means, that is, the history and the conflicting situation of the current request, for each request with the history of the own system and the other system. The histories of the systems are compared, and when a request from the other system is not accepted after a request from the own system has been accepted for the last time within a certain range of history, a suppress W signal is output to suppress acceptance for the system. This mutual comparison of histories is performed by logical operations.

As mentioned above, the last reception in its own system outputs a deterrent signal depending on whether there is a subsequent reception by another system, so when multiple requests conflict, a deterrent effect is exerted on the system that received the relatively new request, and The system that was accepted earlier will have a higher priority. This is done mutually for a plurality of competing systems, and as a result, a system that has not received service in the past, that is, for which no requests have been accepted, has a higher priority.

In this way, by outputting a suppression signal for systems other than those with high priority and inhibiting the input of requests to the priority circuit, there will be no competition in the priority circuit, regardless of its fixed priority.
The request of the system given the highest priority by the priority order changing means will be accepted.

In addition, the priority order change means in this invention may be comprised so that the same priority order may be given to several rift varnishes 1-. In this case, conflicts among the plurality of requests are processed by the priority circuit in a preset order.

As described above, according to the present invention, request sources that have not received services in the past are given higher priority, and priority control is performed so that services are equally distributed to each request source. Moreover, this can be achieved without being affected by the generation cycle of each request.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

<Configuration of Example> FIG. 1 shows the configuration of an embodiment of the priority control circuit of the present invention.

The example shown in FIG. 1 shows requests R6 to R from three systems.
This is an example of a case where there is a conflict between the two.

The priority control circuit of this embodiment has a plurality of request inputs R8
- A priority circuit 10 that selects one request among R2 according to a predetermined priority order, a history storage means 20 that stores the reception status of requests R6 to R2 in chronological order as a history, and multiple requests that are competing with each other. In each of the systems, - within the range stored in the history storage means 20, when a request from another system has not been accepted since the last request from the own system was accepted, the request from the system concerned is It is comprised of a priority determining circuit 30 that outputs a suppression signal to suppress acceptance, and a gate circuit 40 that receives the suppression signal and selectively suppresses requests R6 to R2 from each prefecture.

The priority circuit IO is constituted by a gate circuit, for example, as shown in FIG. This circuit 10 is
A gate output G from a gate circuit 40 which will be described later. -02, and the gate output G. a signal line 11 which directly connects the signal to the request acceptance signal output Ao, an ant gate circuit 12 which performs the logical product of the inverted gate output Go and the outputs G1 to G1, and an output G to the G1. , an inverted version of the gate output G1, and an AND gate circuit 13 that takes the AND of the inverted version of the gate output G1 and the gate output G3.

This priority circuit 10 has gate outputs Go to G2.
Priorities are set in the order of G, >G, and >G2.

As shown in FIG. 1, the history storage means 20 includes registers 21, 22 and 23 for the parallel in-parallel array 1, an OR gate circuit 24 that ORs the output of the priority circuit IO, and It is configured to include an AND gate circuit 25 that performs a logical product of the output and the timing signal T. Each register 21, 22 and 23 is
The connections are made in this order, and the request acceptance statuses of the previous, second, and third requests are stored, respectively. BO~B2,C
Outputs history information representing the reception status of o-C2.

The priority order determining circuit 30 and gate circuit 40 constitute priority order changing means of the present invention.

For requests R6 to R2, the priority order determination circuit 30 determines the above A o "'-A2. B o to B2,
Using the history information of Co-C2, inhibit signals H8 to H2
form. This conditional expression is as follows.

Ho=A o” (RH+ R2) + H, = A I” (Ro + R2) + H2=A 2” (Ro + R1) + Equation (1) is,
There is a conditional expression for Ho, and the first term is to give a lower priority than requests R, . . . R2 if request R8 was accepted one time ago. The second term is such that when request R6 has been accepted two times ago, if request R4°R2 has not been accepted one time ago, the priority is lowered than requests R, , R2. The third term is such that when request R6 has been accepted three times ago, if requests R□ and R2 have not been accepted two times ago, the priority is lowered than requests R1°R2.

Similarly, H8 in equation (2) and H2 in equation (3) are determined.

According to the above logical formulas (1) to (3), the priority determination circuit 3
0 lowers the priority of request sources that have been accepted recently. If you change your perspective, this becomes L RU (Le
ast Recently Used Method)
It is thought that the opposite idea was realized in a logic circuit.

FIG. 3 shows an example of the configuration of this priority order determining circuit 30.

As shown in FIG. 3, the priority order determining circuit 30 includes a logic block U corresponding to the system issuing the request. ,U,,
consisting of U 2 and corresponding inhibition signals H6+Hf
Output H2. Each logical block U o; U l + U
2 has the same configuration.

Logical Flock U. are three small blocks U n and U b corresponding to the logical operations of terms 1 to 3 of equation (1) above.

Uc and an OR gate circuit 3 that takes the logical sum of these outputs.
10.

The small block Ua includes an OR gate circuit 311 that logically ORs requests R1 and R2, and history information A that represents the previous reception status of this logical OR and request R6. It has an anchor circuit 312 which calculates which AND.

The small block Ub includes an ant gate circuit 313 that calculates the AND of the request R1 and history information A representing the previous reception status of the R1, and A that is the inverted version of the history information A that represents the reception status immediately before the request R1; An ant gate circuit 314 that logically ANDs history information representing the reception status with λ-2 which is inverted, an OR gate circuit 315 that logically sums these outputs, and this logical sum and the reception status two times before request R8. History information B does not represent. AND gate circuit 316 that takes the AND with
It has

The small block Uc includes an ant gate circuit 317 that calculates the AND of the request R0 and A, , B, which are the inverted history information representing the reception status of the previous request R, and the request R2. An inquiry circuit 31 that calculates the AND of A-2 and B2, which are the inverted history information representing the reception status of the request R2 before and after the request R2.
8, and an OR gate circuit 319 that logically ORs these outputs.
and an inquiry circuit 320 which calculates the AND of this logical sum and the history information Co representing the acceptance status three times before the request R8.

The gate circuit 40 includes AND gate circuits 41, 42, and 43 corresponding to requests R6 to R2.

The corresponding AND gate circuits 41, 42 and 43 are inputted with inverted inhibit signals H6, H, H2, respectively.
When the inhibit signal is at a high level, the gate of the corresponding ant gate circuit is turned off. In other words, all requests from the relevant Kate are suppressed.

<Operation of the Embodiment> Next, the operation of the present invention will be explained with reference to the time charts shown in FIGS. 1, 2, 3, and 4.

The values of A to C of registers 21 to 23 shown in FIG.
As shown in the figure, A="100", B="'010",
If C="100", that is, if the priority is R2>Rr>Ro, requests R8 to R
An example of when two events occur at the same time will be explained.

First, the values of A to C in registers 21 to 23 are A = “100.
”, B-“010”, and C-“100””, and the request signals are generated simultaneously at time t.
Depending on the value of C and the values of requests R'o to R2, as shown in FIG. 4, H, = "1", H, = "1",
Outputs the logical value of H2=“O”.

Due to the signals H8 to H2, only the AND gate circuit 43 of the gate circuit 40 is turned on, and the priority circuit 10 is turned on.
, and outputs an acceptance signal A2 in response to the request.

Thereafter, at time t, the OR gate 24 and the ANTO gate 25 output a clock trigger to the registers 21-23. Then, Resis 21-23 A-C
As shown in Fig. 4, A = “OO1” at time 〇
, B=“100”.

C=″′010”. Also, at time t1, A2;
° "1" turns off request R2, which also turns off acceptance signal A2.

Subsequently, the priority order determining circuit 30 determines that A=゛001'', B
='“100”, C; “010°” and request R6=
"1", R,= "1", R8=°"0 Pa, as shown in Fig. 4, Ho=°"1", H+
= “O” and H2 = “1”. The signals H8 to H2 turn on only the ant gate circuit 42 of the gate circuit 40, are applied to the priority circuit 10, and output an acceptance signal A1 in response to the request.

Thereafter, at time t2, the OR gate 24 and the ANTO gate 25 output a clock trigger to the registers 21-23. Then, A- of registers 21 to 23
C is shown in Figure 4, where A = “
010 °°, B - "0 0 Bi, C = "100", request R
2, turn off the quest R1 and the acceptance signal A.

Further, the priority order determination circuit 30 determines that A-010'', B=
``100'', C = ``010'' and request R8-
Based on "1", R1-"0", R2-"o", as shown in FIG. 4, Ho="0", H,= "1'"
, H2-'"l"' outputs the logical value. This H8~H
2, the AND gate circuit 4 of the gate circuit 40
1 is turned on and is added to the priority circuit 10, and the acceptance signal A for the request. Output.

Thereafter, at time t3, the OR gate 24 and the ANTO gate 25 output a clock trigger to the registers 21-23. Then, registers 21-23 A~
As shown in Fig. 4, C is A-“lOO”, B=゛0
10'', C="OO1", and request R8 and acceptance signal A are turned off.

As is clear from the above description, according to the present invention, it is possible to lower the priority of requests that have recently been assigned.

<Other Examples> The present invention is not limited to the above-mentioned embodiments, and various modifications are possible. For example, the history storage means may be configured with a serial-in/parallel-out shift register.

[Effects of the Invention] As explained above, according to the present invention, request sources that have not received service in the past are prioritized based on the history of requests received in the past, so that each request is Priority control can be performed to ensure equal service to each request source regardless of the cycle.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a priority control path according to an embodiment of the present invention, FIG. 2 is a logic circuit diagram showing the configuration of a priority circuit used in the above embodiment, and FIG. 3 is a block diagram showing the configuration of a priority circuit used in the above embodiment. FIG. 4 is a logic circuit diagram showing the configuration of a priority order determining circuit used in the present invention, and FIG. 4 is a time chart showing the operation of the priority order determining circuit. 10... Priority circuit 20... History storage means 21-23... Register 24... OR gate circuit 25... Ant gate circuit 30... Priority order determination circuit 40... Gate circuits 41-42 ...Ant gate circuit Uo~U2...Logic block U8~Uc...Small block

Claims (1)

[Scope of Claims] 1. In a priority control circuit having a priority circuit that selects one request from among a plurality of request inputs according to a predetermined priority order, history storage that stores request reception status in chronological order as a history. and, in each of the multiple systems in which requests are competing, no requests from other systems have been accepted since the last request from the own system was accepted, within the range stored in the history storage means. 1. A priority control circuit comprising: priority order changing means for changing the priority order by suppressing acceptance of requests of the system at the time of the request. 2. The priority control circuit according to claim 1, wherein the history storage means is configured to store the reception status of requests from immediately before to a plurality of times before, and output the reception status of each request to the priority order changing means. .