JPH01241194A - Printed circuit board - Google Patents
Printed circuit boardInfo
- Publication number
- JPH01241194A JPH01241194A JP6858588A JP6858588A JPH01241194A JP H01241194 A JPH01241194 A JP H01241194A JP 6858588 A JP6858588 A JP 6858588A JP 6858588 A JP6858588 A JP 6858588A JP H01241194 A JPH01241194 A JP H01241194A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- epoxy resin
- para
- circuit board
- printed circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000003822 epoxy resin Substances 0.000 claims abstract description 21
- 229920000647 polyepoxide Polymers 0.000 claims abstract description 21
- 229920003235 aromatic polyamide Polymers 0.000 claims abstract description 19
- 239000004020 conductor Substances 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 claims abstract description 14
- -1 polyparaphenylene Polymers 0.000 claims abstract description 7
- 229920000265 Polyparaphenylene Polymers 0.000 claims abstract description 6
- AVRQALNKUQDGLO-UHFFFAOYSA-N benzene-1,4-dicarboxamide;phenoxybenzene Chemical compound NC(=O)C1=CC=C(C(N)=O)C=C1.C=1C=CC=CC=1OC1=CC=CC=C1 AVRQALNKUQDGLO-UHFFFAOYSA-N 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 22
- 239000004593 Epoxy Substances 0.000 claims description 3
- 239000011247 coating layer Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 21
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 12
- 239000011889 copper foil Substances 0.000 abstract description 12
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 abstract description 9
- 125000003118 aryl group Chemical group 0.000 abstract description 9
- 229920000768 polyamine Polymers 0.000 abstract description 9
- 238000000034 method Methods 0.000 abstract description 7
- 229910052709 silver Inorganic materials 0.000 abstract description 7
- 239000004332 silver Substances 0.000 abstract description 7
- 239000004744 fabric Substances 0.000 abstract description 5
- 239000004848 polyfunctional curative Substances 0.000 abstract description 3
- 230000003685 thermal hair damage Effects 0.000 abstract description 2
- 239000003795 chemical substances by application Substances 0.000 description 6
- RTZKZFJDLAIYFH-UHFFFAOYSA-N Diethyl ether Chemical compound CCOCC RTZKZFJDLAIYFH-UHFFFAOYSA-N 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 241000531908 Aramides Species 0.000 description 3
- 230000008602 contraction Effects 0.000 description 3
- 239000000835 fiber Substances 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 238000005470 impregnation Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 241000220317 Rosa Species 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- MHSKRLJMQQNJNC-UHFFFAOYSA-N terephthalamide Chemical compound NC(=O)C1=CC=C(C(N)=O)C=C1 MHSKRLJMQQNJNC-UHFFFAOYSA-N 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052708 sodium Inorganic materials 0.000 description 1
- 239000011734 sodium Substances 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
- H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
- H05K1/0366—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement reinforced, e.g. by fibres, fabrics
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Reinforced Plastic Materials (AREA)
- Laminated Bodies (AREA)
- Insulated Metal Substrates For Printed Circuits (AREA)
- Organic Insulating Materials (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は電子機器の回路構成に利用することができるプ
リント回路板に関するものである。DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to a printed circuit board that can be used in the circuit configuration of electronic equipment.
従来の技術
プリント配線板の基材には、紙基材フェノール樹脂板、
ガラス布基材エポキシ樹“指板などが一般に用いられ、
この種の基板上に銅箔導体層を張り付けて、回路配線導
体としている。また、最近では、メタ系アーラミドｍｊ
ａ布にポリイミド樹脂を含浸させた基材構成も試みられ
ている。Conventional technology The base materials for printed wiring boards include paper-based phenolic resin boards,
Glass cloth-based epoxy wood fingerboards are commonly used.
A copper foil conductor layer is pasted on this type of board to serve as a circuit wiring conductor. Also, recently, meta-based aramide mj
A base material structure in which a cloth is impregnated with polyimide resin has also been attempted.
発明が解決しようとする課題
近年、プリント配線板上に半導体集積回路チップ（以下
、単に半導体チップと記す）を直接搭載して、ハイブリ
ッド回路板を形成する用途が生まれているが、かかる用
途には、従来のプリント配線板は必ずしも適合しない。Problems to be Solved by the Invention In recent years, applications have emerged in which semiconductor integrated circuit chips (hereinafter simply referred to as semiconductor chips) are directly mounted on printed wiring boards to form hybrid circuit boards. , conventional printed wiring boards are not necessarily suitable.
すなわち、紙基材板は半導体チップ搭載の過程の高温プ
ロセスに不適合であり、ガラス布基材板では不純物、と
りわけ、ナトリウム成分の半導体チップへの作用を排除
するのが困難である。さらに、樹脂含浸のブリント配線
板では、半導体チップとの熱的整合、すなわち、温度に
よる伸縮率が半導体と樹脂とで著しく異なるので、温度
サイクルで接着剥離を起こしたり、半導体チップが破断
するという問題を有していた。この種の問題は、従来の
メタ系アーラミド繊維紙にポリイミド樹脂含浸の基板の
場合も同様に生じていた。That is, paper base plates are not suitable for high-temperature processes in the process of mounting semiconductor chips, and glass cloth base plates have difficulty in eliminating the effects of impurities, particularly sodium components, on semiconductor chips. Furthermore, in resin-impregnated printed wiring boards, thermal matching with semiconductor chips, that is, the rate of expansion and contraction due to temperature, is significantly different between the semiconductor and the resin, so there are problems such as adhesive peeling or breakage of the semiconductor chip due to temperature cycles. It had This kind of problem also occurred in the case of the conventional substrate made of meta-aramide fiber paper impregnated with polyimide resin.
本発明の目的は、半導体チップを直接搭載しても、高信
頼性が達成できるプリント回路板を提供することにある
。An object of the present invention is to provide a printed circuit board that can achieve high reliability even when a semiconductor chip is directly mounted thereon.
課題を解決するための手段
本発明は、バラ系アーラミド基材にエポキシ樹脂を５５
〜６０重量％の割合で含浸させ、表面に導体層を被着し
た構成のプリント回路板である。Means for Solving the Problems The present invention provides 55% epoxy resin on a rose-based Aramide base material.
The printed circuit board is impregnated with a concentration of ~60% by weight and has a conductive layer on its surface.
パラ系アーラミドはポリパラフェニレン３−４ディフェ
ニルエーテルテレフタラミドを使用すると好適である。As the para-aramide, polyparaphenylene 3-4 diphenyl ether terephthalamide is preferably used.
また、このエポキシ樹脂含浸パラ系アーラミド基材回路
板を用い、スルーホールをもって、他方の基板の配線層
と導電接続するとき、その導電接続材にはエポキシ樹脂
系導電塗布層を使用したものが適当である。In addition, when using this epoxy resin-impregnated para-aramide base circuit board to conductively connect it to the wiring layer of the other board using through holes, it is appropriate to use an epoxy resin-based conductive coating layer as the conductive connecting material. It is.
作用
本発明によると、−４０℃〜１５０℃の温度範囲にわた
って、シリコン基体の半導体チップと同等の伸縮率を有
する回路板が得られる。バラ系アーラミド基材は温度に
対して負の係数をもち、エポキシ樹脂の正の温度係数を
相殺して、半導体チップと同等の温度係数を実現できる
。こうして、温度及び湿度のサイクル的変化に対して、
信頼性の高い半導体チップ搭載用プリント回路板が得ら
れる。According to the present invention, it is possible to obtain a circuit board having an expansion/contraction rate equivalent to that of a silicon-based semiconductor chip over a temperature range of -40°C to 150°C. The rose-based aramide base material has a negative temperature coefficient, which cancels out the positive temperature coefficient of the epoxy resin, making it possible to achieve a temperature coefficient equivalent to that of a semiconductor chip. Thus, against cyclical changes in temperature and humidity,
A highly reliable printed circuit board for mounting semiconductor chips can be obtained.
実施例 つぎに、本発明を実施例によって詳しくのべる。Example Next, the present invention will be described in detail by way of examples.
第１図は本発明実施例回路板の適用装置の断面図であり
、絶縁性基板１を、芳香族ポリアミンアダクト硬化剤配
合のエポキシ樹脂を重量比５５〜６０％で含浸させたポ
リパラフェニレン３−４゜デイフェニルエーテルテレフ
タラミド紙または布基材板で形成し、この絶縁性基板１
上に、厚さ３５μｍの銅箔導体２および厚さ５〜７μｍ
の銀めっき層３を設け、半導体チップ４を接着し、ワイ
ヤ５で接続したものである。絶縁性基板１上への銅箔導
体２の張り付けは、含浸材のエポキシ樹脂の硬化過程を
利用して、その半硬化状態で貼り合わせ、完全硬化過程
で接着すればよい。また、半導体チップ４の接着は、同
チップ裏面側に金層を形成しておき、その金層を介して
圧着することで可能である。また、半導体チップ４の接
着に、芳香族ポリアミンアダクトを硬化剤としたエポキ
シ樹脂配合の導電性接着剤を用いることもでき、これに
よると、銀の移行を抑止する効果がある。さらに、銀め
っき層３の代わりに、ニッケルまたはニッケルと金との
二重層を用いることができる。FIG. 1 is a sectional view of an application device for a circuit board according to an embodiment of the present invention, in which an insulating substrate 1 is made of polyparaphenylene 3 impregnated with an epoxy resin containing an aromatic polyamine adduct curing agent at a weight ratio of 55 to 60%. -4゜diphenyl ether terephthalamide paper or cloth base plate, and this insulating substrate 1
On top, a copper foil conductor 2 with a thickness of 35 μm and a thickness of 5 to 7 μm
A silver plating layer 3 is provided, and a semiconductor chip 4 is adhered and connected with wires 5. The copper foil conductor 2 may be pasted onto the insulating substrate 1 by utilizing the hardening process of the epoxy resin as an impregnating material, by pasting the epoxy resin in a semi-hardened state, and then adhering it during the completely hardening process. Further, the semiconductor chip 4 can be bonded by forming a gold layer on the back side of the chip and press-bonding the semiconductor chip 4 through the gold layer. Further, a conductive adhesive containing an epoxy resin containing an aromatic polyamine adduct as a curing agent can be used to bond the semiconductor chip 4, and this has the effect of suppressing silver migration. Furthermore, instead of the silver plating layer 3, nickel or a double layer of nickel and gold can be used.
絶縁性基板１の基材であるパラ系アーラミドのポリパラ
フェニレン３−４′デイフエニルエーテルテレフタラミ
ドは、メタ系アーラミドのポリパラフェニレンテレフタ
ラミドより塩素等の不純物の含有量が１〜２桁少ない。The polyparaphenylene 3-4' diphenyl ether terephthalamide of para-aramide, which is the base material of the insulating substrate 1, has a content of impurities such as chlorine of 1 to 10% less than that of polyparaphenylene terephthalamide of meta-aramide. Two digits less.
また、このパラ系アーラミド紙は、高い耐熱性をもつが
、エポキシ樹脂含浸により、絶縁性基板１の耐熱性は、
その含浸材に依存し、んとえは、結晶化温度（Ｔｇ）が
１２５〜１５０℃となる。しかし、半導体チップ４の接
着あるいは、ワイヤボンディングの際の短時間の高温な
らば、約３５０℃までの耐久性は得られる。In addition, this para-aramide paper has high heat resistance, but due to the epoxy resin impregnation, the heat resistance of the insulating substrate 1 is
Depending on the impregnating material, the crystallization temperature (Tg) will be between 125 and 150°C. However, if the semiconductor chip 4 is bonded or wire bonded to a high temperature for a short period of time, durability up to about 350° C. can be obtained.
実施例として、芳香族ポリアミンアダクト硬化剤配合エ
ポキシ樹脂含浸（含浸率６０Ｍ量％）のパラ系アーラミ
ド基材基板１上に、３５μｍの銅箔２を張り付け、これ
に、銀めっき層３を介して、半導体チップ（チップサイ
ズ：４Ｘ４ｍｍ）４を接着したもので、その温度サイク
ル（−６５℃〜１５０°Ｃ）および温度サイクル（１２
０℃。As an example, a 35 μm copper foil 2 is pasted on a para-aramide base substrate 1 impregnated with an epoxy resin containing an aromatic polyamine adduct hardener (impregnation rate: 60 M%), and a copper foil 2 of 35 μm is attached to this via a silver plating layer 3. , semiconductor chips (chip size: 4 x 4 mm) 4 are glued together, and their temperature cycles (-65°C to 150°C) and temperature cycles (12
0℃.
１００％〜１２０℃、ドライ）の各テストを行ったとこ
ろ、基板寸法１０×１０ＣＩ１１．厚さ！ 、 ６ ＋
ｎｍの場合、上記温度サイクル＝４５０〜５００回。When various tests were conducted (100% to 120°C, dry), the board size was 10 x 10 CI 11. thickness! , 6 +
In the case of nm, the above temperature cycle = 450 to 500 times.
上記湿度サイクル＝１００〜１５０回の耐久性が確認さ
れ、また、基板の厚さを０．４ｍｍになしたもので、温
度サイクル＝２００回〜２５０回、湿度サイクルニア５
〜１２５回の耐久性が得られた。The durability of the above humidity cycle = 100 to 150 times was confirmed, and the substrate thickness was 0.4 mm, temperature cycle = 200 to 250 times, humidity cycle near 5
Durability of ~125 times was obtained.
第２図は、別の実施例のプリント回路板を示す断面図で
ある。このプリント回路板は、芳香族ポリアミンアダク
ト硬化剤配合のエポキシ樹脂を含浸率６０重量％で含浸
させたパラ系アーラミド繊維紙基材の第１基板２１に、
厚さ３５μｍの銅箔導体２２を貼り合わせ、これに、上
記第１基板２１と同組織の第２基板２３および厚さ３５
μｍの銅箔導体２４を、それぞれ、重ねて貼り合わせた
ものである。そして、第１基板２１には、スルーホール
を形成し、このスルーホールを第２基板２３上の銅箔導
体２４の位置に合わせて貼り合わせたのち、スルーホー
“ルを、芳香族ポリアミンアダクト硬化剤配合エポキシ
樹脂中に銀粉を混合した導電接着剤の塗布によって埋め
、導体層２５を形成した。この導体層２５の形成は、金
属マスクを使って、印刷形成することができる。なお、
各基板および銅箔の貼り合わせの工程ならびにスルーホ
ールの形成工程は、エポキシ樹脂を、初めに、１３０℃
、３０分で半硬化（いわゆる、Ｂステージ硬化）の状態
で行い、これらを重ね合わせたのちに、１６０〜１６５
℃、１５〜１０分の再硬化処理を行うことによって、完
全硬化（Ｃステージ硬化）の状態にできる。また、塗布
導体層２５の硬化条件も、基板形成時とほとんど同じで
よいが、流動性を考慮すると、１５０℃、３０分程度の
低温、長時間を採用するのが適当である。FIG. 2 is a cross-sectional view of another embodiment of the printed circuit board. This printed circuit board includes a first substrate 21 made of a para-aramide fiber paper base impregnated with an epoxy resin containing an aromatic polyamine adduct hardener at an impregnation rate of 60% by weight.
A copper foil conductor 22 with a thickness of 35 μm is bonded together, and a second substrate 23 having the same structure as the first substrate 21 and a thickness of 35 μm are attached to this.
Copper foil conductors 24 of .mu.m are laminated one on top of the other. Then, a through hole is formed in the first substrate 21, and after bonding the through hole to the position of the copper foil conductor 24 on the second substrate 23, the through hole is cured with an aromatic polyamine adduct curing agent. The conductor layer 25 was formed by applying a conductive adhesive containing silver powder mixed into a compounded epoxy resin.The conductor layer 25 can be formed by printing using a metal mask.
In the process of bonding each board and copper foil and the process of forming through holes, epoxy resin is first heated at 130°C.
, in a semi-cured state (so-called B stage curing) for 30 minutes, and after stacking these, 160 to 165
By performing re-curing treatment at 15 to 10 minutes at 100° C., a completely cured state (C-stage cure) can be achieved. Further, the curing conditions for the coated conductor layer 25 may be almost the same as those for forming the substrate, but in consideration of fluidity, it is appropriate to use a low temperature of 150° C. for about 30 minutes for a long time.
第３図は、四層配線をもつ積層基板構造の実施例プリン
ト回路板の断面図である。この実施例構成で、第１．第
２および第３基板３１．３２および３３は、いずれも、
ポリパラフェニレン３−４゛デイフ工ニルエーテルテレ
フタラミド繊維紙に、芳香族ポリアミンアダクト硬化剤
配合のエポキシ樹脂を５５〜６０重量％に含浸させた、
厚さ０．１〜１．０ｍｍの構成物であり、導体層３４，
３５゜３６．３７は、厚さ３５μｍあるいは７０μｍの
銅箔で形成される。また、互いの導体層を接続するため
のスルーホール導体層３８．３９は、芳香族ポリアミン
硬化剤配合エポキシ樹脂に銀粉混合の導電性接着剤の塗
布層で形成される。なお、この導体層の抵抗率は１２〜
１５ｍΩ／口であった。FIG. 3 is a cross-sectional view of an embodiment of a printed circuit board having a laminated board structure with four-layer wiring. With this embodiment configuration, the first. The second and third substrates 31, 32 and 33 are both
A polyparaphenylene 3-4゛definyl ether terephthalamide fiber paper was impregnated with 55 to 60% by weight of an epoxy resin containing an aromatic polyamine adduct curing agent.
It is a structure having a thickness of 0.1 to 1.0 mm, and includes a conductor layer 34,
35°36.37 is formed of copper foil with a thickness of 35 μm or 70 μm. Further, the through-hole conductor layers 38 and 39 for connecting the conductor layers to each other are formed of a coating layer of a conductive adhesive containing silver powder mixed in an epoxy resin containing an aromatic polyamine curing agent. Note that the resistivity of this conductor layer is 12~
It was 15 mΩ/mouth.
この実施例構成は、所望の多層配線を得るのに適し、耐
熱性、耐湿性にすぐれたものである。The structure of this embodiment is suitable for obtaining a desired multilayer wiring, and has excellent heat resistance and moisture resistance.
発明の効果
本発明によれば、芳香族ポリアミンアダクト硬化剤配合
エポキシ樹脂含浸パラ系アーラミド基材を用いて、プリ
ント回路板を構成したことにより、耐熱性、耐湿性のよ
いものが実現され、とくに、同基板上に半導体チップを
直接搭載しても、両者の温度伸縮率が同等なため、熱的
破損が避けられる。また、本発明のプリント回路板は、
銀の移行性をも十分に抑止する効果があり、多層構造で
、高密度配線構造を採用して、その配線間相互の影響を
抑制して、高度の信頼性を達成することができる。Effects of the Invention According to the present invention, by constructing a printed circuit board using a para-aramide base material impregnated with an epoxy resin containing an aromatic polyamine adduct curing agent, a printed circuit board with good heat resistance and moisture resistance is realized. Even if a semiconductor chip is directly mounted on the same substrate, thermal damage can be avoided because the temperature expansion and contraction rates of both are the same. Further, the printed circuit board of the present invention includes:
It has the effect of sufficiently suppressing the migration of silver, and can achieve a high degree of reliability by employing a multilayer structure and a high-density wiring structure, suppressing the mutual influence between the wirings.
第１図〜第３図は本発明の各実施例プリント回路板の断
面図である。
１．２１．２３．３１．３２．３３・旧・・エポキシ樹
脂含浸パラ系アーラミド基材基板、２．２２゜２４．３
４〜３７・・・・・・銅箔導体。1 to 3 are cross-sectional views of printed circuit boards according to various embodiments of the present invention. 1.21.23.31.32.33 Old...Epoxy resin impregnated para-aramide base material substrate, 2.22°24.3
4-37...Copper foil conductor.
Claims (4)
０重量％の割合で含浸させ、表面に導体層を被着したプ
リント回路板。(1) Epoxy resin 55-6 on para-aramide base material
A printed circuit board impregnated with 0% by weight and coated with a conductive layer on its surface.
ィフェニルエーテルテレフタラミドでなる請求項１に記
載のプリント回路板。2. The printed circuit board according to claim 1, wherein the para-aramide is polyparaphenylene 3-4 diphenyl ether terephthalamide.
する第１の基板をエポキシ樹脂含浸パラ系アーラミド基
材で構成し、この第１の基板を、少なくとも一面に導体
層を有する第２の基板に重ね、前記第１の基板上の導体
層と前記第２の基板上の導体層とをエポキシ樹脂系導電
塗布層で導電接続したプリント回路板。(3) A first substrate having a conductor layer and through holes on one or both sides is made of an epoxy resin-impregnated para-aramid base material, and this first substrate is connected to a second substrate having a conductor layer on at least one side. A printed circuit board in which a conductive layer on the first substrate and a conductive layer on the second substrate are electrically connected by an epoxy resin conductive coating layer.
請求項３に記載のプリント回路板。(4) The printed circuit board according to claim 3, wherein the first board is stacked on both sides of the second board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63068585A JPH0793478B2 (en) | 1988-03-23 | 1988-03-23 | Printed circuit board for mounting semiconductor chips |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63068585A JPH0793478B2 (en) | 1988-03-23 | 1988-03-23 | Printed circuit board for mounting semiconductor chips |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01241194A true JPH01241194A (en) | 1989-09-26 |
| JPH0793478B2 JPH0793478B2 (en) | 1995-10-09 |
Family
ID=13378017
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63068585A Expired - Fee Related JPH0793478B2 (en) | 1988-03-23 | 1988-03-23 | Printed circuit board for mounting semiconductor chips |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0793478B2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6235593A (en) * | 1985-08-09 | 1987-02-16 | 東芝ケミカル株式会社 | Metal substrate for circuit |
-
1988
- 1988-03-23 JP JP63068585A patent/JPH0793478B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6235593A (en) * | 1985-08-09 | 1987-02-16 | 東芝ケミカル株式会社 | Metal substrate for circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0793478B2 (en) | 1995-10-09 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |