JPH01143266A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the withstand voltage of a drain by forming a stepped part on the surface of a semiconductor substrate between a gate electrode and a drain electrode, and further forming a low concentration impurity layer on the stepped part. CONSTITUTION:A semiconductor substrate 1 includes a gate electrode 2 formed thereon, and drain and source electrodes 3, 4 formed on both sides of the gate electrode 2. Then, respective n<+> layers 5, 6 for the drain and the source are formed on the lower side of those drain and source electrodes 3, 4. Further, a channel n layer 7 is formed below the gate electrode 2. The thickness of the semiconductor substrate 1 from the drain side end of the gate electrode 2 to a drain region is partially reduced, at which a stepped part 8 is formed. An n layer 9 of a lower concentration than in the drain side n<+> layer 5 is formed at the stepped part 8. The n layer 9 connects the n<+> layer 5 with the channel layer 7. According to this arrangement, the n layer 9 of the low concentration is formed between the channel n layer 7 and the drain side n<+> layer 5, assuring the improvement of drain withstand voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of a field effect transistor (FET) having a high drain breakdown voltage.

[Conventional technology]

An example of a conventional FET is shown in FIG. In the figure, l is the semiconductor substrate, 2 is the gate electrode, 3 is the source electrode, 4 is the drain electrode, 5.6 is the n layer for good connection between the electrode and the semiconductor layer (5 is the drain side, 6 is the source side), 7 is F
This is a channel n layer for ET operation.

[Problem that the invention seeks to solve]

In order to increase the drain breakdown voltage in the FET having the structure shown in FIG. 3 described above, it is necessary to reduce the concentration of the n'' layer 5, or in FIG. Possible configurations include a configuration in which it is moved back.

However, in the former configuration in which the concentration of n''N5 is lowered, it is necessary to form the n9 layer 5 in a separate process from the n''IW6 on the source side, resulting in an increase in the number of manufacturing steps. In addition, if it is formed in the same process as the source side, the source resistance will increase due to a decrease in the concentration on the source side. on the other hand,
In the latter configuration in which the 09 layer 5 is retreated toward the drain side, the layer 5 cannot be formed by a self-alignment method using the gate electrode 2, so errors in alignment with the gate electrode 2 have a large effect, resulting in variations in characteristics. There is a problem of inviting

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device including an FET with improved drain breakdown voltage and suppressed variations in characteristics.

[Means for solving problems]

The semiconductor device of the present invention has a structure in which a stepped portion is formed on the surface of a semiconductor substrate between a gate electrode and a drain electrode, and a low concentration impurity layer is formed in this stepped portion.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a sectional view of a first embodiment of the present invention.

A gate electrode 2 is formed on a semiconductor substrate 1, and drain and source electrodes 3 and 4 are further formed on both sides thereof.

Furthermore, below each of the drain and source electrodes 3.4, drain-side and source-side n' layers 5.6 are formed.

Furthermore, an n-channel layer 7 is formed below the gate electrode 2 .

Here, the thickness of the semiconductor substrate 1 is reduced from the drain side end of the gate electrode 2 to the drain region, and a low inclined step portion 8 is formed in this portion. This stepped portion 8 has a lower concentration of O2 than the drain side n layer 5.
A layer 9 is formed, and this layer 9 connects the n'' layer 5 and the channel n.
The layers 7 are connected. In this case, even if the 0 layer 9 is formed by ion implantation at the same time as the n' layer 5, it will be formed at a low concentration to a certain extent due to the slope of the stepped portion 8. Note that the width of this stepped portion 8 is proportional to the depth of the step, but if the depth is set to about 1 μm or less, higher precision can be achieved than in horizontal alignment.

According to this structure, since the low concentration 0 layer 9 is formed between the channel n layer 7 and the drain side n' layer 5, it is possible to improve the drain breakdown voltage. In addition, by providing the step portion 8, this low concentration 0 layer 9 can be formed simultaneously with the formation of the n° layers 5 and 6 and by a self-alignment method using the gate electrode 2, without increasing the number of steps. Moreover, it can be formed with high precision.

FIG. 2 is a sectional view of a second embodiment of the present invention, and the same parts as in FIG. 1 are given the same reference numerals.

In this example, the step portion 8A formed between the drain side end of the gate electrode 2 and the drain side layer 5 is formed on the semiconductor substrate 1.
The grooves form an inclined surface, and the low concentration n layer 9 is formed along this inclined surface.

In this case, when forming the low concentration n layer 9, the n layer 56
The fact that it can be formed by simultaneous ion implantation is the same as in the previous embodiment. Furthermore, it is also possible to form the gate electrode 2 in a self-aligned manner using the gate electrode 2.

It goes without saying that this low concentration n layer 9 can improve the drain breakdown voltage. Note that in this embodiment, the source electrode 3
There is an advantage that the drain electrode 4 and the drain electrode 4 can be arranged at the same height.

〔Effect of the invention〕

As explained above, in the present invention, a step portion is formed on the surface of the semiconductor substrate between the gate electrode and the drain electrode, and a low concentration impurity layer is formed in this step portion, so that the drain breakdown voltage can be improved. This low-concentration impurity layer can be formed simultaneously with the source and drain high-concentration impurity layers by a self-alignment method using the gate electrode and by using the slope of the stepped portion, so it can be manufactured without increasing the number of man-hours.
Moreover, it has the effect of suppressing variations in characteristics.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a first embodiment of the invention, FIG. 2 is a sectional view of a second embodiment of the invention, and FIG. 3 is a sectional view of a conventional structure. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Gate electrode, 3... Source electrode, 4... Drain electrode, 5... Drain side n' layer, 6... Source side n+ layer, 7... - Channel layer, 8, 8A... step portion, 9... low concentration n layer.

Claims (1)

[Claims] (1) In a semiconductor device including a field effect transistor in which a gate electrode, a source electrode, and a drain electrode are formed on a semiconductor substrate, and a highly concentrated impurity layer is formed below the source electrode and the drain electrode, the gate electrode and the drain electrode are formed on a semiconductor substrate. 1. A semiconductor device comprising: a step portion formed on a surface of a semiconductor substrate between a drain electrode; and a low concentration impurity layer formed in the step portion.