JPH01125977A - Mos semiconductor device - Google Patents

Abstract

PURPOSE:To suppress a short-channel effect and a punch-through effect by a method wherein a sidewall gate electrode is provided and an intense inversion layer with a small thickness and an opposite conductivity type is provided between the gate electrode and a source (drain) region by applying a voltage to the sidewall gate electrode. CONSTITUTION:A voltage of, for instance, -5V is applied to sidewall gates 7'. In this state, as the conductivity type of the sidewall gates 7' is p<+>type and there is an n<->type substrate 1 immediately below the sidewall gates 7', p-type intense inversion layers 14 are formed in the surface regions of the n-type substrate 1 immediately below the sidewall gates 7'. As the intense inversion layers 14 reduce series resistances in those regions and the situation equivalent to the formation of very shallow source and drain regions are produced because the thickness of the intense inversion layer 14 is less than 1000Angstrom A so that a short-channel effect and a punch-through effect can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a MOS semiconductor device, and particularly to a miniaturized MOS semiconductor device.

(Prior Art) Source/drain diffusion layers constituting a conventional MO8 type transistor are formed by patterning a gate electrode and then implanting impurity ions into the substrate surface using the gate electrode as a mask. The impurity diffusion layer in this case is obtained, for example, by ion-implanting arsenic at a dose of about 1015/cd for an n-channel transistor, and boron at a dose of about 1015/cj for a p-channel transistor. Then, in order to electrically activate these impurities, 9oo
Heat treatment is performed at a high temperature of approximately .degree. C., and a PSG or BPSG film is deposited on the surface to flatten the device surface, followed by reflow treatment at a high temperature.

However, when a diffusion layer is formed by such an ion implantation method, the diffusion layer tends to spread within the silicon substrate.

In order to increase the density of semiconductor devices and to miniaturize submicron regions, it is necessary to reduce the junction depth of source/drain diffusion layers in order to prevent short channel effects, bunch-through effects, and the like.

In order to achieve this, there is a method of lowering the acceleration voltage during ion implantation to achieve low acceleration, but the 1015
It is very difficult to obtain a practical ion implantation current necessary for ion implantation at a high dose of /c- at a low voltage. Further, even if the dose is reduced, the junction depth becomes shallower, but on the contrary, the layer resistance of the diffusion layer increases and the characteristics of the semiconductor device deteriorate.

Further, as described above, since heat treatment is performed at high temperature for electrical activation after ion implantation, the junction depth becomes deeper. In particular, boron used in p-channel MOS transistors has a small atomic radius, so the range during ion implantation is large, and because the atomic radius is small, it is easy to diffuse into a deep region by high-temperature heat treatment.

(Problems to be Solved by the Invention) As mentioned above, in conventional MOS semiconductor devices, it is difficult to make the source ψ drain diffusion region shallow due to the properties of ions and the manufacturing method, which leads to a decrease in threshold voltage and There is a problem in that sufficient high density cannot be achieved because punch-through occurs.

The present invention has been made to solve these problems, and provides a high-performance, hole-reliable MOS semiconductor device by reducing the diffusion depth of the source/drain diffusion layer to eliminate the cause of characteristic deterioration. The purpose is to

[Structure of the invention]

(Means for Solving the Problems) In the MOS type semiconductor device according to the present invention, a gate electrode is formed in an element formation region of a semiconductor substrate of one conductivity type via a gate oxide film, and a side wall portion of the gate electrode is A sidewall gate electrode of opposite conductivity type provided through an insulating film and to which a voltage is applied independently of the gate electrode, and source and drain regions of opposite conductivity type formed in the semiconductor substrate on both sides of this sidewall gate electrode. The device is characterized in that a thin forced transition layer of opposite conductivity type is formed between the gate electrode and the source and drain regions by applying a voltage to the sidewall gate electrode.

(Function) When a voltage is applied to the sidewall gate electrode of opposite conductivity type, a strong transition layer of opposite conductivity type is formed between the gate electrode and the source and drain regions. Since this strong transition layer is extremely thin and has low resistance, it can achieve the same effect as when the depth of the source and drain diffusion layers is made extremely shallow, suppressing the short channel effect and bunch-through effect and improving the characteristics. It is possible to obtain a fine semiconductor device with good quality and high reliability.

(Example) Hereinafter, a MOS semiconductor device and a method for manufacturing the same according to the present invention will be described in detail with reference to the drawings.

FIG. 1(e) is a sectional view showing an embodiment of a MOS type semiconductor device according to the present invention.

In this semiconductor device, a gate electrode 4 of a MOS transistor is formed on an n-type semiconductor substrate 1 with a gate oxide film 3 interposed therebetween, and a high concentration silicon oxide film 6 is formed on the side wall of the gate electrode 4 with an insulating silicon oxide film 6 interposed therebetween. A sidewall gate 7' in which a p-type impurity is diffused is formed in the sidewall gate 7', and a voltage is applied to this sidewall gate 7'. Source and drain regions 9 in semiconductor substrate 1 are formed outside sidewall gate 7'.

The operation of such a semiconductor device will be explained.

First, a voltage of, for example, -5V is applied to the sidewall gate 7'. In this state, the sidewall gate 7' has a p+ conductivity type, and the n-type substrate 1 is directly below it, so the surface of the n-type substrate 1 directly under the sidewall gate 7' has a p-type strong conductivity type. Layer 14 is formed. This strong transition layer 14 reduces the series resistance of this region, and since the thickness of this strong transition layer is less than 1000 Å, the state is similar to that of extremely shallow source and drain regions. Short channel effects and punch-through effects are suppressed.

Next, the manufacturing process of this MO3 type semiconductor device will be explained with reference to the step-by-step sectional views shown in FIG.

First, an n-type silicon substrate 1 with crystal orientation (100) is prepared, and a thick field oxide film 2 is formed on its surface using a normal device isolation technique using a nitride film or the like to isolate device regions.

Next, the surface of the substrate 1 is oxidized by thermal oxidation or the like, and a gate oxide film 3 is formed to a thickness of, for example, 250 mm. Then, an n+ polycrystalline silicon film 4 is deposited thereon to a thickness of, for example, 4,000 wafers, and a silicon nitride film 5 is further deposited thereon to a thickness of, eg, 1,500 wafers, and etched using lithography and reactive ion etching techniques. The polycrystalline silicon film 4 and the silicon nitride film 5 are etched using the etching method. As a result, a patterned gate electrode is obtained (Fig. 1(a)
)).

Next, thermal oxidation is performed to form a silicon oxide film 6 to a thickness of approximately 500 nm on the surface of the polycrystalline silicon exposed on the side walls of the gate electrode (FIG. 1(b)). During this oxidation, almost no oxide film is formed on the silicon nitride film 5.

Next, a polycrystalline silicon layer 7 is applied to the entire surface using the CVD method to a thickness of approximately 3000 nm.
Boron ions are deposited to a thickness of about 100 mL, and boron ions are implanted at a speed of 40 kV and an amount of 1 x 1016/+ C- (FIG. 1(C)). The broken line in the polycrystalline silicon layer shows how ions are implanted in this way, and the implanted boron ions are electrically activated by annealing in a nitrogen atmosphere at 1000°C for about 20 minutes. The entire crystalline silicon layer has a p-type concentration (P+
) Polycrystalline silicon.

Subsequently, when reactive ion etching is performed on the entire surface, p+ polycrystalline silicon 7' remains only on the side walls of the gate electrode (first
Figure (d)).

Next, using the gate electrode and the remaining polycrystalline silicon layer 7' as an ion implantation mask, boron was implanted at an accelerating voltage of 40 KV.
When ion implantation is performed at a dose of 5.times.10.sup.15/c-, an ion implantation layer 8 is formed near the surface of the semiconductor substrate 1 (FIG. 1(d)).

Next, annealing is performed to form p+ diffusion layers 9 that will become source and drain diffusion layers. And silicon oxide film 10 on the entire surface
is deposited by the CVD method, and then a PSG film 11 is deposited.

Contact holes for wiring are then opened in these films using lithography technology. The contact holes to be formed are shown in FIG. 3, and include a source contact hole 41, a drain contact hole 42, a sidewall gate contact hole 43, and a gate contact hole 4.
It is 4.

First, a first resist pattern is formed for the former three, and a CVD silicon oxide film 1 is etched by reactive ion etching.
0 and PSG film 11 are removed to form a hole. Note that when the source contact hole 41 is opened, the hole is opened on the gate electrode 4, and the silicon nitride film 5 is formed on the gate electrode 4 as described above.
Since this silicon nitride film 5 has a large selection ratio compared to other materials, if etching is stopped at an appropriate point, the gate electrode and sidewall gate electrode will be shorted due to the aluminum wiring. Never.

Subsequently, a second resist pattern for gate contact is formed, and by reactive ion etching, the CVD silicon 1) silicon oxide film 10, PSG film 11, and silicon nitride film 5 are removed to form a hole.

Then, wirings 12 and 13 are formed by vapor depositing aluminum and patterning it (Fig. 1(e)
)).

FIG. 2 is a sectional view of an element showing another embodiment of the present invention, in which parts corresponding to those in FIG. 1 are given reference numbers with 20 added to the numbers in FIG. 1. In this embodiment, the conductivity types are all reversed, and an n-channel transistor is formed using a p-type substrate 21 and forming an n-type sidewall gate 27' and n-type source and drain regions 29.

〔Effect of the invention〕

As described above, according to the present invention, a sidewall gate electrode is provided for forming a thin and low-resistance, opposite conductivity type strong conversion layer between the gate electrode and the source and drain regions by applying a voltage. As a result, the short channel effect and punch-through effect are suppressed, resulting in a fine semiconductor device with good characteristics and high reliability. can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the structure of an embodiment of a semiconductor device according to the present invention and a method for manufacturing the same, FIG. 2 is a cross-sectional view of an element showing another embodiment of the present invention, and FIG. 3 is a contact hole FIG. 1.21... Semiconductor substrate, 3, 23... Gate oxide film, 4, 24... Gate electrode, 5, 25... Silicon nitride film, 6, 26... Silicon oxide film, 7'27'
...Side wall gate, 9.29...Source, drain region. Applicant's agent Sato - 1 stallion, 3 horses

Claims (1)

[Claims] 1. A gate electrode formed in an element formation region of one conductivity type semiconductor substrate via a gate oxide film, and a gate electrode provided on a side wall of the gate electrode with an insulating film interposed therebetween; comprises a sidewall gate electrode of opposite conductivity type to which a voltage is applied independently, and source and drain regions of opposite conductivity type formed in the semiconductor substrate on both sides of the sidewall gate electrode, and a voltage is applied to the sidewall gate electrode. A MOS type semiconductor device in which a thin strong inversion layer of an opposite conductivity type is formed between the gate electrode and the source and drain regions by applying a voltage applied thereto. 2. The MOS type semiconductor device according to claim 1, wherein a silicon nitride film is provided on the upper surface of the gate electrode, and a silicon oxide film is provided on the side surface of the gate electrode as an insulating film.