JPH01112455A - Memory card circuit - Google Patents

Abstract

PURPOSE:To guarantee the recording data of a semiconductor memory without fail by providing a power source voltage detecting circuit to cause unidirectional and bidirectional three state buffers to be a conductive condition when a power source input voltage is larger than a specified value and to cause the buffers to be an interrupted condition when it is smaller than the specified value. CONSTITUTION:When a power source input 14 achieves a normal voltage to be larger than the specified value, a power source voltage detecting circuit 21 generates a signal to contact a series transistor (TR) 20 and unidirectional and bidirectional three state buffers 18 and 19. When the input 14 is an abnormal voltage to be smaller than the specified value, or in case of a portable time, the circuit 21 generates a signal to turn off the TR 20 and the buffers 18 and 19. Since the contacting/turning-off is controlled by a card attaching and detaching signal input 23 from a terminal equipment, the storing data of the semiconductor memory are guaranteed when the card is attached and detached in the active condition of the terminal equipment and the memory card. When the input 14 is turned off and in case of the portable time, a power source current is prevented to be flowed to the terminal equipment.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to memory card circuits, and in particular, to replacing an external storage device with a semiconductor memory and taking advantage of the characteristics of semiconductor memory such as high speed, low power consumption, and no noise. This paper relates to the circuitry of a portable memory card that can be utilized.

[Conventional technology]

FIG. 4 shows a conventional memory card circuit. In this figure, 1 is a static RAM group, which has a plurality of static RAMs 2. 3 is an address decoder circuit which decodes each static RAM from static RAM group 1 by address bus signal 8 and chip enable signal 9.
A static RAM selection signal 13 for selecting RAM 2 is generated.

The static RAM group 1 has a well-known chip enable signal (CB)9. Write enable signal m)10. An output enable signal (OE) 11° and a data bus signal 12 are connected. 14 is a power supply input, which becomes an internal power supply 15 via a series diode 16. When this power source 14 is disconnected (cut off) or when you carry it with you, the battery 6
operates, series resistance 5. A current is supplied via the protection diode 4 as an internal power supply 15. Further, 7 is a capacitor, and 17 is a pull-up resistor. In addition, the signal pi.

τT, WE, and σ1 are “L” active (operable at “L”).

The circuit shown in FIG. 4 has the minimum necessary circuit configuration as a memory guard circuit, and is generally well known. Each static RAM 2 of static RAM group 1
Address decoder circuit 3 is used to select. Static R which is the output of this address decoder 3
The AM selection signals 13 are connected to chip select signals of the corresponding RAMs 2, respectively. That is, the circuit of this conventional memory card is a circuit that outputs each terminal signal of the RAM 2 directly to the outside. Therefore, the operation of the circuit shown in this figure is basically exactly the same as that of the RAM 2 alone.

The operation of this circuit will be explained below.

First, the operation when there is no power source 14 will be explained. R.A.
M2. The voltage of a battery 6 is supplied to the address decoder 3 via a series resistor 5 and a protection diode 4. Further, the RAM selection signal 13 which is the output of the decoder 3 is all at the "H" level because the resistor 17 of the chip enable signal 9 is pulled up to the internal power supply 15. Therefore, since the signal 9 of each RAM2 becomes "H" level, the RA
The data bus signal 12 of M2 becomes a floating state. Therefore, the data stored in the RAM 2 does not disappear and can be maintained.

Next, the operation when the power source 14 is supplied from the terminal will be described. Power source 14 is supplied to internal power source 15 via series diode 16 .

Generally, the voltage of the internal power source 15 at this time is set higher than that of the battery 6, so the internal power source 15 and the battery 6 are cut off by the action of the protection diode 4. Therefore, battery 6
Since no current flows through it, there is no wear and tear.

Since the read and write operations of the RAM 2 are the same as those of a single RAM, a detailed explanation will be omitted and will be briefly explained below. First, the address bus signal 8 is input from the terminal, and the decoder 3. Applied to RAM2. The decoder 3 has an R corresponding to the address bus signal 8.
The chip enable signal (CE) 9 of AM2 is decoded, but it is actually output when the chip enable signal (CE) 9 of the decoder 3 is at "L" level. Now, the RAM 2 corresponding to 8000 is selected by the decoder 3, and the RAM 2
Assume that the chip enable signal CE of is "L". R
When data from the data bus signal 12 is written into the storage area of AM2, it is possible to do so by setting the write enable signal (WE) 10 to the "L" level during the L" level section of the signal Cπ. At this time, the output enable signal (OE) 11 is set to "H" level.
Reading from the storage area of the RAM 2 can be done by setting the signal 11 to the "L" level during the "L" level interval of 100. At this time, the signal 10 is set to the "H" level. Also, if signal 9 is set to 'H' level, RAM2
data bus (No. 8 and 12 is in a floating state,
It becomes impossible to read (read) or write (write).

These operations are the same as those of a standalone RAM and are generally well known.

[Problem that the invention seeks to solve]

Conventional memory card circuits have the following problems.

1) The single terminal signal of RAM2 is directly exposed (output) to the outside, and when the memory card is inserted in the operating state B of the terminal (power supply 14 is supplied state B), the memory card is The R
Destroy the data stored in AM2.

2) If the power supply 14 is cut off while the terminal and memory card are connected, and the chip enable signal 9 and write enable signal 10 are at "L" level on the terminal side, the series resistance 5° protection is applied. Diode 4. The current in the battery 6 flows out to the terminal side through the pull amplifier resistor 17, and the battery 6 is instantly discharged and consumed.

3) Since each terminal signal of RAM2 is basically output to the outside, the static electricity resistance depends on the static electricity resistance of RAM2 alone.

4) The input/output impedance of the memory card when carried is RAM2. The static electricity resistance depends on the impedance of the address decoder circuit 3, which is generally very high impedance.

The electromagnetic field resistance will be a low value.

5) When RAM2 increases, the input/output capacity of each signal 9 to 12 increases, and the rise and fall times of each signal become extremely long, making it impossible to satisfy the standard value for RAM2 alone (
The electrical performance will deteriorate significantly.

This invention was made to solve the above-mentioned problems, and it is possible to directly remove or insert the memory card when the terminal and the memory card are connected in a live wire state (power-carrying state). We provide a highly reliable large-capacity memory card circuit with high static electricity resistance and electromagnetic field resistance, which can reliably guarantee the data recorded in semiconductor memory such as RAM even if The purpose is to

[Means for solving problems]

The memory card circuit according to the present invention includes a unidirectional 3-state buffer circuit for the address bus and control bus (chip enable, write enable, and output enable signals) of a semiconductor memory, and a bidirectional 3-state buffer circuit for the data bus, A series transistor is provided between the semiconductor memory and the terminal device, a series transistor is provided between the power input and the semiconductor memory, and a power supply voltage detection circuit is provided to detect the power input to select operation/non-operation based on the card insertion/removal signal from the terminal device. Series transistors and unidirectional and bidirectional 3-state buffers are "connected" (conducting) when the power supply input voltage is above the specified value, and "disconnected" (blocking) when it is below the specified value, and pull amplifier resistors are installed at all terminals. is grounded via a pull-down resistor.

[Effect]

In this invention, 1) address bus signal, signal σ7L, TFT! ,,
By providing unidirectional or bidirectional 3-state buffers for all 1° and data bus signals, each terminal signal of the semiconductor memory is prevented from being directly exposed to the outside, and the electrical performance can be achieved.

2) A series transistor connects/disconnects the power source and the internal power source.

3) The power supply voltage detection circuit connects the series transistor and unidirectional/bidirectional 3-state buffer when the power supply input reaches a normal voltage above the specified value, and when the power supply input reaches an abnormal voltage below the specified value or when carried. Generates a signal that disconnects the series transistor and the unidirectional and -bidirectional 3-state buffers, and further controls the connection/disconnection by the card insertion/removal signal input from the terminal, thereby making it possible to activate the terminal and memory card. In the line state (energized state),
The data stored in the semiconductor memory is guaranteed when the device is inserted or removed, and the battery current is prevented from flowing out to the terminal device when the power supply is turned off or when the device is carried.

4) When carrying in your possession, by grounding all terminals such as the input side of the unidirectional 3-state buffer and the output side of the bidirectional 3-state buffer with pull-up and pull-down resistors,
The input/output impedance of all terminals decreases.

〔Example〕

FIG. 2 shows a memory card circuit according to one embodiment of the present invention. In this figure, 1 to 17 are basically the same as in FIG. Signals 8 to 11 are connected to the RAM 2 via a unidirectional 3-state buffer 18 and signal 12 via a bidirectional 3-state buffer 19. A series transistor 20 is interposed between the power supply 14 and the internal power supply 15, and connection/disconnection thereof is performed by a power supply voltage detection circuit 21. This power supply voltage detection circuit 21 can be controlled by a card insertion/removal signal input 23. When the card insertion/removal signal input 23 is at the "H" level, the detection circuit 21 is operational, and at this time, the power source 14 is applied, and when the voltage reaches a normal voltage value, the transistor 20 operates and is supplied to the internal power source 15. At the same time, the input/output cover sofa connection/disconnection signal 24 becomes "H" level, and the address decoder circuit 3° unidirectional 3-state buffer 18 is connected.

The chip enable signal 9 is connected to a terminal (enable terminal) of a buffer 19 via a buffer 18. The buffer 19 can be connected in both directions when the Bi terminal is at the "L" level, and when it is at the "H" level? roating and bidirectional connection becomes impossible.

The output enable signal 11 is connected to a DIR terminal (direction control terminal) of a buffer 19 via a buffer 18 . When the DIR terminal of the buffer 19 is set to "L" level, the data stored in RAM2 is read, and when the DIR terminal is set to "H" level, it is read from the RAM2.
Data can be written to M2. 22 is a pull-down resistor, which grounds the pull-up resistor 17 connected to signals 8 to 12 when carrying a memory card.
The signal E is "H'" (active and operable at "H").

Next, the operation of this embodiment will be explained by dividing it into the following three operation modes.

Operation mode 1: Operation when the terminal and memory card are connected. Operation mode 2: Operation when removing the memory card from operation mode 1. Operation mode 3: Operation when inserting the memory card into the terminal. Operation mode 1 will be explained below.

A card insertion/removal signal 23 from the terminal is set to "H" level and applied to the power supply voltage detection circuit 21. The detection circuit 21 is “
H'' level operation is possible. Power supply from all terminals is 14
is supplied, and when the voltage reaches the specified value, the detection circuit 2
1 operates and draws the base current of the series transistor 20, so this transistor 20 conducts and the internal power supply 15
is applied to At the same time, the input/output buffer connection/disconnection signal 24 becomes "H" level and the address decoder circuit 3. These are added to the unidirectional 3-state buffer 18 and are enabled. 0 When RAM 2 is not accessed normally, chip enable signal 9 = "H" level, write enable signal 10 = "H" level, output Enable signal 11 is at "H" level. Therefore, the static RAM selection signals 13 are all at "H" level, and the 100 terminal of the bidirectional 3-state buffer 19 is also at "H" level. In this state, when writing the data bus signal 12 from the terminal to the RAM 2, the following procedure is performed. becomes.

When the write address is given to the address bus signal 8 and the chip enable signal 9 is set to "L" level, the address decoder 3 sets the static RAM selection signal 13 of the corresponding memory to "
By setting the write enable signal lO to the "L" level during the "L" level section of the RAM selection signal 13, the data bus signal 12 at that time is set to the "L" level.
It is possible to write to 2. At this time, the output enable signal 11 is set to "H" level. Next, when reading the data stored in RAM 2 to the terminal, the read address is given to signal 8, and when signal 9 is set to "L" level, decoder 3
sets the signal 13 of the corresponding memory to "L" level. this"
By setting 111 to @L level in the L'' level interval, the data stored at that address can be read to the terminal.The DIR terminal of the buffer 19 controls the direction of the bidirectional buffer. When the signal 11 is at "H" level, it goes from the terminal to RAM2, and when it is at "L" level, it goes from RAM2 to the terminal.The above operation is performed by a single RAM.
- It is a well-known operation in boat fishing. In this operation mode, the voltage of the internal power supply 15 is higher than the voltage of the battery 6, so the battery 6 is cut off by the protection diode 4 and no current flows through the battery 6.

Furthermore, when the voltage of the power source 14 drops below the specified value, the detection circuit 21 is activated, and the input/output bus connection/disconnection signal 24 immediately goes to L'' level, the transistor 20 is cut off, and the decoder 3 is disabled (inoperable). ) next to signal 13
are all at "H" level. Also, the buffer 18 is cut off, so the ■ terminal of the buffer 19 is connected to the pull-up resistor 17.
Since it is pulled up at “H” level, buffer 1
9 is floating. That is, the internal power supply 15 is supplied by the battery 6, and the data stored in the RAM 2 is retained.

Next, operation mode 2 will be explained below.

When removing the memory card from the terminal, set the card insertion/removal signal 23 to "L" level on the terminal before removing (and R)
It is possible to extract the data stored in AM2 without destroying it. When the signal 23 is set to "L" level, all the signals 13 are "H" level and the buffers 18 and 19 are cut off, so that all terminal signals of the terminal and the RAM 2 are completely cut off.

Therefore, RAM2 is the connection part between the terminal and the memory card (
Since it is not affected by noise such as the level fluctuation 9 time difference that occurs at the moment of pulling out in a normal connector), the stored data is guaranteed not to be destroyed. After this, since the memory card has no power source 14 and the resistor 22 is pulled down (maintains the "L" level), the human output buffer connection/disconnection signal 24 goes to the "L" level and stores the stored data. The internal power source 15 at this time is supplied by the battery 6.

As means for generating the signal 23 in the terminal, a method using a switch as shown in FIG. 2 or cpUft+II of the terminal as shown in FIG. 3 is used. There is a method using il. In these figures, 25 is a memory card, 30, 40 is a buffer, 32 is a switch, 31 is a signal line connected to a CPU interrupt signal or I10 port, and 41 is a CPU
This is the signal line from the software control. In these methods, the access status (write) of the memory card is determined by supplying the signal 23 to the memory card 25 and simultaneously applying it to the interrupt terminal or I10 terminal of the CPU of the terminal.

Since reading can be stopped, erroneous writing and reading during insertion and removal can be completely prevented.

Finally, operation mode 3 will be explained below.

- The operation when inserting the memory card into the terminal after being pulled out in operation mode 2 is shown below. All terminal signals of the terminal and RAM2 are completely cut off, so the terminal is in a live state ( Even if a memory card is inserted while the device is in a power-on state, the stored data is guaranteed not to be destroyed. The subsequent operation is in mode 1. This is the same as mode 2, so it will be omitted.

Note that, according to the above embodiment, the semiconductor memory has a static R
Although AM is used, the present invention is also applicable to other semiconductor memories except for batteries, series resistors, and protection diodes.

For example, OTP (one time programmable) RO
The same effects as in the above embodiments can be achieved also in M, mask ROM, and EEFROM.

〔Effect of the invention〕

As described above, the memory card circuit according to the present invention has the following effects.

1) All terminal signals of the semiconductor memory are connected to the terminal via unidirectional and bidirectional buffers, so even if a large number of semiconductor memories are used, the same electrical characteristics as a single product can be achieved.

2) A series transistor is provided between the power supply input and the semiconductor memory, and a power supply voltage detection circuit that is controlled by the card insertion/removal signal from the terminal device and detects the power supply input is provided, and the series transistor and the buffer are connected to each other when the power supply input exceeds a specified value. Since it is connected when the voltage is below the specified value and disconnected when the voltage is below the specified value, the terminal device and the semiconductor memory can be disconnected by the buffer, and even if the memory card is inserted or removed while the terminal device is in a live state. Destruction of stored data can be prevented, and battery current can also be prevented from flowing into the terminal. Furthermore, even if the semiconductor memory is being accessed, it is possible to interrupt the access, thereby preventing erroneous writing and reading.

3) Since the input/output terminals of the memory card are grounded using pull-up and pull-down resistors when carried, the input/output impedance is significantly smaller than that of a single semiconductor memory.
Static electricity resistance and electromagnetic field resistance are significantly improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a memory card circuit according to an embodiment of the present invention, FIG. 2 is a diagram for explaining card insertion/removal signal input by a switch, and FIG. 3 is a diagram for explaining card insertion/removal signal input by a terminal CPU. FIG. 4 is a diagram showing a conventional memory card circuit. 1 is a static RAM group, 2 is a static RAM, 3 is an address decoder circuit, 4 is a protection diode, 5 is a series resistor, 6 is a battery, 7 is a capacitor, 8 is an address bus signal, 9 is a chip enable signal, 10 is a write enable signal, 11 is an output enable signal, 12
is a data bus signal, 13 is a static RAM selection signal,
14 is a power supply input, 15 is an internal power supply, 16 is a series diode, 17 is a pull-up resistor, 18 is a unidirectional 3-state buffer circuit, 19 is a bidirectional 3-state buffer circuit, 20 is a series transistor, 21 is a power supply voltage detection circuit , 22 is a pull-down resistor, 23 is a card insertion/removal signal input, and 24 is an input/output bumper connection/disconnection signal. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] (1) In a memory card circuit having a portable memory card, a unidirectional three-state buffer circuit and a data bus connected to the address bus and control bus of the semiconductor memory to interface between the semiconductor memory and the terminal device. A bidirectional 3-state buffer circuit connected to the memory card, a series transistor provided between the power input of the memory card and the semiconductor memory, and a card insertion/removal signal from the terminal device to select its operation or non-operation state;
The power input of the memory card is detected, and the series transistor, the unidirectional 3-state buffer, and the bidirectional 3-state buffer are turned on when the power input voltage is above a specified value, and cut off when it is below the specified value. A memory card circuit comprising: a power supply voltage detection circuit; a pull-up resistor provided to all terminal signals of the memory card; and a pull-down resistor for grounding the pull-up resistor.