JP7091113B2 - Semiconductor devices and control methods for semiconductor devices - Google Patents

Description

The present invention relates to a semiconductor device and a method for controlling the semiconductor device, particularly a semiconductor device including a memory circuit driven by a built-in voltage conversion circuit (boost circuit, step-down circuit), and a method for controlling the semiconductor device. ..

When a booster circuit is configured in a semiconductor device provided with a memory circuit, a charge pump is often used. For example, as a conventional technique of a memory circuit having a power supply circuit using a charge pump, for example, a variable stage charge pump disclosed in Patent Document 1 is known. The variable stage charge pump disclosed in Patent Document 1 includes a first charge pump, a second charge pump, a first switch that couples the output of the first charge pump to the input of the second charge pump, and a first charge pump. A variable stage charge pump comprising a second switch that couples the input of to the input of the second charge pump, the first when the first switch is in the first position and the second switch is in the second position. When the charge pump and the second charge pump are connected in series to the common output node, the first switch is in the second position and the second switch is in the first position, the first charge pump and the second charge pump are in the common output node. Is connected in parallel to.

Here, as described in Patent Document 1, conventionally, in semiconductor devices, there is a tendency to use an external power supply voltage for the purpose of reducing power consumption. In addition, in order to improve the withstand voltage of the oxide film due to the miniaturization of the semiconductor device process and to meet the problems of flattening (stabilizing) the power supply voltage, a power supply that requires an external power supply voltage inside the semiconductor chip. Internal step-down is generally performed by stepping down to a voltage.

On the other hand, there are many cases where a voltage higher than the voltage supplied by the power supply is required, for example, in the write, erase, and read operations of the flash memory, and in such a case, a charge pump circuit is used as a booster circuit. .. A general charge pump circuit is composed of a capacitance for pumping an electric charge and a transfer MOS (Metal Oxide Semiconductor) transistor (field effect transistor) for transferring the pumped electric charge to prevent backflow and boosting the voltage.

In addition, in order to control the output voltage of the charge pump to the target boost voltage, a sensor circuit is provided, and the pump operation is continued and the pump operation is stopped when it is detected that the voltage exceeds the target. Then, when the sensor circuit detects that the boosted voltage has dropped due to the drive current or leak current after stopping, the pump operation is restarted. Ringing may occur in the boosted voltage due to the pump operation and its stop and start. Therefore, if you do not want to change the boosted voltage, for example, the word line voltage when reading the flash memory, step down the boosted voltage. In some cases, a step-down power supply circuit that stably supplies voltage may be added.

Special Table No. 11-512864 Gazette

Here, when the sensor circuit is provided as described above, it depends on the diode connection row or resistance element row by the P-type MOS transistor (hereinafter referred to as “Pomycin transistor”) connected between the output of the boosted voltage and the ground (GND). Generally, a comparative voltage is generated by a voltage divider circuit. In this case, the power of the boosted voltage source is consumed by the current flowing through the voltage divider circuit. Therefore, the flash memory-equipped microcontroller especially during low-speed operation. As described above, in applications where low current consumption is required, it is common to throttle the current flowing through the voltage divider circuit in order to meet the operating current standard. However, if the current flowing through the voltage divider circuit is throttled, the above-mentioned microcontroller can be used. When switching from low-speed operation to high-speed operation, there was a problem that the comparison voltage did not follow immediately, and the boosted voltage continued to drop during that time, making reading difficult. Also, even during low-speed operation, the boosted voltage had a problem. Since the current is flowing from the source to the voltage divider circuit, there is a problem that the loss of the operating current is large even if the current flowing through the voltage divider circuit is throttled. Such a problem is connected to the booster circuit. The same applies to a step-down circuit that lowers the boost voltage from the booster circuit to supply power. In the following, the booster circuit and the step-down circuit may be collectively referred to as a “voltage conversion circuit”.

In this regard, the variable stage charge pump disclosed in Patent Document 1 aims to be able to cope with different output levels at a given charge pump power input level, and has a problem of suppressing current consumption. is not.

The present invention has been made to solve the above-mentioned problems, and is a semiconductor device having a voltage conversion circuit capable of supplying a stable voltage while suppressing an increase in current consumption, and a semiconductor device. The purpose is to provide a control method.

The semiconductor device according to the present invention has a first mode that operates at a first speed and a second mode that operates at a second speed faster than the first speed, and inputs a power supply voltage. It is provided with an input unit of 1, a second input unit for inputting a reference voltage, and a third input unit for inputting a comparison voltage, and converts and outputs the power supply voltage based on the comparison between the reference voltage and the comparison voltage. A voltage conversion unit that outputs a voltage from the output unit and one terminal are connected to the output unit, and the voltage obtained by dividing the output voltage is output as the comparative voltage from the other terminal to the third input unit. The operation mode includes the voltage dividing unit and the capacitance in which one terminal is connected to the output unit and the other terminal is connected to the third input unit, and the operation mode is from the first mode to the second mode. When the mode is switched, the decrease in the comparative voltage due to the decrease in the output voltage is returned to the voltage conversion unit via the capacitance, and the output voltage increases before the voltage dividing unit completes charging. It is a thing.

The semiconductor device of another aspect according to the present invention has a first mode operating at a first speed and a second mode operating at a second speed higher than the first speed, and has a power supply voltage. A first input unit for inputting a reference voltage, a second input unit for inputting a reference voltage, and a third input unit for inputting a comparison voltage are provided, and the power supply voltage is based on a comparison between the reference voltage and the comparison voltage. The voltage conversion unit that converts the voltage and outputs the output voltage from the output unit, the load connected to the output unit, and one terminal connected to the output unit, and the voltage obtained by dividing the output voltage is compared. A voltage dividing section that outputs a voltage from the other terminal to the third input section, a discharging section connected to the output section, and a predetermined voltage after switching from the first mode to the second mode. This includes a control unit that controls the discharge unit so that a current equivalent to the load current flowing through the load flows through the discharge unit in the second mode.

On the other hand, the control method of the semiconductor device according to the present invention has a first mode operating at a first speed and a second mode operating at a second speed faster than the first speed, and has a power supply. The power supply includes a first input unit for inputting a voltage, a second input unit for inputting a reference voltage, and a third input unit for inputting a comparison voltage, based on a comparison between the reference voltage and the comparison voltage. A voltage conversion unit that converts a voltage and outputs it as an output voltage from the output unit, one terminal is connected to the output unit, and the voltage obtained by dividing the output voltage is used as the comparison voltage from the other terminal to the third terminal. It is a control method of a semiconductor device including a voltage dividing unit that outputs to an input unit and a capacitance in which one terminal is connected to the output unit and the other terminal is connected to the third input unit, and the operation mode is When the mode is switched from the first mode to the second mode, the decrease in the comparative voltage due to the decrease in the output voltage is returned to the voltage conversion unit via the capacitance, and the voltage dividing unit charges. The output voltage is increased before completion.

According to the present invention, it is possible to provide a semiconductor device provided with a voltage conversion circuit capable of supplying a stable voltage while suppressing an increase in current consumption, and a control method for the semiconductor device.

In the semiconductor device according to the first embodiment, (a) is a block diagram, and (b) is a timing chart showing an operation waveform of each part. In the semiconductor device according to the second embodiment, (a) is a block diagram, and (b) is a timing chart showing an operation waveform of each part. In the semiconductor device according to the third embodiment, (a) is a block diagram, and (b) is a timing chart showing an operation waveform of each part. It is a block diagram which shows an example of the short circuit of the semiconductor device which concerns on 3rd Embodiment.

Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. In the following embodiment, a memory device as a semiconductor device and a booster circuit control method built in the memory device as a control method of the semiconductor device and controlling a booster circuit that generates a potential required for data access will be exemplified and described. ..

[First Embodiment]
The memory device 50 and the booster circuit control method according to the present embodiment will be described with reference to FIG.

As shown in FIG. 1, the memory device 50 includes a booster circuit 52 and a memory unit 54.

The booster circuit 52 includes an oscillation circuit 1, a booster clock generation circuit 2, a charge pump circuit 3, a reference voltage generation circuit 4, a voltage divider circuit 5, a constant current source circuit 6, a timing generation circuit 7, a sensor circuit 8, and a step-down circuit 10. It includes a voltage divider circuit 11, an NaCl transistor 16, 17-1 to 17-4, and 18-1 to 18-4.

The charge pump circuit 3 is a circuit for increasing the voltage by combining a capacitor and a switch that operate in synchronization with the drive clock signal, and in the present embodiment, the voltage is increased with reference to the power supply voltage of the potential VDD. , Output voltage is output as VCP.

The boost clock generation circuit 2 converts the clock signal from the oscillation circuit 1 into the drive clock signal for operating the charge pump circuit 3. The oscillation circuit 1 is an oscillator for the boost clock generation circuit 2 to generate a clock signal that is the source of the drive clock signal. The oscillation circuit 1 is controlled to start / stop by the control signal SAO from the sensor circuit 8.

The step-down circuit 10 steps down the output voltage VCP to generate a voltage for operating the memory unit 54. In the present embodiment, the step-down voltage from the step-down circuit 10 is output as an output voltage VREG via the NaOH transistor 16. The reference voltage VREF2 from the reference voltage generation circuit 4 described later is input to the non-inverting input of the step-down circuit 10, and the comparison voltage VDET2 described later is input to the inverting input. The NTM transistors 17-2 and 18-2 connected in series are connected to the step-down circuit 10. The NOTE transistor 18-2 is a transistor that supplies a constant current to the step-down circuit 10, and the step-down circuit 10 operates by supplying the constant current. The NOTE transistor 17-2 is a switch that controls whether the constant current is passed or cut off.

The voltage dividing circuit 11 divides the output voltage VREG to generate a comparative voltage VDET2. The voltage divider circuit 11 includes a polyclonal diode connection row 11a and a capacitance 11b. The comparative voltage VDET2 is taken out from the middle of the polyclonal diode connection row 11a, and the capacitance 11b is connected between the output voltage VREG and the comparative voltage VDET2. The nanotube transistors 17-1 and 18-1 connected in series are connected to the polyclonal diode connection row 11a. The MIMO transistor 18-1 is a transistor that supplies a constant current to the polyclonal diode connection row 11a, and the polyclonal diode connection row 11a operates by being supplied with the constant current. The NOTE transistor 17-1 is a switch that controls whether the constant current is passed or cut off.

The voltage dividing circuit 5 divides the output voltage VCP and generates a comparative voltage VDET which is a monitor voltage of the output voltage VCP. The configuration of the voltage dividing circuit 5 is not particularly limited, and is composed of a polyclonal diode connection row, a resistance row, and the like, but in the present embodiment, it is a polyclonal diode connection row. The nanotube transistors 17-3 and 18-3 connected in series are connected to the voltage dividing circuit 5. The NOTE transistor 18-3 is a transistor that supplies a constant current to the voltage dividing circuit 5, and the voltage dividing circuit 5 operates by supplying the constant current. The NOTE transistor 17-3 is a switch that controls whether the constant current is passed or cut off.

The reference voltage generation circuit 4 generates the reference voltage VREF 2 and the reference voltage VREF supplied to the sensor circuit 8. The reference voltage generation circuit 4 is controlled to start / stop by the deep power down signal DPPDN. The deep power down according to the present embodiment means a power down that stops most of the operations of the circuit associated with the memory device 50 among the power downs, and is supplied from a control circuit or the like (not shown). The deep power down signal DPPDN is an example of a control signal, and other appropriate control signals may be used.

The sensor circuit 8 monitors the voltage level of the output voltage VCP, and generates a control signal SAO that controls the oscillation circuit 1 according to the monitored voltage level. NMOS transistors 17-4 and 18-4 connected in series are connected to the sensor circuit 8. The NOTE transistor 18-4 is a transistor that supplies a constant current to the sensor circuit 8, and the sensor circuit 8 operates by supplying the constant current. The NOTE transistor 17-4 is a switch that controls whether the constant current is passed or cut off.

The timing generation circuit 7 is connected to the gates of the nanotube transistors 17-1 to 17-4, and the activation signal ENSA controls the on / off of the nanotube transistors 17-1 to 17-4. The constant current source circuit 6 is connected to the gates of the nanotube transistors 18-1 to 18-4, and the nanotube transistors 18-1 to 18-4 supply a bias voltage VBIAS for passing a constant current. The timing generation circuit 7 and the constant current source circuit 6 are controlled by the deep power down signal DPPDN. The sources of the NMOS transistors 18-1 to 18-4 are connected to ground (GND).

The memory unit 54 includes a plurality of memory cells 30 and a driver circuit 9 for driving the plurality of memory cells 30. The driver circuit 9 supplies a necessary voltage to the word line connected to the memory cell 30 based on the decoded signal obtained by decoding the address signal. For example, when the memory device 50 is a flash memory with advanced miniaturization, the output voltage VREG generated by the booster circuit 52 is supplied to the word line of the memory cell 30 through the driver circuit 9 to perform a read operation. The memory device 50 according to the present embodiment has a low-speed operation mode for reading at a low speed and a high-speed operation mode for reading at a high speed.

Next, the operation of the booster circuit 52 will be described with reference to FIG. 1 (b). FIG. 1B is a timing chart showing operation waveforms of each of the deep power down signal DPPDN, the output voltage VCP of the charge pump, the output voltage VREG of the step-down circuit, and the decoded signal. When the deep power down signal DPPDN is released, the timing generation circuit 7, constant current source circuit 6, sensor circuit 8, voltage divider circuit 5, step-down circuit 10, voltage divider circuit 11, and reference voltage generator circuit 4 are activated. ..

When the deep power down signal DPPDN is released at time t1, the reference voltage VREF is generated from the reference voltage generation circuit 4, the bias voltage VBIAS of the constant current source is generated from the constant current source circuit 6, and the activation signal is generated from the timing generation circuit 7. ENSA occurs. The sensor circuit 8 and the voltage dividing circuit 5 receive the activated bias voltage VBIAS and the activation signal ENSA to start operation.

The control signal SAO, which is the output signal of the sensor circuit 8, is used until the comparative voltage VDET generated from the voltage dividing circuit 5 becomes larger than the reference voltage VREF, that is, until the output voltage VCP of the charge pump circuit 3 becomes larger than the boost target voltage VPWL. High level (hereinafter referred to as "H"). The oscillation circuit 1 continues to generate a clock signal while the control signal SAO is H, and drives the charge pump circuit 3 via the boost clock generation circuit 2.

When the voltage of the output voltage VCP of the charge pump circuit 3 reaches the boost target voltage VPWL, the control signal SAO becomes a low level (hereinafter, “L”), and the control of the output voltage VCP shifts to the intermittent operation controlled by the sensor circuit 8. ..

On the other hand, the step-down circuit 10 and the voltage dividing circuit 11 also receive the activated bias voltage VBIAS and the activation signal ENSA to start the operation, and converge the output voltage VREG to the target voltage VWL.

When the memory device 50 shifts from low-speed operation to high-speed operation at time t2, the current consuming the output voltage VREG rapidly increases due to the driver circuit 9, the balance of the step-down circuit 10 is disturbed, and the output voltage VREG drops temporarily. When the output voltage VREG drops, the node voltage of the comparative voltage VDET2 is lowered by the coupling action of the capacitance 11b, the gate voltage of the NOTE transistor 16 which is the output driver of the step-down circuit 10 is raised, and the output voltage VREG rises at time t3. To start.

After that, the output voltage VREG is controlled to the target voltage VWL so that the polyclonal diode connection row 11a completes the charging required for the comparison voltage VDET2 to become the divided voltage of the output voltage VREG (time t4). The effect of the output voltage from time t2 to t4 is called the voltage drop amount ΔVWL.

As described in detail above, according to the semiconductor device according to the present embodiment and the control method of the semiconductor device, when the load of the output voltage VREG is switched to the high load associated with the high-speed operation mode, the polyclonal diode connection row 11a Since the output voltage VREG starts to rise before the comparative voltage VDET2 is charged to the divided voltage of the output voltage VREG, the voltage drop amount ΔVWL of the output voltage VREG can be reduced. Therefore, since it is possible to throttle the current flowing through the polyclonal diode connection row 11a, it is possible to achieve both reduction of operating current and stabilization of memory cell reading (stabilization of output voltage VREG).

[Second Embodiment]
The memory device 50A and the booster circuit control method according to the present embodiment will be described with reference to FIG. The memory device 50A according to the present embodiment is a form in which the booster circuit 52 of the memory device 50 is replaced with the booster circuit 52A. Therefore, the same reference numerals are given to the same configurations, and detailed description thereof will be omitted.

As shown in FIG. 2A, in the booster circuit 52A, a timing generation circuit 13 and a discharge circuit 12 are added to the booster circuit 52.

The timing generation circuit 13 receives the mode signal FMODE as an input, and generates a discharge signal DISC according to the mode signal FMODE. The mode signal FMODE defines a read operation speed of the memory device 50A equipped with the booster circuit 52A. When the mode signal FMODE is L, it is in a low speed operation (read) mode, and when it is H, it is in a high speed operation (read) mode.

The discharge circuit 12 includes a polyclonal diode connection row 12a and an HCl transistor 12b connected to the output voltage VREG. A discharge signal DISC is input to the gate of the nanotube transistor 12b, and when the nanotube transistor 12b is turned on by the discharge signal DISC, the discharge circuit 12 is activated.

The operation of the booster circuit 52A will be described with reference to FIG. 2 (b). FIG. 2B is a timing chart showing the operation waveforms of the deep power down signal DPPDN, the output voltage VCP of the charge pump, the output voltage VREG of the step-down circuit 10, the mode signal FMODE, the discharge signal DISC, and the decoded signal. be.

When the deep power down signal DPPDN is released at time t1, the output voltage VCP of the charge pump circuit 3 and the output voltage VREG of the step-down circuit operate in the same manner as described in FIG. 1 (b). In the example of FIG. 2B, a low-speed operation decoded signal is input at time t2.

After that, when the mode signal FMODE is switched from the low-speed operation mode to the high-speed operation mode at time t3, immediately after that, the discharge signal DISC becomes H, and a load current equivalent to the load current during high-speed operation flows through the discharge circuit 12. ..

After the output voltage VREG converges to the target voltage VWL, the discharge signal DISC becomes L at time t4, and high-speed operation (reading) is started. During the period when the discharge signal DISC is H, the high-speed operation setup period SUT is set, and the high-speed read operation is prohibited.

According to the memory device and the booster circuit control method according to the present embodiment, the high-speed operation setup time can be shortened at the time of high-speed switching, and after the high-speed operation setup period SUT, the output voltage VREG is stably irrespective of the voltage drop amount ΔVWL. The read operation can be performed.

In addition, in this embodiment, the embodiment provided with the capacitance 11b in addition to the discharge circuit 12 has been described as an example, but since the functions of the discharge circuit 12 and the capacitance 11b are common, the embodiment excluding the capacitance 11b is used. May be good.

[Third Embodiment]
A booster circuit control method for the memory device 50B and the booster circuit 52B according to the present embodiment will be described with reference to FIG. In the present embodiment, the booster circuit 52 is changed to the booster circuit 52B in the memory device 50, and the booster circuit 52B changes the voltage divider circuit 11 of the booster circuit 52 to the voltage divider circuit 20. In the voltage dividing circuit 20 according to the present embodiment, a short circuit 14 and a timing generation circuit 15 are added to the voltage dividing circuit 11. Since other configurations are the same as those of the memory device 50, the same reference numerals are given to the same configurations, and detailed description thereof will be omitted.

As shown in FIG. 3A, the voltage divider circuit 20 includes a polyclonal diode connection row 11a, a capacitance 11b, and a short circuit 14.

The short circuit 14 is connected between the terminal for outputting the voltage divider voltage VDET3 of the polyclonal diode connection row 11a and the terminal on the comparison voltage VDET2 side of the capacitance 11b. The short circuit 14 is controlled by the activation signal ENSK described below and functions as a switch that connects or disconnects between the polyclonal diode connection row 11a and the capacitance 11b.

FIG. 4 shows a specific circuit example of the short circuit 14. The short circuit 14 includes a pass transistor (transfer gate) 21 and an inverter 22. Then, based on the activation signal ENSK, the terminal of the voltage dividing voltage VDET3 and the terminal of the comparative voltage VDET2 are connected or disconnected. According to this short circuit 14, noise is canceled by the polyclonal transistor and the nanotube transistor, so that when the short circuit 14 is turned off (cut off), the potential of the comparison voltage VDET2 fluctuates due to the coupling noise, and the activation signal ENSK Has the effect of suppressing the deviation of the control voltage of the output voltage VREG during the period of L.

The timing generation circuit 15 inputs the deep power down signal DPPDN and outputs the activation signal ENSK. The activation signal ENSK is supplied to the gate and short circuit 14 of the nanotube transistor 17-1 to control the operation of the nanotube transistor 17-1 and the short circuit 14.

Next, the operation of the booster circuit 52B will be described with reference to FIG. 3 (b). FIG. 3B is a timing chart showing operation waveforms of the deep power down signal DPPDN, the output voltage VCP of the charge pump circuit 3, the output voltage VREG of the step-down circuit 10, and the activation signal ENSK.

The activation signal ENSK output from the timing generation circuit 15 has an activation period of at least the period from when the deep power down signal DPPDN becomes L until the output voltage VREG of the step-down circuit 10 converges to the target voltage VWL. It is H as T1 (between time t1 and t2). When the activation signal ENSK is set to H, the short circuit 14 is conducted and the Now's transistor 17-1 is turned on. After that, the activation signal ENSK is set as the period H of the activation period T3 at the interval of the activation cycle T2 from the time t3 (between the time t3 and t4). In FIG. 3B, the activation cycle T2 is started at time t5 and t6.

During the period when the activation signal ENSK is L, the short circuit 14 is cut off, the comparative voltage VDET2 is maintained by the charge stored in the capacitance 11b, and the output voltage VREG is controlled toward the boost target voltage VPWL. Before the charge stored in the capacitance 11b decreases due to the leak between the electrodes of the capacitance 11b or the leakage of the diffusion layer of the short circuit 14, the control voltage of the output voltage VREG drops, and the allowable voltage drop of the target voltage VWL is exceeded. By recharging the capacitance 11b during the activation period T3 (ie, every activation cycle T2), control of the output voltage VREG is maintained towards convergence to the target voltage VWL.

According to the present embodiment, in addition to achieving the same effect as that of the above-described embodiment, the current flowing through the voltage dividing circuit 20 can be cut off during the operation except for the activation period T3, so that timing is generated. Even if the increase in current consumption due to the timer operation of the circuit 15 is taken into consideration, the operating current can be further reduced. Further, as compared with the case where the conventional voltage divider circuit having no capacitance 11b is intermittently operated, the output voltage VREG drops due to the current flowing through the voltage divider circuit 20 during the activation cycle T2 excluding the activation period T3. Since there is no such thing, the output voltage VREG can always be controlled even during the intermittent operation period, so that the activation cycle T2 (intermittent cycle) can be lengthened and the operating current is reduced.

1 Oscillation circuit 2 Boost clock generation circuit 3 Charge pump circuit 4 Reference voltage generation circuit 5 Voltage divider circuit 6 Constant current source circuit 7 Timing generator 8 Sensor circuit 9 Driver circuit 10 Step-down circuit 11 Voltage divider circuit 11a ProLiant diode connection row 11b Capacity 12 Discharge circuit 12a ProLiant diode connection row 12b CICS transistor 13 Timing generation circuit 14 Short circuit 15 Timing generation circuit 16, 17-1 to 17-4, 18-1 to 18-4 NOTE transistor 20 voltage divider circuit 21 pass transistor 22 OR Circuit 30 Memory cell 50, 50A, 50B Memory device 52, 52A, 52B Booster circuit 54 Memory section

Claims (7)

It has a first mode that operates at a first speed and a second mode that operates at a second speed that is faster than the first speed.
A first input unit for inputting a power supply voltage, a second input unit for inputting a reference voltage, and a third input unit for inputting a comparison voltage are provided, and the reference voltage is compared with the comparison voltage. A voltage converter that converts the power supply voltage and outputs it as an output voltage from the output section,
A voltage dividing section in which one terminal is connected to the output section and the voltage obtained by dividing the output voltage is used as the comparative voltage and output from the other terminal to the third input section.
One terminal is connected to the output unit and the other terminal is connected to the third input unit.
When the operation mode is switched from the first mode to the second mode, the decrease in the comparative voltage accompanying the decrease in the output voltage is fed back to the voltage conversion unit via the capacitance, and the voltage dividing unit is used. A semiconductor device in which the output voltage rises before the charging is completed. A switch connected between the other terminal of the capacitance and the other terminal of the voltage dividing portion,
The first period in which the switch is made conductive to charge the capacitance and the voltage dividing portion is charged, and the second period in which the switch is shut off and the charge stored in the capacitance is used to generate the comparative voltage. The semiconductor device according to claim 1, further comprising a control unit that controls the switches so as to arrive alternately. The control unit further controls the switch to conduct the switch for a third period longer than the period until the output voltage converges to the target voltage before the first period and the second period arrive. The semiconductor device according to claim 2. It has a first mode that operates at a first speed and a second mode that operates at a second speed that is faster than the first speed.
A first input unit for inputting a power supply voltage, a second input unit for inputting a reference voltage, and a third input unit for inputting a comparison voltage are provided, and the reference voltage is compared with the comparison voltage. A voltage converter that converts the power supply voltage and outputs it as an output voltage from the output section,
With the load connected to the output unit,
A voltage dividing section in which one terminal is connected to the output section and the voltage obtained by dividing the output voltage is used as the comparative voltage and output from the other terminal to the third input section.
The discharge unit connected to the output unit and
During a predetermined period after switching from the first mode to the second mode, the discharge is such that a current equivalent to the load current flowing through the load in the second mode flows through the discharge unit. A semiconductor device that includes a control unit that controls the unit. One terminal is connected to the output unit, and the other terminal further includes a capacitance connected to the third input unit.
When the operation mode is switched from the first mode to the second mode, the decrease in the comparative voltage accompanying the decrease in the output voltage is returned to the voltage conversion unit via the capacitance, and the voltage dividing unit is charged. The semiconductor device according to claim 4, wherein the output voltage rises before the completion of the above. The output unit is further provided with a plurality of memory cells as loads connected via a drive circuit.
The semiconductor device according to any one of claims 1 to 5, wherein the first mode is a mode for reading the memory cell at a low speed, and the second mode is a mode for reading the memory cell at a high speed. .. A first input unit having a first mode operating at a first speed and a second mode operating at a second speed faster than the first speed, and a reference voltage for inputting a power supply voltage. A voltage that is provided with a second input unit for input and a third input unit for inputting a comparison voltage, converts the power supply voltage based on the comparison between the reference voltage and the comparison voltage, and outputs the output voltage as an output voltage. The conversion unit, one terminal is connected to the output unit, the voltage division unit that outputs the voltage obtained by dividing the output voltage as the comparison voltage from the other terminal to the third input unit, and one terminal. Is a control method for a semiconductor device including a capacitance connected to the output unit and the other terminal connected to the third input unit, and the operation mode is switched from the first mode to the second mode. At that time, the decrease in the comparative voltage due to the decrease in the output voltage is fed back to the voltage conversion unit via the capacitance, and the output voltage is increased before the voltage dividing unit completes charging. Control method.

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