JP7040491B2 - A method for determining the gap size at the time of manufacturing a silicon single crystal and a method for manufacturing a silicon single crystal. - Google Patents

Description

The present invention relates to a method for determining a gap size at the time of producing a silicon single crystal and a method for producing a silicon single crystal.

Silicon wafers used as substrates for semiconductor devices are generally cut out from silicon single crystals grown by the Czochralski method (hereinafter, may be referred to as the "CZ method"), and are manufactured through processes such as polishing and heat treatment. To.
The defect distribution of a silicon single crystal is generally a value obtained by dividing the pulling speed V of the silicon single crystal by the temperature gradient G in the growth direction of the silicon single crystal immediately after pulling, with the distance from the crystal center to the outer edge as the horizontal axis. Can be shown in a diagram with the vertical axis. The temperature gradient G is considered to be generally constant during the process of pulling the silicon single crystal due to the thermal properties of the hot zone structure of the CZ furnace. Therefore, V / G can be controlled by adjusting the pulling speed V.

The defect distribution map as described above mainly includes a COP (Crystal Originated Particle) region, an OSF (Oxidation induced Stacking Fault) region, a Pv region, a Pi region, and an L / D (Large Dislocation) region. Shown.
COP is an aggregate of pores lacking atoms that should form a crystal lattice during the growth of a silicon single crystal.
The OSF region is adjacent to the COP region, and when thermal oxidation treatment is performed at a high temperature (generally 1000 ° C to 1200 ° C), OSF nuclei become apparent as OSF.
The Pv region is adjacent to the OSF region and is a defect-free region in which vacancies are predominant. The Pv region contains oxygen precipitate nuclei in the as-grown state, and when heat-treated, oxygen precipitates (BMD) are likely to be generated.
The Pi region is adjacent to the Pv region and is a defect-free region in which interstitial silicon type point defects are predominant. The Pi region contains almost no oxygen precipitation nuclei in the as-grown state, and BMD is unlikely to occur even after heat treatment.
L / D is an aggregate of interstitial silicon that is excessively incorporated between crystal lattices, and is a defect with dislocations (dislocation clusters). The L / D region is adjacent to the Pi region.

In recent years, there has been an increasing demand for silicon wafers having no defects on the entire surface, and a method for manufacturing a silicon single crystal capable of obtaining such a silicon wafer has been studied (see, for example, Patent Document 1).
Patent Document 1 describes a silicon single crystal having a pulling speed V and a temperature gradient G in a range including an OSF region and an N- region (defect-free region composed of only a Pv region and a Pi region) located outside the OSF region. It is disclosed that it will be raised.

Japanese Unexamined Patent Publication No. 11-199386

However, in the configuration as in Patent Document 1, there are not a few OSF regions in the silicon wafer, and it is not possible to obtain a defect-free silicon single crystal in the narrow sense described below.

An object of the present invention is to provide a method for determining a gap size at the time of manufacturing a silicon single crystal, which can obtain a large number of silicon wafers having only a defect-free region, and a method for manufacturing a silicon single crystal.
The defect-free region is a region excluding the FPD (Flow Pattern Defect) region and the L / D region in a broad sense, and means a region composed of only a Pv region and a Pi region in a narrow sense. Similarly, a defect-free silicon wafer means a silicon wafer in which the FPD (Flow Pattern Defect) region and the L / D region do not exist in the plane in a broad sense, and the Pv region and the Pi region in a narrow sense. Means a silicon wafer composed of only silicon wafers. The silicon wafer having only a defect-free region may be either a defect-free silicon wafer in a broad sense or a defect-free silicon wafer in a narrow sense.

The gap size determination method of the present invention is arranged above the pit so as to surround the pit containing the silicon melt, the pulling portion for pulling the silicon single crystal from the silicon melt, and the silicon single crystal being pulled. It is a method of determining the gap size between the lower end of the heat shield and the surface of the silicon melt at the time of manufacturing a silicon single crystal using a pulling device provided with the heat shield, and the silicon single is determined for each gap size. A step of simulating the relationship between the defect distribution of the crystal and the pulling speed of the silicon single crystal, and a step of specifying the margin of the pulling speed at which the silicon single crystal having only a defect-free region can be obtained based on the result of the simulation. The step of quantifying the defect distribution obtained in the simulation and specifying the first relationship between the value of the defect distribution, the margin of the pulling speed obtained in the simulation, and the gap size, and the pulling device. The defect distribution of the evaluation silicon single crystal manufactured using the method was quantified by the same method as the defect distribution obtained in the simulation, and the value of this defect distribution and the gap size at the time of manufacturing the evaluation silicon single crystal were obtained. Based on the step of specifying the second relationship of the above, and the first relationship and the second relationship, the margin of the pulling speed at the time of manufacturing the silicon single crystal for evaluation is estimated, and the estimated pulling is performed. It is characterized by carrying out a step of determining a gap size that is larger than the speed margin.

The margin of the pulling speed (hereinafter, may be referred to as “defect-free margin”) for obtaining a silicon single crystal having only a defect-free region varies depending on the gap size. The defect-free margin means the difference between the upper limit value and the lower limit value of the silicon single crystal pulling speed in which the entire surface of the silicon wafer obtained from the silicon single crystal is a defect-free region.
As described above, the defect-free region may be either a defect-free region in a broad sense or a defect-free region in a narrow sense. Hereinafter, the present invention will be described with the defect-free region as a defect-free region in a narrow sense.
The gap size with the largest defect-free margin can be obtained by simulation. The simulation includes not only computer simulation by numerical calculation but also simulation by experiment.
If this obtained gap size is applied to the pulling device, it should be the manufacturing condition that maximizes the defect-free margin, but in reality, the thermal environment becomes different from the simulation due to deterioration of the components of the hot zone. The defect-free margin may not be the largest. In this case, if the pulling speed changes during manufacturing, the pulling speed may be out of the defect-free margin range, and a silicon single crystal having a defect region may be manufactured.
In the present invention, the large defect-free margin when the silicon single crystal for evaluation is manufactured by using the first relationship based on the simulation result and the second relationship based on the defect distribution of the silicon single crystal for evaluation. The size is estimated and the gap size is determined so that the defect-free margin is larger than the estimated size. Therefore, by using this manufacturing gap size, it is possible to manufacture a silicon single crystal with a defect-free margin larger than that at the time of manufacturing a silicon single crystal for evaluation. As a result, even if the pulling speed changes, it is possible to prevent the pulling speed from being out of the defect-free margin range, and many silicon wafers having only a defect-free region can be obtained.

In the gap size determination method of the present invention, the radius of the circular defect region and the width of the ring-shaped defect region in the wafer surface obtained from the silicon single crystal, or the defect in the single crystal radial direction corresponding to the radius and the width. It is preferable that the defect distribution is quantified according to the distribution.

According to the present invention, the defect distribution can be easily quantified based on the OSF and oxygen precipitate (BMD) that can be visually confirmed by the heat treatment.

In the gap size determination method of the present invention, it is preferable that the numerical value of the defect distribution is a dimensionless value.

In the gap size determination method of the present invention, it is preferable that the defect distribution is the distribution of the OSF region or the distribution of the Pv region.

According to the present invention, based on the OSF and oxygen precipitate (BMD) that can be visually confirmed by heat treatment, it is possible to easily determine the gap size that increases the defect-free margin as compared with the case of producing a silicon single crystal for evaluation.

In the gap size determination method of the present invention, the numerical value of the defect distribution is the ratio of the radius of the circular OSF region to the width of the ring-shaped OSF region, or the radius of the circular Pv region and the ring-shaped Pv region. It is preferably a ratio to the width.

According to the present invention, based on the ratio of the radius of the circular OSF region to the width of the ring-shaped OSF region, or the ratio of the radius of the circular Pv region to the width of the ring - shaped Pv region . The defect distribution can be easily quantified.

The method for producing a silicon single crystal of the present invention is characterized in that a silicon single crystal is produced using the gap size determined by the above-mentioned gap size determining method.

According to the present invention, it is possible to manufacture a silicon single crystal capable of obtaining a large number of silicon wafers having only a defect-free region.

In the method for producing a silicon single crystal of the present invention, it is preferable that the gap size determination method determines the gap size so that the margin of the pulling speed is maximized.

According to the present invention, it is possible to maximize the change tolerance of the pulling speed, and it is possible to obtain many silicon wafers in which only a defect-free region exists.

The schematic diagram of the pulling device which concerns on the related technique of this invention and one Embodiment. The flowchart of the manufacturing method of a silicon single crystal in the said embodiment. The schematic diagram which shows an example of the relationship between the pulling speed of a silicon single crystal and the defect distribution. The schematic diagram which shows an example of the relationship between the pulling speed of a silicon single crystal and the defect distribution. Explanatory drawing which shows the relationship between the pulling speed and the existence state of the ring-shaped and disk-shaped OSF regions. The graph which shows the relationship between the disk radius and the disk ring ratio of the OSF area based on the simulation result. The graph which shows the relationship between the disk radius and the disk ring ratio of the OSF region based on the simulation result and the manufacturing record of the silicon single crystal for evaluation using the temporary gap size. It is explanatory drawing which shows the relationship between the pulling speed in the modification of this invention, and the existence state of a ring-shaped and a disk-shaped Pv region. It is the result of Experiment 1 in the Example of this invention, and is the graph which shows the relationship between the disk radius and the disk ring ratio of the OSF region based on the simulation result and the production record of the silicon single crystal for evaluation using the production gap size. The graph which is the result of the experiment 2 in the said Example, and shows the yield effect of the experimental examples 1 and 2.

[Related Techniques of the Present Invention]
First, the related technique of the present invention will be described with reference to the drawings.
As shown in FIG. 1, the silicon single crystal SM pulling device 1 is a device used in the CZ method (Czochralski method) and includes a device main body 2.
The apparatus main body 2 includes a chamber 21, a crucible 22 arranged in the chamber 21, a heater 23 for heating the crucible 22, a pulling portion 24, a heat shield 25, a heat insulating material 26, and a crucible drive unit. It is equipped with 27.
As shown by the alternate long and short dash line, the pulling device 1 is a device used in the MCZ (Magnetic field applied Czochralski) method, and has a pair of electromagnetic coils 28 arranged on the outside of the chamber 21 with the crucible 22 interposed therebetween. You may have.

A gas introduction port 21A for introducing an inert gas such as Ar gas into the chamber 21 is provided in the upper part of the chamber 21. At the lower part of the chamber 21, a gas exhaust port 21B for discharging the gas in the chamber 21 is provided. A heat insulating material 26 is provided on the inner surface of the chamber 21.

The crucible 22 melts silicon into a silicon melt M. The crucible 22 includes a quartz crucible 221 and a graphite crucible 222 accommodating the quartz crucible 221. The quartz crucible 221 is replaced every time one or more silicon single crystal SMs are grown. On the other hand, the graphite crucible 222 is not replaced every time one silicon single crystal SM is manufactured, and is replaced when it is considered that the quartz crucible 221 cannot be properly supported.

The heater 23 is arranged around the crucible 22 and melts the silicon in the crucible 22. A bottom heater 231 as shown by the alternate long and short dash line may be further provided below the crucible 22.
The pull-up unit 24 includes a cable 241 to which the seed crystal SC is attached to one end, and a pull-up drive unit 242 that raises and lowers and rotates the cable 241.
The heat shield 25 is provided so as to surround the silicon single crystal SM, and blocks radiant heat radiated upward from the heater 23.
The crucible drive unit 27 includes a support shaft 271 that supports the graphite crucible 222 from below, and rotates and raises and lowers the crucible 22 at a predetermined speed.
The hot zone in the pulling device 1 is a chamber 21, a crucible 22, a heater 23, a cable 241, a heat shield 25, a heat insulating material 26, a support shaft 271, a silicon melt M, a silicon single crystal SM, and the like.

[Embodiment]
[Manufacturing method of silicon single crystal]
Next, a method for producing a silicon single crystal SM according to an embodiment of the present invention will be described.
In this embodiment, a case where a silicon single crystal SM having a straight body portion having a diameter of 300 mm after cylindrical grinding is manufactured is exemplified, but the diameter after cylindrical grinding may be 200 mm, 450 mm, or another size. good. Further, a dopant for adjusting the resistivity may or may not be added to the silicon melt M.

As a manufacturing method of the silicon single crystal SM, as shown in FIG. 2, a step (step S1) of carrying out the gap size determining method at the time of manufacturing the silicon single crystal SM and the manufacturing gap size determined by this determination method are applied. Then, the step of manufacturing the silicon single crystal SM for the product (step S2: manufacturing step) is carried out. Hereinafter, each step will be described in detail.

In the process of implementing the gap size determination method, first, for each size of the gap GP between the lower end of the heat shield 25 and the surface of the silicon melt M (hereinafter, the size of the gap GP is referred to as “gap size”), a silicon single crystal. The relationship between the defect distribution of SM and the pulling speed of silicon single crystal SM is simulated (step S11: simulation step).
The gap size is the distance between the lower end of the heat shield 25 and the surface of the silicon melt M at the time of manufacturing the silicon single crystal SM.
The simulation step is performed on at least the straight body portion SM1 of the silicon single crystal SM. Due to the influence of changes in the thermal history of the silicon single crystal SM during pulling, even if the gap size is the same, the defect distribution will differ depending on the position of the straight body portion SM1 in the length direction. Therefore, it is preferable that the simulation step is performed at a plurality of locations along the length direction of the straight body portion SM1. In the present embodiment, a simulation step is performed on a region obtained by dividing the straight body portion SM1 into three equal parts in the length direction. Of the regions divided into three equal parts, the upper end region in the pulling direction is referred to as a top region, the central region is referred to as a middle region, and the lower end region is referred to as a bottom region.
By this simulation step, a defect distribution can be obtained with the distance from the center of the silicon single crystal SM as the horizontal axis and the pulling speed V as the vertical axis. 3 and 4 show an example of the simulation results in which only the gap size in the straight body portion SM1 is different. In FIGS. 3 to 5, the left end of the horizontal axis represents the center position of the silicon single crystal SM, and the right end represents the outer edge position. Further, FIGS. 3 to 7 are views relating to the middle region of the silicon single crystal SM.
The simulation process can be an experimental simulation as well as a computer simulation by numerical calculation. Computer simulation by numerical calculation, which can save the cost and time for simulation, is preferable.

Next, the defect-free margin as shown in FIGS. 3 and 4 is specified based on the result of the simulation step (step S12: defect-free margin specifying step). The defect-free margin means a margin of the pulling speed at which a silicon single crystal SM having only a defect-free region can be obtained. The defect-free margin ranges from the lowest position of the OSF-Pv boundary line between the OSF region and the defect-free region to the highest position of the Pi-L / D boundary line between the defect-free region and the L / D region. ..

After that, the defect distribution obtained in the simulation step is quantified, and the first relationship between the value of the defect distribution, the defect-free margin specified in the defect-free margin specifying step, and the gap size is specified (step S13). : First relationship identification process).
In the present embodiment, first, the gap size at which the defect-free margin is maximized (hereinafter, the gap size at which the defect-free margin is maximum may be referred to as “temporary gap size”) is specified. The defect-free margin changes depending on the gap size. For example, when a graph is created in which the gap size is on the horizontal axis and the defect-free margin is on the vertical axis, a mountain-shaped graph is obtained. That is, there is only one gap size that maximizes the defect-free margin. Therefore, the temporary gap size is specified based on the results of a plurality of simulations in which only the gap size is changed for the same location.

Next, for example, based on the defect distribution of the temporary gap size as shown in FIG. 5, the generation state of the OSF region when the silicon single crystal SM is pulled up at a velocity V ₁ such that the OSF region exists is shown. grasp. The silicon wafer obtained from this silicon single crystal SM has a disk-shaped (circular) OSF region including the center thereof. Outside the disk-shaped OSF region, there is a ring-shaped OSF region sandwiching the defect-free region.
Next, the radius of the disk-shaped OSF region and the width of the ring-shaped OSF region are obtained as the disk radius and the ring width, respectively. Further, the disk radius and the ring width when the silicon single crystal SM is manufactured at another pulling speed such that the OSF region exists are obtained. That is, the defect distribution obtained in the simulation process is quantified.

Further, based on the defect distribution when the gap size is 1 mm larger than the temporary gap size and the defect distribution when the gap size is 1 mm smaller than the temporary gap size, the disk radius and the ring width when the gap size is pulled up at a plurality of pulling speeds are obtained.
Then, based on the defect distribution shown in FIG. 5, comparison data is created with the disk radius as the horizontal axis and the ring width divided by the disk radius as the vertical axis as shown in FIG. This comparison data includes the numerical value of the defect distribution obtained by the simulation (disk radius, disk ring ratio), the defect-free margin obtained by the simulation (maximum defect-free margin), and the gap size (temporary gap size). , Temporary gap size ± 1 mm).
This comparison data is created for each of the top area, middle area, and bottom area. The comparison data may be created by a computer or by an operator.

Next, the gap size of the pulling device 1 is set to the temporary gap size, and the silicon single crystal SM for evaluation is manufactured (step S14: single crystal manufacturing step for evaluation).
In the evaluation single crystal manufacturing process, when manufacturing the top region, middle region, and bottom region, the gap size is set to the temporary gap size corresponding to each region, and the pulling speed is ring-shaped or disk-shaped in each region. Set the speed so that the OSF region exists. As the speed at which the ring-shaped and disk-shaped OSF regions exist, for example, the speed V ₁ at which the OSF region exists based on the defect distribution in which the gap size is a temporary gap size, as shown in FIG. It may be set or it may be set based on the past manufacturing results.
In the present embodiment, a plurality of evaluation silicon single crystal SMs having ring-shaped and disk-shaped OSF regions are manufactured.

Next, the defect distribution of the silicon single crystal for evaluation is quantified by the same method as the defect distribution obtained by the simulation, and the value of this defect distribution and the gap size at the time of manufacturing the silicon single crystal for evaluation are second. (Step S15: second relationship specifying step).
In the present embodiment, first, a silicon wafer is acquired from the straight body portion SM1 of the silicon single crystal SM for evaluation, and a process of exposing the OSF region is performed. As the actualization treatment, it can be exemplified that the heat treatment is performed for 3 hours in an oxygen atmosphere of 1000 ° C., and then the heat treatment is further performed for 2 hours in an oxygen atmosphere of 1150 ° C. After that, the ring width and the disk radius of the exposed OSF region are measured. The above processing is performed on the silicon wafers acquired from each region in the plurality of evaluation silicon single crystal SMs. The number of silicon wafers acquired from each region may be one or a plurality of silicon wafers. Further, only one silicon single crystal SM for evaluation may be manufactured, and a plurality of silicon wafers may be obtained from the silicon single crystal SM.
Then, the relationship between the disc radius and the disc ring ratio based on the measurement result of each silicon wafer is specified. That is, the second relationship between the numerical value (disk radius, disc ring ratio) of the defect distribution of the silicon single crystal SM for evaluation and the gap size at the time of manufacturing the silicon single crystal SM for evaluation is specified.

After that, based on the first relationship and the second relationship, the defect-free margin at the time of manufacturing the silicon single crystal SM for evaluation is estimated, and the manufacturing gap size is set to be larger than the estimated defect-free margin. Determine (step S16: manufacturing gap size determination step).
In the present embodiment, first, the first relationship represented by the comparative data and the second relationship are compared, and it is determined whether or not the defect-free margin is the largest at the time of manufacturing the silicon single crystal SM for evaluation. do. Since both of these are data obtained based on the generation status of OSF, they correspond to the defect distribution of the silicon single crystal SM for simulation results and evaluation.

For example, as shown in FIG. 7, the measurement result (manufacturing record (second relationship)) of the OSF region in each silicon wafer is plotted on the comparison data of FIG. If the silicon single crystal SM is manufactured under the same manufacturing conditions, the measurement results of the OSF region of the silicon wafer obtained from these should be the same. It may be different as shown in 7.
Then, when this measurement result is almost the same as the comparison data in the temporary gap size, it is estimated that the defect-free margin is the largest, and the temporary gap size is determined as the manufacturing gap size. On the other hand, when the measurement result deviates from the comparison data by a predetermined amount, it is estimated that the defect-free margin is not the largest, and a size other than the temporary gap size is determined as the manufacturing gap size.

For example, the reference approximation line L _S of the comparison data in the temporary gap size, the first comparison approximation line L ₁ of the comparison data when it is 1 mm larger than the temporary gap size, and the second comparison of the comparison data when it is 1 mm smaller than the temporary gap size. Approximate line L ₂ and the actual approximate line N of the measurement results of the silicon wafer are obtained. Then, the manufacturing gap size is determined based on the distance between each approximation line L _S , L ₁ , L ₂ and the actual approximation line N.

In the result shown in FIG. 7, the actual approximation line N is located substantially in the middle between the reference approximation line L _S and the first comparison approximation line L ₁ . In this case, it is estimated that the manufacturing conditions when the temporary gap size is applied in the pulling device 1 correspond to the manufacturing conditions when a size 0.5 mm larger than the temporary gap size is applied in the simulation. According to this estimation result, it is considered that the manufacturing conditions when the size 0.5 mm smaller than the temporary gap size is applied correspond to the manufacturing conditions when the temporary gap size is applied in the simulation. Therefore, a size 0.5 mm smaller than the temporary gap size is determined as the manufacturing gap size.
Further, when the actual approximation line N is located between the reference approximation line L _S and the second comparison approximation line L ₂ , only the length corresponding to the distance between the actual approximation line N and the reference approximation line L _S is obtained. , A size larger than the temporary gap size is determined as the manufacturing gap size. For example, the actual approximation line N is located at the position of "0.3" when the position of the reference approximation line L _S is "0" and the position of the second comparison approximation line L ₂ is "1". In this case, a size 0.3 mm larger than the temporary gap size is determined as the manufacturing gap size.

On the other hand, when the actual approximation line N almost coincides with the reference approximation line L _S , the manufacturing conditions when the temporary gap size is applied in the pulling device 1 correspond to the manufacturing conditions when the temporary gap size is applied in the simulation. Then, the temporary gap size is determined as the manufacturing gap size.
As described above, by determining the manufacturing gap size so that the actual approximation line N coincides with the reference approximation line L _S , the manufacturing condition having the largest defect-free margin is obtained.
This manufacturing gap size determination step is performed for each of the top region, middle region, and bottom region. The manufacturing gap size determination step may be performed by a computer or by an operator.

In the above processing, the manufacturing gap size was determined based on the existence status of the ring-shaped and disk-shaped OSF regions, but as shown in FIG. 8, the manufacturing gap size was determined based on the existence status of the ring-shaped and disk-shaped Pv regions. The manufacturing gap size may be determined. In this case, the pulling speed at the time of manufacturing the silicon single crystal SM for simulation or evaluation may be set to a speed V ₂ or the like that generates a ring-shaped or disk-shaped Pv region. As a treatment for making the Pv region manifest, it can be exemplified that a heat treatment is performed for 3 hours in an oxygen atmosphere of 780 ° C., and then a heat treatment is further performed in an oxygen atmosphere of 1000 ° C. for 16 hours.

After that, the manufacturing process (step S2) is performed.
In the manufacturing process, the silicon single crystal SM for the product is manufactured using the manufacturing gap size determined in the process of step S1 at the time of manufacturing each of the top region, the middle region, and the bottom region.

[Action and effect of the embodiment]
According to the above embodiment, in the manufacturing gap size determination step, the size of the defect-free margin when the silicon single crystal SM for evaluation is manufactured is estimated, and the gap size is made larger than the estimated size. Is determined as the manufacturing gap size. By using this manufacturing gap size in the manufacturing process, it is possible to manufacture the silicon single crystal SM for the product in a state where the defect-free margin is larger than that at the time of manufacturing the silicon single crystal SM for evaluation. Therefore, even if the pulling speed changes, it is possible to prevent the pulling speed from being out of the defect-free margin range, and it is possible to obtain many silicon wafers in which only the defect-free region exists.
In particular, in the present embodiment, by using the manufacturing gap size that maximizes the defect-free margin in manufacturing, the change tolerance of the pulling speed can be maximized, and more silicon wafers have only defect-free regions. can get.

In the manufacturing gap size determination step, the manufacturing gap size can be easily determined based on the positions of the reference approximation line L _S , the first and second comparison approximation lines L ₁ , and the actual approximation line N with respect to the comparison approximation line L ₂ .

[Modification example]
The present invention is not limited to the above embodiment, and various improvements and design changes can be made without departing from the gist of the present invention.
For example, the gap size determination method and the manufacturing method at the time of manufacturing a silicon single crystal were performed for each of the top region, middle region, and bottom region of the straight body portion SM1, but even if only one or two regions were performed. Alternatively, the straight body portion SM1 may be divided into two or four or more regions in the length direction.

In the manufacturing gap size determination step, the manufacturing gap size was determined based on the distance between _each approximation line L _S , L ₁ , L ₂ and the actual approximation line N. The manufacturing gap size may be determined based only on the comparison between the reference approximation line L _S and the actual approximation line N without obtaining L ₂ .
In the manufacturing gap size determination process, the first comparative approximation line L ₁ was obtained based on the defect distribution when the gap size was 1 mm larger than the temporary gap size, but other sizes such as 0.5 mm or 2 mm from the temporary gap size were obtained. The first comparative approximation line L ₁ may be obtained based on the defect distribution when the size is so large. The second comparative approximation line L ₂ may be obtained in the same manner.
In the manufacturing gap size determination step, in addition to the _first and _second comparative approximation lines L1 and L2, the third and third based on the defect distribution when the gap size is larger than the temporary gap size by, for example, 2 mm and 2 mm smaller. A fourth comparative approximation line may be obtained, and the manufacturing gap size may be determined using the third and fourth comparative approximation lines as well.
In the manufacturing gap size determination process, the plot data used to create the approximation lines L _S , L ₁ , L ₂ , N were not obtained, but only the plot data used to create the approximation lines L _S , L ₁ , L ₂ , N were compared. The manufacturing gap size may be determined.
The manufacturing gap size does not have to be the gap size at which the defect-free margin is the largest, at least as long as the defect-free margin is larger than that at the time of manufacturing the silicon single crystal SM for evaluation. For example, when the result shown in FIG. 7 is obtained, a size 0.5 mm smaller than the temporary gap size is determined as the manufacturing gap size, but a size 0.3 mm smaller may be determined as the manufacturing gap size.

In the manufacturing gap size determination process, the manufacturing gap size was determined based on the comparison data with the disk radius as the horizontal axis and the disc ring ratio obtained by dividing the ring width by the disk radius as the vertical axis. Other indicators may be used. Examples of the combination of the indexes on the horizontal axis and the vertical axis include a disk radius and a ring width.

Next, the present invention will be described in more detail with reference to Examples and Comparative Examples, but the present invention is not limited to these examples.

[Experiment 1]
Using the production gap size determined based on FIG. 7 in the above embodiment, a plurality of evaluation silicon single crystal SMs having ring-shaped and disk-shaped OSF regions were produced. Then, the disc radii and the disc ring ratio of a plurality of wafers obtained from the silicon single crystal SM for this evaluation were obtained, and these relationships were plotted in the graph shown in FIG.
The results are shown in FIG.

As shown in FIG. 9, the actual approximation line N ₁ based on the measurement result of the evaluation silicon single crystal SM manufactured with the manufacturing gap size is the actual approximation line N of the evaluation silicon single crystal SM manufactured with the temporary gap size. It was confirmed that the reference approximation line L _S was much closer than that.
Therefore, by using the manufacturing gap size obtained by the method for determining the gap size at the time of manufacturing the silicon single crystal SM in the manufacturing process, a silicon single crystal SM for a product can be manufactured with a defect-free margin increased. I was able to confirm that it was possible.

[Experiment 2]
[Experimental Example 1]
{Comparative Example 1}
The processing of steps S11 to S13 assuming that the hot zone is the A type pulling device 1 is performed, the temporary gap size is specified for each of the top region, the middle region, and the bottom region, and the specified temporary gap size is used as the comparative example 1. Silicon single crystal SM was manufactured. As the pulling speed of the silicon single crystal SM of Comparative Example 1, the median value within the defect-free margin in the simulation result to which the temporary gap size was applied was applied.
After that, among the silicon single crystal SMs of Comparative Example 1, a product region in which a silicon wafer (product wafer) having only a defect-free region can be obtained was specified. At this time, silicon wafers are acquired from a plurality of positions in the length direction of the straight body portion SM1, the region sandwiched by the product wafers is set as the product region, and the silicon wafers (defective wafers) having the OSF region, which is a defective region, are sandwiched. The area where the product is defective is defined as the defective product area.
Then, the value obtained by dividing the weight of the product area by the weight of the silicon raw material put into the crucible 22 was obtained as the yield of Comparative Example 1.

{Example 1}
Based on the generation status of OSF in the defective wafer obtained from the silicon single crystal SM of Comparative Example 1 , the treatments of steps S15 to S16 were performed, and the manufacturing gap size of the region where the defective wafer was obtained was determined. Then, the silicon single crystal SM of Example 1 was manufactured with a manufacturing gap size using the pulling device 1 having an A type hot zone. As the pulling speed of the silicon single crystal SM of Example 1, the same speed as that of Comparative Example 1 was applied.
After that, the product area of the silicon single crystal SM of Example 1 was specified, and the yield of Example 1 was determined in the same manner as in Comparative Example 1.

[Experimental Example 2]
{Comparative Example 2, Example 2}
Comparative Example 2 and Example 2 were subjected to the same processing as in Comparative Example 1 and Example 1 except that the hot zone used the B type pulling device 1 instead of the A type pulling device 1. Asked for yield

〔evaluation〕
The value obtained by subtracting the yield of Comparative Example 1 from the yield of Example 1 was obtained as the yield effect of Experimental Example 1, and the value obtained by subtracting the yield of Comparative Example 2 from the yield of Example 2 was used as the yield effect of Experimental Example 2. I asked. The results are shown in FIG.

As shown in FIG. 10, it was confirmed that the yield effect was 1% or more in both Experimental Examples 1 and 2.
From this, it was confirmed that many product wafers can be obtained by using the manufacturing gap size obtained by the gap size determining method at the time of manufacturing the silicon single crystal SM in the manufacturing process.

1 ... Pulling device, 22 ... Crucible, 24 ... Pulling part, 25 ... Heat shield, GP ... Gap, M ... Silicon melt, SM ... Silicon single crystal.

Claims (7)

A pulling device including a crucible for accommodating a silicon melt, a pulling portion for pulling a silicon single crystal from the silicon melt, and a heat shield arranged above the crucible so as to surround the silicon single crystal being pulled. A method for determining the gap size between the lower end of the heat shield and the surface of the silicon melt in the production of a silicon single crystal using the above method.
A process of simulating the relationship between the defect distribution of the silicon single crystal and the pulling speed of the silicon single crystal by computer simulation by numerical calculation for each gap size.
Based on the result of the simulation, the step of specifying the margin of the pulling speed at which the silicon single crystal having only the defect-free region is obtained, and
Based on the relationship between the specified pull-up speed margin and the gap size, the temporary gap size that maximizes the pull-up speed margin is specified, and the defect distribution obtained in the simulation is used in the temporary gap size. The process of quantifying the case of pulling up at a plurality of pulling speeds and specifying the first relationship between the value of this defect distribution and the temporary gap size, and
The defect distribution of the silicon single crystal for evaluation manufactured using the pulling device is quantified by the same method as the defect distribution obtained in the simulation, and the value of this defect distribution and the time of manufacturing the silicon single crystal for evaluation are manufactured. And the process of identifying the second relationship with the gap size of
Based on the first relationship and the second relationship, the margin of the pulling speed at the time of manufacturing the silicon single crystal for evaluation is estimated, and the gap size is larger than the estimated margin of the pulling speed. A method for determining a gap size, which comprises carrying out a step of determining. In the gap size determination method according to claim 1,
The defect distribution is quantified by the radius of the circular defect region and the width of the ring-shaped defect region in the wafer surface obtained from the silicon single crystal, or the defect distribution in the single crystal radial direction corresponding to the radius and the width. A method of determining a gap size, characterized in that In the gap size determination method according to claim 2,
A method for determining a gap size, wherein the value obtained by quantifying the defect distribution is a dimensionless value. In the gap size determination method according to any one of claims 1 to 3.
A method for determining a gap size, wherein the defect distribution is a distribution in an OSF region or a distribution in a Pv region. In the gap size determination method according to claim 4,
The value obtained by quantifying the defect distribution is the ratio between the radius of the circular OSF region and the width of the ring-shaped OSF region, or the ratio between the radius of the circular Pv region and the width of the ring-shaped Pv region. How to determine the gap size. A method for producing a silicon single crystal, which comprises producing a silicon single crystal using the gap size determined by the gap size determining method according to any one of claims 1 to 5. In the method for producing a silicon single crystal according to claim 6,
The method for determining a gap size is a method for producing a silicon single crystal, which comprises determining the gap size so that the margin of the pulling speed is maximized.

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