JP6484489B2 - Nitride semiconductor epitaxial wafer and manufacturing method thereof - Google Patents

Description

  The present invention relates to a nitride semiconductor epitaxial wafer and a method for manufacturing the same.

The nitride semiconductor is represented by a general formula In _x Al _y Ga _1-xy N (0 ≦ x <1, 0 ≦ y <1, 0 ≦ x + y <1). Since the nitride semiconductor can change the band gap in the range of 1.95 eV to 6 eV depending on the composition, it is researched and developed as a light emitting device material in a wide wavelength range from the ultraviolet region to the infrared region. Has been put to practical use.

  Moreover, the device using the nitride semiconductor is used for a power element or the like that operates at a high frequency and a high output. In particular, field effect transistors (FETs) such as high electron mobility transistors (HEMTs) are known as semiconductor devices suitable for amplification in a high frequency band.

  In an electronic device using the nitride semiconductor, a Si substrate is generally used as a method for suppressing the price of the device.

  However, since the crystal growth of the nitride semiconductor is performed at a high temperature around 1000 ° C., the epitaxial substrate on which the nitride semiconductor is epitaxially grown has a large warpage due to the difference in thermal expansion coefficient between Si and the nitride semiconductor. Arise.

  As a method for reducing the warpage of the epitaxial substrate, there is an epitaxial substrate for electronic devices disclosed in Japanese Patent Laying-Open No. 2010-153817 (Patent Document 1). This epitaxial substrate for electronic devices includes a group III nitride laminate formed by epitaxially growing a plurality of group III nitride layers on a Si single crystal substrate, and the Si single crystal substrate has a p-type impurity such as boron. The resistivity is adjusted to 0.01 Ω · cm or less by adding elements.

  In this way, the Si substrate itself is hardened to suppress warpage when the nitride semiconductor is grown.

  Further, there is a semiconductor bulk crystal disclosed in Japanese Patent Application Laid-Open No. 2012-197218 (Patent Document 2). In this semiconductor bulk crystal, the compound semiconductor single crystal is epitaxially grown by forming a cavity in such a manner that the base substrate and the compound semiconductor single crystal are in direct contact with each other or by forming irregularities on the main surface of the base substrate. The generation of cracks in the middle is suppressed.

  In this way, the epitaxial growth substrate is preliminarily roughened to grow a nitride semiconductor, thereby relaxing the strain of the epitaxial growth substrate and suppressing warpage and cracks at the edges.

JP 2010-153817 A JP 2012-197218 A

  However, the conventional method for reducing the warpage of the epitaxial substrate has the following problems.

  In other words, in the “epitaxial substrate for electronic devices” disclosed in Patent Document 1, warping caused by a difference in thermal expansion coefficient can be suppressed to some extent. However, when the temperature of the group III nitride layer is lowered after the completion of crystal growth, the group III nitridation in the outer peripheral portion of the Si single crystal substrate is caused by a volume change caused by a difference in thermal expansion coefficient between the growth substrate and the nitride semiconductor. Cracks occur in the physical layer portion, or defects such as nanopipes occur in the group III nitride layer.

  The generated cracks and the nanopipes become a cause of occurrence of leaks and the like, and there is a problem that device characteristics are deteriorated.

  In addition, the “semiconductor bulk crystal” disclosed in Patent Document 2 is not preferable from the viewpoint of manufacturing because it takes time and cost for the irregularity processing step of the base substrate.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a nitride semiconductor epitaxial wafer and a method for manufacturing the same that can suppress the occurrence of internal defects such as nanopipes and dislocations to reduce leaks and improve device characteristics.

In order to solve the above problems, the nitride semiconductor epitaxial wafer of the present invention is
An epitaxial growth substrate;
A nitride semiconductor layer epitaxially grown on the epitaxial growth substrate;
When the value of warpage in the substrate for epitaxial growth is a negative warp when it is negative, and when it is a convex warp when it is positive, it is within a range of −100 μm or more and less than +150 μm. And
The nitride semiconductor layer is characterized in that the value of crack length is in the range of 100 μm or more and less than 10,000 μm from the outer periphery.

In the nitride semiconductor epitaxial wafer of one embodiment,
The epitaxial growth substrate is one of Si, SiC, ZnO and sapphire,
The epitaxial growth substrate has a diameter of 3 inches or more and a thickness of 1500 μm or more.

In addition, the method of manufacturing the nitride semiconductor epitaxial wafer of the present invention is as follows:
An epitaxial growth step of epitaxially growing a nitride semiconductor on the epitaxial growth substrate;
In the epitaxial growth step, the nitride semiconductor warpage during the epitaxial crystal growth is at least once, from a downward convex warp to an upward convex warp, or from an upward convex warp to a downward convex warp. It is characterized by changing.

Further, in the method of manufacturing a nitride semiconductor epitaxial wafer of one embodiment,
The temperature increase rate of the epitaxial crystal growth temperature in the epitaxial growth step or the temperature decrease rate of the epitaxial crystal growth temperature after the epitaxial growth is set to 5 ° C./min to 80 ° C./min.

Further, in the method of manufacturing a nitride semiconductor epitaxial wafer of one embodiment,
The epitaxial growth step is
Epitaxially growing an AlN underlayer on the epitaxial growth substrate;
And epitaxially growing the nitride semiconductor on the AlN underlayer.

  As is clear from the above, the nitride semiconductor epitaxial wafer of the present invention has a warp value in the epitaxial growth substrate in the range of −100 μm or more and less than +150 μm, and a crack length value in the nitride semiconductor layer is Since it is within the range of 100 μm or more and less than 10000 μm from the outer periphery, the internal stress in the nitride semiconductor epitaxial wafer can be reduced.

  Therefore, in the nitride semiconductor device using the nitride semiconductor epitaxial wafer, internal defects such as nanopipes and dislocations are suppressed. Therefore, it becomes possible to reduce leaks and improve device characteristics.

  Further, in the method for manufacturing a nitride semiconductor epitaxial wafer according to the present invention, the warpage of the nitride semiconductor during the epitaxial growth is changed from a downwardly convex warp to an upwardly convex warp, or from an upwardly convex warp to below. The convex warpage is changed at least once. Therefore, at the timing at which the warpage of the nitride semiconductor is reversed, minute dislocations that do not easily affect the leak or the like enter, and the strain can be reduced.

  As a result, defects such as nanopipes in the nitride semiconductor can be suppressed, leakage of the manufactured device can be reduced, and device characteristics can be improved.

It is a cross-sectional schematic diagram in the nitride semiconductor for HEMTs using the nitride semiconductor epitaxial wafer of this invention.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

First Embodiment FIG. 1 is a schematic sectional view of a nitride semiconductor for HEMT using the nitride semiconductor epitaxial wafer of the present embodiment.

  In FIG. 1, the nitride semiconductor for HEMT includes an AlN layer 2, an AlGaN buffer layer 5, a superlattice buffer layer 10, an undoped GaN layer 11, and an AlGaN barrier layer 12 in this order on a Si (111) substrate 1. Configured.

Here, the AlGaN buffer layer 5 is composed of the stacked Al _0.50 Ga _0.50 N layer 3 and GaN layer 4. The superlattice buffer layer 10 is composed of an AlN layer 6, an Al _0.05 Ga _0.95 N layer 7, an Al _0.90 Ga _0.10 N layer 8, and an Al _0.10 Ga _0.90 N layer 9 repeatedly. It is configured by stacking.

  Next, a method for producing a nitride semiconductor epitaxial wafer used for producing a nitride semiconductor for HEMT having the above configuration will be described.

  First, the Si (111) substrate 1 having a thickness of 800 μm is treated with diluted hydrofluoric acid to remove the natural oxide film on the surface. Next, the Si substrate 1 is introduced into a reactor of a MOCVD (Metal Organic Chemical Vapor Deposition) apparatus.

In the MOCVD apparatus, after raising the substrate temperature from room temperature to 1100 ° C., H ₂ , N ₂ , NH ₃ (ammonia) and TMA (trimethylaluminum) are supplied to the main surface of the Si substrate 1. The AlN layer 2 is grown to a thickness of 150 nm.

Next, the substrate temperature is changed to 1050 ° C., H ₂ , N ₂ , NH ₃ , TMA and TMG (trimethylgallium) are supplied, and Al _0.50 Ga _0.50 with a layer thickness of 300 nm is formed on the AlN layer 2. N layer 3 is grown. Further, a GaN layer 4 having a layer thickness of 20 nm is grown. Thus, the AlGaN buffer layer 5 in which the Al _0.50 Ga _0.50 N layer 3 and the GaN layer 4 are stacked is formed.

After that, while maintaining the substrate temperature at 1050 ° C., H ₂ , N ₂ , NH ₃ and TMA are supplied to grow the AlN layer 6 having a layer thickness of 3.5 nm. Further, H ₂ , N ₂ , NH ₃ , TMA and TMG are supplied to grow an Al _0.05 Ga _0.95 N layer 7 having a layer thickness of 1.5 nm. Further, H ₂ , N ₂ , NH ₃ , TMA and TMG are supplied to grow an Al _0.90 Ga _0.10 N layer 8 having a layer thickness of 1.5 nm. Further, H ₂ , N ₂ , NH ₃ , TMA and TMG are supplied to grow an Al _0.10 Ga _0.90 N layer 9 having a layer thickness of 23.5 nm. Thereafter, the formation of the AlN layer 6 to the Al _0.10 Ga _0.90 N layer 9 is repeated 60 times to form the superlattice buffer layer 10.

Thereafter, the substrate temperature is changed to 1040 ° C., H ₂ , N ₂ , NH ₃ and TMG are supplied to grow the undoped GaN layer 11 having a layer thickness of 1200 nm. Thereafter, the growth temperature is changed to 1020 ° C., and H ₂ , N ₂ , NH ₃ , TMA and TMG are supplied, and an Al _0.20 Ga _0.80 N AlGaN barrier having a layer thickness of 30.0 nm is supplied. Layer 12 is grown.

  After that, by cooling to room temperature, the AlN layer 2, the AlGaN buffer layer 5, the superlattice buffer layer 10, the undoped GaN layer 11, and the AlGaN barrier layer 12 are stacked on the Si (111) substrate 1 for HEMT. The nitride semiconductor epitaxial wafer is obtained.

  Furthermore, with respect to the nitride semiconductor epitaxy structure laminated on the Si (111) substrate 1 in the nitride semiconductor epitaxial wafer, an electrode, an insulating film, and the like are formed by using a photolithography technique, and finally the substrate A nitride semiconductor for HEMT is formed by grinding, polishing and dicing. Further, the HEMT device is completed through processes such as die bonding and mounting.

  Hereinafter, in the nitride semiconductor epitaxial wafer formed as described above, the crack length from the outer peripheral portion of the nitride semiconductor layer composed of the AlGaN buffer layer 5 to the AlGaN barrier layer 12, and the Si (111) substrate 1 The correlation between the warpage and the defect rate such as leakage in a HEMT device (hereinafter simply referred to as a device) manufactured using the nitride semiconductor epitaxial wafer was examined.

  Although it is difficult to accurately adjust the degree of the “warp” and “crack”, the “crack” was adjusted by changing the film thickness of the AlN layer 2, the cooling rate after epitaxial growth, and the substrate thickness. Further, “warping” was adjusted by changing the film thickness of the AlN layer 2.

(Crack length)
The correlation between the crack lengths from the various peripheral portions of the wafer adjusted as described above and the leakage defect rate is as follows.

  The crack length from the said outer periphery in the sample of the prepared nitride semiconductor epitaxial wafer is as follows.

Sample (A): Less than 3.0 mm Sample (B): 3.0 mm or more and less than 6.0 mm Sample (C): 6.0 mm or more and less than 8.0 mm Sample (D): 8.0 mm or more and Less than 10.0 mm Sample (E): 10.0 mm or more and less than 12.0 mm Sample (F): 12.0 mm or more and less than 14.0 mm Was measured. The measured values of the defect rate related to this leak are as follows. However, the defect rate is a total value of measured values using a good area where cracks in the nitride semiconductor epitaxial wafer do not extend.

Sample (A): 4.6%
Sample (B): 0.6%
Sample (C): 1.6%
Sample (D): 2.3%
Sample (E): 12.8%
Sample (F): 18.5%
As a result, it can be said that a crack length of less than 10 mm from the outer periphery of the nitride semiconductor epitaxial wafer is desirable.

  As a model for the occurrence of leakage, it is considered that in a wafer in which cracks occur in the outer peripheral portion, the internal stress is large even in the central portion of the wafer, and a large number of dislocations and nanopipes that cause leakage are generated. Therefore, the sample (A) having the shortest crack length among the crack lengths of less than 10 mm from the outer periphery is particularly desirable.

  Therefore, when the contents of the sample (A) were investigated, in the region of 100 μm or less from the outer periphery of the nitride semiconductor epitaxial wafer, stress was applied to the inside of the wafer, and defects entered during the process of grinding and polishing the substrate, Unfavorable results such as a decrease in overall yield were obtained. As a result, it is preferable that the nitride semiconductor crack is 100 μm or more and less than 10000 μm from the outer periphery of the nitride semiconductor epitaxial wafer.

(warp)
The correlation between the various substrate warpages adjusted as described above and the leakage defect rate is as follows. The warpage of the Si (111) substrate 1 was adjusted by adjusting the layer thickness of the AlN layer 2.

  The warpage in the prepared nitride semiconductor epitaxial wafer sample is synonymous with BOW (bow), refers to the amount of warpage evaluated at the center of the wafer, and is an intermediate point connecting equidistant points from the front and back surfaces of the wafer It is the amount of displacement of the surface irregularities. Here, when the value of the warp is negative, it is convex (Concave), and when it is positive, it is convex (Convex).

Sample (A): −200 μm or more and less than −150 μm Sample (B): −150 μm or more and less than −100 μm Sample (C): −100 μm or more and less than −50 μm Sample (D): −50 μm or more and 0 μm Less than Sample (E): 0 μm or more and less than 50 μm Sample (F): 50 μm or more and less than 100 μm Sample (G): 100 μm or more and less than 150 μm Sample (H): 150 μm or more and less than 200 μm A device was fabricated using a wafer, and the defect rate related to leakage was measured. The measured value of the defect rate related to this leak is as follows.

Sample (A) 21.8%
Sample (B): 5.6%
Sample (C) 3.1%
Sample (D): 0.8%
Sample (E): 0.4%
Sample (F): 3.4%
Sample (G): 12.1%
Sample (H): 19.5%
As a result, it can be said that the warp of the nitride semiconductor epitaxial wafer is preferably −150 μm or more and less than 100 μm.

  Regarding the warpage of the nitride semiconductor epitaxial wafer, the internal stress increases as the warp value increases, regardless of “convex upward” and “convex downward”. For this reason, it is considered that many dislocations and nanopipes that cause leakage occur.

  Actually, when the cross section of the nitride semiconductor is observed with the STEM (Scanning Transmission Electron Microscopy) for each of the above samples, the wafer with a longer crack length is also in the center of the wafer where the crack has not extended. In addition, many defects and the like are observed in the nitride semiconductor. The same tendency is also observed for nitride semiconductor epitaxial wafers with large warpage.

Second Embodiment The second embodiment relates to a change in warpage during crystal growth in the method for manufacturing a nitride semiconductor epitaxial wafer in the first embodiment.

  In the manufacture of a nitride semiconductor epitaxial wafer, during epitaxial crystal growth, the warpage is changed from the above Concave (convex downward) to the above Convex (convex upward), or from the above Convex (convex upward) to the above Concave (convex downward). As a result, the internal stress changes greatly, and defects such as nanopipes and dislocations having an appropriate size (for example, about several nm to several tens of nm) are introduced into the nitride semiconductor crystal.

  Here, the change of the warp during the crystal growth described above is performed, for example, by changing the degree of difference in crystallinity generated at the center portion and the end portion of the wafer.

  As a result, when the epitaxial wafer is cooled from around 800 ° C. to 1000 ° C. after the crystal growth is completed, the large stress applied to the nitride semiconductor due to the difference in thermal expansion coefficient between the epitaxial growth substrate and the nitride semiconductor is as described above. Because it is moderately relaxed by light nanopipes and dislocations introduced by changes in warpage during crystal growth, the occurrence of defects that affect device characteristics, threading dislocations, and relatively thick nanopipes are suppressed. is there.

Third Embodiment The third embodiment relates to a temperature rise and temperature drop rate during crystal growth in the method for manufacturing a nitride semiconductor epitaxial wafer in the first embodiment.

  In the manufacture of a nitride semiconductor epitaxial wafer, when a nitride semiconductor is crystal-grown or grown on a substrate for epitaxial growth (Si substrate 1), the rate of temperature rise and fall is 5 ° C./min. If it is lower, the defect rate related to leakage of the manufactured device exceeds 15%. Moreover, when it exceeds 80 degreeC / min, since a process takes time, it is not preferable as a manufacturing method.

  Therefore, when the nitride semiconductor is crystal-grown on the epitaxial growth substrate or after the crystal growth, the rate of temperature increase and the rate of temperature decrease is 5 ° C./min or more and 80 ° C./min or less. It is preferable.

  By doing so, a rapid temperature change of the epitaxial growth substrate and the nitride semiconductor is suppressed, and when the temperature rises and falls (especially when the temperature drops after completion of crystal growth), the growth substrate and the nitride semiconductor The rate of change of strain generated from the difference in thermal expansion coefficient can be suppressed. Therefore, the occurrence of defects such as nanopipes that have occurred in the nitride semiconductor under the conventional conditions is suppressed, and the leakage of the manufactured device can be reduced and the device characteristics can be improved.

Fourth Embodiment The fourth embodiment relates to the type of substrate and the configuration of the substrate in the nitride semiconductor epitaxial wafer in the first embodiment.

  When Si, SiC, ZnO, sapphire or the like is used as the epitaxial growth substrate and AlN, GaN or the like is used as the nitride semiconductor, the difference in thermal expansion coefficient between the epitaxial growth substrate and the nitride semiconductor is large. Defects such as cracks occur in the nitride semiconductor portion in the outer peripheral portion of the nitride semiconductor epitaxial wafer.

  Therefore, in this case, by setting the diameter of the epitaxial growth substrate to 3 inches or more and the thickness to 1500 μm or more, as described in the third embodiment, the crystal growth temperature heating rate and It becomes possible to reduce the temperature drop rate. Therefore, the volume change rate is reduced and the occurrence of defects and the like is reduced. As a result, an improvement effect of device characteristics can be obtained as compared with the case where the method of the present invention is not applied.

  Furthermore, as the substrate size is increased or the substrate thickness is increased, the volume change rate due to relaxation of the rate of temperature rise and fall of the crystal growth temperature is further reduced, and the effect that defects can be more effectively suppressed is obtained.

Fifth Embodiment The fifth embodiment relates to the effect of the AlN buffer layer in the nitride semiconductor epitaxial wafer manufacturing method according to the first embodiment.

  In the manufacture of a nitride semiconductor epitaxial wafer, when the growth substrate is Si, the AlN layer 2 is used as a base buffer layer in order to suppress the reaction between Si and GaN, which is a nitride semiconductor. Then, defects of an appropriate size (for example, about several nanometers to several tens of nanometers) such as nanopipes are generated in the AlN layer 2 in contact with the interface with the Si substrate 1.

  Therefore, the reaction between the Si substrate 1 and the nitride semiconductor GaN can be more effectively suppressed by the appropriately sized defects such as the nanopipes, and the device characteristics can be improved.

  In each of the above embodiments, a nitride semiconductor epitaxial wafer for producing a nitride semiconductor for HEMT has been described as an example. However, the present invention is not limited to a nitride semiconductor epitaxial wafer for producing a nitride semiconductor for HEMT.

In summary, the nitride semiconductor epitaxial wafer of the present invention is
An epitaxial growth substrate 1;
Nitride semiconductor layers 3 to 12 epitaxially grown on the epitaxial growth substrate 1, and
When the value of warpage in the substrate for epitaxial growth 1 is a negative warp, it is a convex warp downward, and in the case of a positive notation, it is a convex warp upward, and within a range of −100 μm or more and less than +150 μm. And
The nitride semiconductor layers 3 to 12 are characterized in that the value of the crack length is in the range of 100 μm or more and less than 10000 μm from the outer periphery.

  According to the above configuration, the internal stress in the nitride semiconductor epitaxial wafer is reduced. Therefore, in the nitride semiconductor device using this nitride semiconductor epitaxial wafer, generation of internal defects such as nanopipes and dislocations is suppressed. Therefore, it becomes possible to reduce leaks and improve device characteristics.

In the nitride semiconductor epitaxial wafer of one embodiment,
The epitaxial growth substrate 1 is one of Si, SiC, ZnO and sapphire,
The epitaxial growth substrate 1 has a diameter of 3 inches or more and a substrate thickness of 1500 μm or more.

  When Si, SiC, ZnO or sapphire is used as the epitaxial growth substrate 1, and AlN, GaN or the like is used as the nitride semiconductor layers 3-12, the epitaxial growth substrate 1, the nitride semiconductor layers 3-12, Therefore, defects such as cracks are generated in the nitride semiconductor layers 3 to 12 in the outer peripheral portion of the nitride semiconductor epitaxial wafer due to the volume change.

  According to this embodiment, the epitaxial growth substrate 1 has a diameter of 3 inches or more and a thickness of 1500 μm or more. Therefore, it is possible to relax the rate of temperature rise and fall of the crystal growth temperature, the volume change rate is reduced, and the occurrence of defects such as leaks is reduced. As a result, device characteristics can be improved.

  Furthermore, the larger the substrate size of the epitaxial growth substrate 1 or the thicker the substrate, the lower the volume change rate due to relaxation of the rate of temperature rise and fall of the crystal growth temperature, and the effect of effectively suppressing the generation of defects. can get.

In addition, the method of manufacturing the nitride semiconductor epitaxial wafer of the present invention is as follows:
An epitaxial growth step of epitaxially growing nitride semiconductors 3 to 12 on the epitaxial growth substrate 1,
In the epitaxial growth step, the warpage of the nitride semiconductors 3 to 12 during the epitaxial crystal growth is at least from a downward convex warp to an upward convex warp or from an upward convex warp to a downward convex warp. It is characterized by being changed once or more.

  According to the above configuration, during the epitaxial growth, at the timing when the warpage of the nitride semiconductors 3 to 12 is reversed, minute dislocations that do not affect the leakage and the like enter, and the strain can be reduced. As a result, defects such as nanopipes inside the nitride semiconductor can be suppressed, leakage of the manufactured device can be reduced, and device characteristics can be improved.

Further, in the method of manufacturing a nitride semiconductor epitaxial wafer of one embodiment,
The temperature increase rate of the epitaxial crystal growth temperature in the epitaxial growth step or the temperature decrease rate of the epitaxial crystal growth temperature after the epitaxial growth is set to 5 ° C./min to 80 ° C./min.

  According to this embodiment, the rapid temperature change during the epitaxial crystal growth is suppressed, and the substrate for epitaxial growth 1 and the nitride semiconductors 3 to 3 are heated at the time of temperature rise and temperature drop, particularly at the time of temperature drop after completion of crystal growth. The rate of change in strain generated from the difference in thermal expansion coefficient from 12 can be suppressed. Therefore, under the conventional conditions, defects such as nanopipes that have occurred inside the nitride semiconductor can be suppressed, leakage of the manufactured device can be reduced, and device characteristics can be improved.

Further, in the method of manufacturing a nitride semiconductor epitaxial wafer of one embodiment,
The epitaxial growth step is
Epitaxially growing an AlN underlayer 2 on the epitaxial growth substrate 1;
And epitaxially growing the nitride semiconductors 3 to 12 on the AlN underlayer 2.

  According to this embodiment, when the epitaxial growth substrate 1 is Si, AlN is used as the base buffer layer in order to suppress the reaction between Si and GaN. In that case, defects of an appropriate size such as nanopipes are generated in the AlN layer 2 in contact with the interface with Si. Therefore, the reaction between the Si substrate 1 and the nitride semiconductors 3 to 12 GaN can be more effectively suppressed by defects of an appropriate size such as the nanopipe, thereby improving device characteristics. it can.

1 Si (111) substrate 2 AlN layer 3 Al _0.50 Ga _0.50 N layer 4 GaN layer 5 AlGaN buffer layer 6 AlN layer 7 Al _0.05 Ga _0.95 N layer 8 Al _0.90 Ga _0.10 N layer 9 Al _0.10 Ga _0.90 N layer 10 Superlattice buffer layer 11 Undoped GaN layer 12 AlGaN barrier layer

Claims (4)

An epitaxial growth substrate;
On the substrate for epitaxial growth, an AlN underlayer epitaxially grown and a nitride semiconductor layer epitaxially grown on the AlN underlayer ,
When the value of warpage in the substrate for epitaxial growth is a negative warp when it is negative, and when it is a convex warp when it is positive, it is within a range of −100 μm or more and less than +150 μm. And
A nitride semiconductor epitaxial wafer, wherein a value of a crack length in the nitride semiconductor layer is within a range of 3 mm or more and less than 10 mm from the outer periphery. The nitride semiconductor epitaxial wafer according to claim 1,
The epitaxial growth substrate is one of Si, SiC, ZnO and sapphire,
A nitride semiconductor epitaxial wafer, wherein the epitaxial growth substrate has a diameter of 3 inches or more and a thickness of 1500 μm or more. An epitaxial growth step of epitaxially growing a nitride semiconductor layer on the epitaxial growth substrate;
In the epitaxial growth step, the nitride semiconductor layer is warped at least once during the epitaxial crystal growth, from a downwardly convex warp to an upwardly convex warp, or from an upwardly convex warp to a downwardly convex warp. varied more,
The epitaxial growth step includes a step of epitaxially growing an AlN underlayer on the epitaxial growth substrate, and a step of epitaxially growing the nitride semiconductor layer on the AlN underlayer,
The nitride semiconductor epitaxial wafer, wherein the thickness of the AlN underlayer is adjusted so that the value of the crack length in the nitride semiconductor layer is within a range of 3 mm or more and less than 10 mm from the outer periphery. Manufacturing method. In the manufacturing method of the nitride semiconductor epitaxial wafer according to claim 3,
Nitride semiconductor epitaxial, characterized in that the rate of temperature increase of the epitaxial crystal growth temperature in the epitaxial growth step or the rate of temperature decrease of the epitaxial crystal growth temperature after the epitaxial growth is not less than 5 ° C./min and not more than 80 ° C./min Wafer manufacturing method.

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