JP6320464B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine that generates a big hit state by a lottery process caused by a gaming operation, and more particularly to a gaming machine capable of powerful moving effects.

  A ball game machine such as a pachinko machine has a symbol start opening provided on the game board, a symbol display section for displaying a series of symbol variation patterns by a plurality of display symbols, and a big winning opening for opening and closing the opening and closing plate. Configured. When the detection switch provided at the symbol start port detects the passage of the game ball, the winning state is entered, and after the game ball is paid out as a prize ball, the display symbol is changed for a predetermined time in the symbol display section. Thereafter, when the symbol is stopped in a predetermined manner such as 7, 7, 7, etc., a big hit state is established, and the big winning opening is repeatedly opened to generate a gaming state advantageous to the player.

  Whether or not to generate such a game state is determined by a jackpot lottery executed on the condition that a game ball has won at the symbol start opening, and the above symbol variation operation is based on this lottery result. It has become a thing. For example, when the lottery result is in a winning state, an effect operation called reach action or the like is executed for about 20 seconds, and then the special symbols are aligned. On the other hand, a similar reach action may be executed even in the case of a lost state. In this case, the player pays close attention to the big hit state and pays close attention to the transition of the performance operation. When the predetermined symbols are aligned on the stop line at the end of the symbol variation operation, the player is guaranteed to be in the big hit state.

JP-A-2015-198716 JP-A-2015-198715 Japanese Patent Laying-Open No. 2015-205117

  In connection with the above reach action, there may be a case where a movable effect for operating one or a plurality of movable accessories is executed. Here, in order to realize a powerful movable effect, the momentum of the movable accessory increases, and in order to smoothly move the large movable accessory, corresponding driving power is required. When the transmission distance of the driving voltage of the motor that drives the movable accessory is long, useless power loss increases accordingly, and thus a high voltage power supply device configuration that takes this point into consideration is desired (Patent Document 1). To 3).

However, in a simple high-voltage power supply configuration, overcurrent at power-on cannot be avoided even if a blown fuse is provided. In other words, the fusing fuse operates based on the integrated value (I ² rt) of the generated Joule heat, so it does not react to the inrush current generated at the time of power-on, and as a result, the power line This specific part (the part where the contact resistance exists) is repeatedly worn. Further, the problem of power supply noise radiated from the high-voltage power supply line at the time of a movable performance by a plurality of movable objects is not solved. In addition, if the game board (board side member) updated for each model is connected to the frame side member placed in the game hall for a long time with a one-touch connector, it should remain in the power-on state. A device configuration that does not cause a power supply trouble even when hot-plugging is accidentally performed is required.

  The present invention has been made in view of the above problems, and it is an object of the present invention to provide a gaming machine capable of driving a large movable accessory without causing power supply trouble and realizing a powerful movable effect. And

  In order to solve the above-described problems, the present invention is a gaming machine that can execute a lottery process based on a predetermined switch signal and execute a game operation according to the lottery result, and executes the lottery process. Main control means for centrally controlling game operations, effect control means for executing effect operations based on instructions from the main control means, and various levels for causing the main control means and the effect control means to function Power generation means for generating a direct current voltage, and the rendering operation includes a movable rendering executed by a rendering motor, and the main control means is a first level DC voltage fed from the power supply means. While the level is supplied to the predetermined inductance member, the effect control means receives the first level DC voltage fed from the power supply means by the capacitance member, and then the level. The first level DC voltage generated by the power supply means is supplied to the main control means without interposing a temperature-dependent current limiting member. The production control means is configured to be supplied with power through a predetermined current limiting member having temperature dependency.

  The present invention employs a high-voltage power supply system that drops the first level DC voltage and supplies it to the effect motor, and therefore can effectively suppress power loss in the power supply line. Further, since the first level DC voltage is received by the capacitance member, the power supply ripple at the time of driving the effect motor can be suppressed, and the problem of power supply noise is solved. Moreover, since the first level DC voltage fed with high voltage is fed via a temperature-dependent current limiting member, an excessive current does not flow even when the capacitance member is rapidly charged, such as when the power is turned on, It is effective for noise countermeasures and device protection.

  The first-level DC voltage preferably has a notarized value of 30 V or more, and is supplied to a drive power supply board on which a step-down circuit is mounted together with the capacitance member via one or a plurality of circuit boards. The direct-current voltage is supplied to the step-down circuit in a state where the direct-current voltage is smoothed by the capacitance member, and the level is lowered. Also, the direct current voltage of the first level is supplied to the effect control means via a one-touch connector in which a plurality of contacts are connected in one mounting operation and a plurality of contacts are separated in one separating operation. It is suitable that it is comprised.

  The inductance member is preferably driven by a driver IC that exhibits an overheat protection function without requiring a power supply voltage, and the predetermined current limiting member has a resistance value at 25 ° C. of a notarized value of 1Ω to It is preferable that the thermistor is composed of a 3Ω thermistor and / or the heat dissipation constant δ is 14 mW / ° C. to 27 mW / ° C. In any case, the capacitance of the capacitance member is preferably 20 μF or more.

  In addition, the power supply means outputs a DC voltage of a second level lower than the first level and a DC voltage having a notarized value of 5 V lower than the second level together with the main control means and the effect control together with the DC voltage of the first level. Preferably, the power is supplied to the means, and the second level DC voltage is preferably used as the driving voltage of the lamp and / or the driving voltage of the sensor for detecting the predetermined switch signal. .

  The step-down circuit is preferably configured so that its output voltage can be changed. In this case, the step-down circuit preferably has a switch circuit (Q2) that operates on / off in response to a voltage control signal, and a first resistor (R1) disposed between the output terminal of the step-down circuit and the switch circuit. ), The second resistor (R2), the emitter terminal is connected to the output terminal of the step-down circuit, the base terminal is connected to the connection point of the first resistor (R1) and the second resistor (R2), and the collector terminal is connected And a control transistor (Q1) to which the third resistor is connected. When the switch circuit (Q2) is turned on, the saturation current of the control transistor flows through the third resistor, while the switch circuit (Q2) During the OFF operation, the leakage current of the switch circuit (Q2) flows through the first resistor (R1) and the second resistor (R2), thereby preventing the energization operation of the control transistor (Q1).

  The third resistance is preferably 200 kΩ or more, and the saturation current is preferably 50 μA or less. The leakage current is preferably 10 μA or less. Although not specifically described in the embodiment, all the configurations of the embodiment satisfy this condition.

  As described above, according to the present invention, a large movable accessory can be driven without causing a power supply trouble, and a powerful movable effect can be realized.

It is a perspective view which shows the pachinko machine of a present Example. It is a schematic front view of the game board of a present Example. It is a block diagram which shows the whole circuit structure of a present Example. It is drawing explaining the power line of DC35V used as a drive power supply of a solenoid or an effect motor. It is drawing explaining the circuit structure and circuit operation | movement of a power supply board. It is a block diagram showing a circuit configuration of an effect control unit. It is drawing explaining the circuit structure of a drive power supply board | substrate. It is drawing explaining the deformation | transformation structure of a drive power supply board | substrate. It is drawing which shows the experimental result regarding 3rd electric power feeding line CB3.

  Hereinafter, the present invention will be described in detail based on examples. FIG. 1 is a perspective view showing a pachinko machine GM of the present embodiment. This pachinko machine GM includes a rectangular frame-shaped wooden outer frame 1 that is detachably mounted on an island structure, and a front frame 3 that is pivotably mounted via a hinge 2 fixed to the outer frame 1. It is configured.

  A game board 5 is detachably attached to the front frame 3 from the front side using a one-touch connector rather than from the back side, and a glass door 6 and a front plate 7 are pivoted on the front side so as to be openable and closable. It is worn. Here, the one-touch connector means connection connectors C1 to C4 (see FIG. 3) in which a plurality of contacts are connected in one mounting operation and a plurality of contacts are disconnected in one separation operation.

  On the outer periphery of the glass door 6, an electric lamp such as an LED lamp is arranged in a substantially C shape. On the other hand, a speaker is disposed below the glass door 6.

  The front plate 7 is provided with an upper plate 8 for storing game balls for launching, and a lower plate 9 for storing game balls overflowing or extracted from the upper plate 8 and a launch handle at the lower part of the front frame 3. 10 are provided. The launch handle 10 is interlocked with the launch motor, and a game ball is launched by a striking rod that operates according to the rotation angle of the launch handle 10.

  A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated with the left hand of the player, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp is turned on and can be operated. The button chance state is a game state provided as necessary.

  On the right side of the upper plate 8, an operation panel 12 for ball lending operation with respect to the card-type ball lending machine is provided, a frequency display unit for displaying the remaining amount of the card with a three-digit number, and a ball of game balls for a predetermined amount A ball lending switch for instructing lending and a return switch for instructing to return the card at the end of the game are provided.

  As shown in FIG. 2, a guide rail 13 made of a metal outer rail and an inner rail is provided in an annular shape on the surface of the game board 5, and a central opening HO extending toward the back side is provided in the approximate center. It has been. A display device DS composed of a liquid crystal color display is disposed at the bottom of the central opening HO.

  In addition, in the space formed in the front surface of the display device DS, a production movable body AMU (movable accessory) is disposed so as to be movable up and down. The effect movable body AMU includes a fixed member FIX that is held up and down by being held by the lifting mechanism ALV, and a rotating member ROT that is supported and rotated by the fixed member FIX.

  The raising / lowering operation of the raising / lowering mechanism ALV and the rotating operation of the rotating member ROT are realized by the rotation of the effect motors M1 to Mn formed of stepping motors. In the normal state, the effect movable body AMU stands by in a state of being lifted by the lifting mechanism ALV.

  At appropriate positions in the game area, a symbol starting port 15, a big winning port 16, a normal winning port 17, and a gate 18 are arranged. Each of these winning openings 15 to 18 has a detection switch inside, and can detect the passage of a game ball.

  The display device DS is a device that variably displays a specific symbol related to the big hit state and displays a background image and various characters in an animated manner. This display device DS has a special symbol display part Da to Dc in the central part and a normal symbol display part 19 in the upper right part. And, in the special symbol display parts Da to Dc, a reach effect is executed that expects a big hit state to be invited, or in the special symbol display parts Da to Dc and the surroundings, a notice effect that informs the result of the success / failure is executed. Is done.

  The normal symbol display unit 19 displays a normal symbol. When a game ball that has passed through the gate 18 is detected, the normal symbol fluctuates for a predetermined time, and the lottery extracted at the time when the game ball passes through the gate 18 is extracted. The stop symbol determined by the random number for use is displayed and stopped.

  The symbol start opening 15 is configured to be opened and closed by an electric tulip having a pair of left and right opening and closing claws. When the stop symbol after the fluctuation of the normal symbol display unit 19 hits and the symbol is displayed, the opening and closing claw is predetermined. It is released only for a time or until a predetermined number of game balls are detected.

  The electric tulip is opened when the second solenoid SLb is energized at the timing when the control signal CTLb becomes L level (see FIG. 5). Unlike the configuration of FIG. 2, when the normal winning opening 17 is configured to be openable and closable, the normal winning opening is opened and closed by the third solenoid SLc that is energized and controlled by the control signal CTLc.

  When a game ball wins the symbol start port 15, the display symbols of the special symbol display portions Da to Dc change for a predetermined time and are determined based on the lottery result corresponding to the winning timing of the game ball to the symbol start port 15. Stop at the stop symbol. In addition, in special symbol display parts Da-Dc and its circumference, a notice effect may be performed between a series of symbol effects. In addition, as a kind of notice effect, the effect movable body AMU may descend to the position of the central opening HO. Then, the lowered effect movable body AMU is rotated clockwise or counterclockwise and then raised to the original position.

  The big winning opening 16 is controlled to open and close by, for example, an opening / closing plate 16a that can be opened forward. Is started, and the opening / closing plate 16a is opened. The opening / closing plate 16a is opened when the first solenoid SLa is energized at the timing when the control signal CTLa becomes L level (see FIG. 5).

  After the opening / closing plate 16a of the big prize opening 16 is opened, the opening / closing plate 16a is closed when a predetermined time elapses or when a predetermined number (for example, 10) of game balls wins. In such an operation, the special game is continued up to 15 times, for example, and is controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display parts Da to Dc is a specific symbol of the special symbols, a privilege that the game after the end of the special game is in a high probability state is given.

  FIG. 3 is a block diagram showing an overall circuit configuration of the pachinko machine GM that realizes the above-described operations. As shown in the figure, this pachinko machine GM receives AC24V and outputs various DC voltages and power supply abnormality signals ABN1 and ABN2, a main control board 21 mainly responsible for game control operations, and a main control. An effect control board 22 that executes a lamp effect and a sound effect based on a control command CMD received from the board 21; an image control board 23 that drives the display device DS based on a control command CMD ′ received from the effect control board 22; , A payout control board 24 for controlling the payout motor M based on the control command CMD "received from the main control board 21 and paying out the game ball, and a launch control board 25 for firing the game ball in response to the player's operation. And it is composed around.

  The control command CMD output from the main control board 21 is first transmitted to the effect control board 22, and the control command CMD ′ output from the effect control board 22 passes through the image interface board 28 to the image control board 23. Is transmitted. The control command CMD ″ output from the main control board 21 is transmitted to the payout control board 24 via the main board relay board 32.

  The control commands CMD, CMD ′, and CMD ”are all 16 bits long, but the control commands related to the main control board 21 and the payout control board 24 are transmitted in parallel every two 8 bits. On the other hand, the control command CMD ′ transmitted from the effect control board 22 to the image control board 23 is transmitted in parallel with a 16-bit length. Even when such control commands are continuously transmitted and received, the processing can be completed quickly, and other control operations are not hindered.

  In the present embodiment, the image interface board 28 and the image control board 23 are formed by stacking two circuit boards by directly connecting a male connector and a female connector without going through a wiring cable. Therefore, even if the circuit configuration of each electronic circuit is complicated and sophisticated, the storage space of the entire board can be minimized, and noise resistance can be improved by minimizing the connection lines.

  The main control board 21, the effect control board 22, the image control board 23, and the payout control board 24 are each equipped with a computer circuit including a one-chip microcomputer. In view of this, the control boards 21 to 24 and the circuits mounted on the interface board 28 and the operations realized by the circuits are collectively referred to as functions. In this specification, the main control section 21 and the effect control section 22 are used. , Image control unit 23 and payout control unit 24. That is, in this embodiment, the image control board 23 and the image interface board 28 constitute the image control unit 23. All or part of the effect control unit 22, the image control unit 23, and the payout control unit 24 is a sub-control unit.

  The pachinko machine GM is roughly divided into a frame side member GM1 surrounded by a broken line in FIG. 3 and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes a front frame 3 on which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof. Is fixedly installed. On the other hand, the board side member GM2 is replaced in response to the model change, and a new board side member GM2 is attached to the frame side member GM1 instead of the original board side member. All except the frame side member GM1 is the panel side member GM2.

  As shown in the broken line frame in FIG. 3, the frame side member GM1 includes a power supply board 20, a payout control board 24, a launch control board 25, a frame relay board 35, and a lamp drive board 36. These circuit boards are respectively fixed at appropriate positions of the front frame 3.

  A plurality of LEDs are connected to the lamp drive board 36, and drive data SDATA for driving these LED groups is transmitted via the effect control board 22 → the frame relay board 34 → the frame relay board 35 as a serial signal. Are transmitted to a plurality of LED drivers mounted on the lamp driving board 36.

  On the back surface of the game board 5, a main control board 21, an effect control board 22, an image control board 23, and an image interface board 28 are fixed together with the display device DS and other circuit boards. And the frame side member GM1 and the board | substrate side member GM2 are electrically connected by the connection connectors C1-C4 concentratedly arranged in one place. Each of the connection connectors C1 to C4 has a plurality of contacts, but the contacts of the whole C1 to C4 are connected to each other by one mounting operation and are separated from each other by one separation operation.

  The power supply board 20 is connected to the main board relay board 32 through the connection connector C2, and is connected to the power supply relay board 33 through the connection connector C3. The internal configuration of the power supply substrate 20 is as shown in FIG. 4A. The power supply board 20 has a bridge type rectifier circuit 61 for full-wave rectifying AC24V received from the outside, and a power factor for receiving DC35V output from the rectifier circuit 61. Improvement circuit 62, inrush current prevention circuit 63 for suppressing the transient current of the rectifier circuit, four DC-DC converters (hereinafter abbreviated as converters) RG1 to RG4 and their associated circuits, AC power supply cutoff and DC output And an AC monitoring circuit 64 that monitors voltage anomalies.

  DC35V output from the power factor correction circuit 62 is distributed to the main control board 21, the payout control board 24, and the effect control board 22 through the power supply lines CB1 to CB3. Therefore, before describing the internal configuration of the power supply substrate 20, first, the configuration of the power supply lines CB1 to CB3 will be described in detail.

  As shown in FIG. 4A, the DC voltage DC35V that passes through the fusing fuse FU1 is fed to the main control board 21 and the payout control board 24 via the first feeding line CB1 and the second feeding line CB2. On the other hand, the direct current voltage DC35V that passes through the thermistor TH2 and the fusing fuse FU2 is supplied to the effect control board 22 through the third power supply line CB3.

  The feed lines CB1 and CB2 directly feed the DC voltage DC35V, whereas the feed line CB3 feeds the DC voltage DC35V through the thermistor TH2 in this embodiment. This is because CB2 is terminated with an inductive load, whereas feed line CB3 is terminated with a capacitive load.

  FIG. 5A illustrates whether the power supply lines CB1 to CB3 are terminated with an inductive load or a capacitive load. As shown in the figure, the DC voltage DC35V of the first power supply line CB1 passes through the connection connector C2 and then reaches the game board relay board 31 via the internal wiring of the main control board 21, and the open / close plate 16a of the big prize opening 16 And one end of electromagnetic solenoids SLa to SLc for opening and closing an electric tulip or the like of the symbol start opening 15. In the case of this embodiment, the other ends of the electromagnetic solenoids SLa to SLc receive control signals CTLa to CTLc via the power switch PS that does not require a power supply voltage.

  As shown in FIG. 5B, the power switch PS of the embodiment is composed of three terminals, that is, an input terminal IN, an output terminal OUT, and a ground terminal GND, and N between the output terminal OUT and the ground terminal GND. A transistor Qn, which is a channel MOSFET, is arranged. The transistor Qn of this power switch PS performs ON / OFF operation with the input terminal voltage = 1.5V as a threshold voltage, but overheat protection, overcurrent protection, overvoltage protection, output current control, output cutoff, and electrostatic protection It is composed of a single element with a built-in internal circuit that performs such functions.

  Specifically, the drain-source voltage of the transistor Qn is clamped at about 60V (overvoltage protection), the output operation is stopped when the element temperature is about 150 ° C. (overheat protection), and the input voltage exceeding 10V is clamped. (Electrostatic protection), the protection circuit is configured to function when the drain current exceeds about 6A. Note that the internal resistance between the output terminal and the ground during the ON operation of the transistor Qn is about 0.3Ω, and the shunt resistor for current detection is not connected to the transistor Qn. Further, the drain-source leakage current during the OFF operation is about 5 to 10 μA.

  The power switch PS functions as a current driver that supplies a driving current of about 1 A to the electromagnetic solenoid when the transistor Qn is turned on. However, unlike a normal driver having an equivalent protection function, the power switch PS does not require a power supply voltage. Has major features. If a power transistor is arranged instead of the power switch PS, various protection functions cannot be exhibited.

  FIG. 5C shows an output portion of the driver IC virtually connected to the transistor Qn of FIG. As shown in FIG. 5C, a normal driver IC has an output section having a C-MOS configuration, and a power supply voltage Vcc (for example, 35 V) and a smoothing capacitor Cs are essential. Therefore, in the case of such a driver IC, when the solenoid SLi is not energized, such as when the power is turned on, the P-channel transistor Qp is turned on and the smoothing capacitor Cs is substantially connected to the power supply line CB1. As a result, the power supply line CB1 is terminated with a capacitive load + inductive load.

  On the other hand, in this embodiment, since the electromagnetic solenoid SLi is driven using the power switch PS shown in FIG. 5B in which no power supply voltage exists, the solenoid is not energized, such as when the power is turned on. Of course, even when the solenoid SLi is energized during a game operation, the power supply line CB1 does not become a capacitive load. That is, it is self-evident that the power supply line CB1 becomes an inductive load when the solenoid SLi that turns on the transistor Qn is energized. Since the stray capacitance functions, the power supply line CB1 becomes an inductive load.

  The above points are the same for the second power supply line CB2 as well as the first power supply line CB1. That is, the DC voltage DC35V of the second power supply line CB2 is supplied to one end of the firing solenoid SLe via the internal wiring of the payout board 24 and the firing control board 25, and the other end of the firing solenoid SLe is The control signal CTLe is received via the power switch PS shown in FIG.

  As described above, since the power supply lines CB1 and CB2 are both terminated with an inductive load, there is no possibility that an excessive rush current flows even at the timing when the power supply line is first activated, such as when the power is turned on. There is no risk of power supply trouble such as fusing of the fuse FU1.

  On the other hand, when the normal driver shown in FIG. 5C is used, when the solenoid SLi is in a non-energized state, the power supply line CB1 is a capacitive load + inductive load. Excessive rush current (LC vibration current) flows, which may cause power supply trouble such as fusing of the fuse FU1.

  As described above, the effect of the present embodiment in which the power supply lines CB1 and CB2 are terminated by the power switch PS illustrated in FIG. 5B has been described. However, the third power supply line CB3 cannot have the same configuration.

  That is, as shown in FIG. 5A, the DC voltage DC35V of the third power supply line CB3 passes through the connection connector C3, and then passes through the production control board 22 and the internal wiring of the lamp / motor drive board 30 to drive power. Power is distributed to the substrate 26. A DC-DC converter CN is arranged on the drive power supply board 26, and the smoothing capacitor Cin is arranged on the input side of the DC-DC converter CN, so that the third power feed line CB3 becomes a capacitive load.

  Here, the smoothing capacitor Cin reduces the power consumption at the time of the moving effect so that the input voltage of the DC-DC converter CN does not fluctuate in the dark at the time of the moving effect by the movable accessory and the power supply line noise is not generated from the power supply line CB3. Based on this, the optimum value is set. The power consumption at the time of the movable performance is largely related to the load of the movable accessory, etc., but the smoothing capacitor Cin needs to be at least 20 μF or more, and is optimally set in the range of 20 μF to 800 μF.

  As will be described later with reference to FIG. 7, the DC-DC converter CN is a step-down converter that receives DC 35V and outputs DC 15V or 18V, and the output voltage is the driving voltage Vm of the effect motors M1 to Mn. In the present embodiment, although the drive voltage Vm of the effect motors M1 to Mn is about 15V or 18V, the connection connector C3 → the effect control board 22 → the lamp is intentionally adopted by adopting a high voltage power supply system that distributes DC 35V. / Power loss in the energization path from the motor drive board 30 to the drive power supply board 26 is effectively reduced.

For example, when comparing the configuration of the embodiment that distributes DC 35V up to the drive power supply substrate 26 with the configuration that distributes DC 15V, assuming that the supply power from the power supply substrate 20 is the same in both configurations, In the configuration of the present embodiment in which high-voltage power feeding is performed, the feeding current I is 15/35 = 3/7, so that the power loss in the line loss resistance r is suppressed to 9/49 times (r × I ² ). .

  In the present embodiment using the one-touch connectors CN1 to CN4, particularly, there is a concern about an increase in contact resistance due to deterioration of the connection connector C3 due to age, but the above-described configuration of the high-voltage power supply is very effective.

  As described above, in this embodiment, a high-voltage power supply method is adopted to suppress power loss. However, simply supplying high-voltage power causes a problem when the power is turned on. In other words, the power supply line CB3 is a capacitive load of about 20 μF to 800 μF, but when the power is turned on, the impedance of the capacitor Cin starts from a substantially zero state and is rapidly charged from 0 V to 35 V. The fuse FU2 may be blown by the rush current. In the unlikely event that the panel side member GM2 is attached to the frame side member GM1 with the power turned on, the contact portion of the one touch connector CN3 may be melted.

  Therefore, in the present embodiment, in consideration of the above problem, the thermistor TH2 is arranged on the most upstream side only in the third power feed line CB3 that is a capacitive load. Here, as the thermistor TH2, an element having a resistance value at 25 ° C. of notarized value 1Ω to 3Ω, a resistance value at 100 ° C. of about 0.2Ω, and a resistance value of 170 ° C. of about 0.1Ω is selected.

  The thermistor TH2 has a heat dissipation constant δ of 14 mW / ° C. to 27 mW / ° C. The heat dissipation constant δ means electric power (mW / ° C.) required for the thermistor itself to rise 1 ° C. temperature by self-heating due to energization in a still air atmosphere.

  In the present embodiment, the thermistor TH2 having the above-described characteristics is disposed in the third feed line CB3. For example, the resistance value of the thermistor TH2 that was about 2Ω when the power is turned on is rapidly increased by self-heating due to energization thereafter. The thermistor TH2 that exhibits a transient current limiting function can reliably avoid power supply troubles when the power is turned on.

  FIG. 9 shows the experimental results for this example. By arranging the thermistor TH2 having a resistance value of 2Ω at 25 ° C. in the third power feed line CB3, the peak value of the rush current is suppressed to about 14.5 A, In addition, after the charging time of 2.24 mS, the input capacitor Cin is charged to about 80% of the final value of 35V.

  As described above, the first power supply line CB1, the second power supply line CB2, and the third power supply line CB3 have been described in detail with reference to FIG. 5, and the internal configuration of the power supply substrate 21 will be further described with reference to FIG. .

  As shown in FIG. 4A, the power factor correction circuit 62 is a boost type power factor control circuit that realizes a chopper operation by controlling ON / OFF of the choke coil L1, the switching transistors Q1 and Q2, and the two transistors. It has a PFC and a smoothing capacitor C1, boosts the peak value of input voltage 33.9V (= 24 * SQR2), and outputs a DC voltage of design value DC35V.

  As described above, the DC voltage DC35V is distributed to the main control board 21, the payout control board 24, and the effect control board 22 through the first to third power supply lines CB1 to CB3.

  The power factor control circuit PFC performs ON / OFF control of the transistors Q1 and Q2 in a complementary manner, thereby causing a low-amplitude sawtooth wave charging / discharging current to flow through the AC24V power line (see FIG. 4D). That is, when the transistor Q1 is ON (Q2 is OFF), the energy stored in the choke coil L1 is charged to the smoothing capacitor C1 when the transistor Q2 is ON (Q1 is OFF). The input current is improved to a substantially sinusoidal shape.

  Therefore, according to the present embodiment, the spike-like input current as shown in FIG. 4C does not flow, the maximum current rating of the diodes D1 to D4 constituting the rectifier circuit 61 can be suppressed, It is not necessary to use large-capacity diodes D1 to D4 (relatively expensive). 4 (b) and 4 (c) show the current waveform of the voltage across the smoothing capacitor C1 and the input current of the AC 24V power line for a conventional device (comparative example) that does not have a power factor correction circuit. It is shown that a spike-like large current flows when charging the smoothing capacitor C1. On the other hand, in the present embodiment, since a spike current as shown in FIG. 4C does not flow, no power supply noise is generated, which is also preferable in this sense.

  The inrush current prevention circuit 63 includes an N-channel MOS type switching transistor Q3, a thermistor TH1 disposed between the drain terminal and the source terminal of the transistor Q3, and a bias element (ZD1, R1, R2) that defines the gate voltage of the transistor Q3. , C2). As shown in the figure, since the bias element includes the Zener diode ZD1, a bias voltage is not applied to the gate terminal and the transistor Q3 is turned off in a transient state until the Zener diode ZD1 breaks down and turns ON. .

  Therefore, immediately after the power is turned on, the input current of the AC 24V power line passes through the path of the rectifier circuit 61 → the power factor improving circuit 62 → the thermistor TH1 → the rectifier circuit 61, and a transient current (rush current) when the power is turned on. Is optimally limited by the thermistor TH1. Therefore, in this embodiment, there is an advantage that it is not necessary to use large-capacity and expensive diodes D1 to D4 in this sense. When the output value of the power factor control circuit PFC approaches the steady value (DC35V), the Zener diode ZD1 is turned on and the transistor Q3 is also turned on. Thereafter, no current flows through the thermistor TH1. In addition, useless power consumption does not continue in the thermistor TH1.

  The AC monitoring circuit 64 includes a full-wave rectifier circuit including diodes D5 and D6 and a load resistor R3, a current limiting resistor R4, and a converter RG4. The voltage across the load resistor R3 has a pulsating waveform with a peak value of about 34V (see FIG. 4E), and this pulsating voltage is supplied to the monitoring terminal Sin1 of the converter RG4 via the current limiting resistor R4. Yes. Converter RG4 determines the interruption of AC power supply AC24V based on the voltage supplied to monitoring terminal Sin1, and details thereof will be described later.

  The four converters RG1 to RG4 all receive the DC voltage (DC35V) of the same level and operate with the DC input terminal Vin, and function together with the passive elements (R, L, C) (not shown). DC voltage (12V or 5V) is output. That is, converter RG1 and converter RG2 each generate 12V and output it to output terminal Vout. Output voltage DC12V of converter RG1 is distributed to effect control board 22, and output voltage DC12V of converter RG2 is the main voltage. Power is distributed to the control board 21 and the payout control board 24.

  Further, converter RG3 generates DC5V distributed to effect control board 22 and outputs it from output terminal Vout of converter RG3, and converter RG4 generates DC5V distributed to main control board 21 and payout control board 24. Output from the output terminal Vout of the converter RG4. Thus, in the power supply board 20 of the present embodiment, only three types of DC voltages (35V, 12V, 5V) are generated, and the control boards 20, 21, 22 that receive the distribution of these DC voltages are necessary. Accordingly, a configuration in which one or a plurality of power supply voltages at a drop level is generated is adopted, and the configuration of the power supply circuit as a whole gaming machine is not wasted.

  A backup power supply BAK of DC5V is generated based on the output of the converter RG4 and is distributed to the main control board 21 and the payout control board 24. Here, the backup power source BAK is a DC power source of DC 5V that retains data in the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 24 even after the AC power source 24V is shut off due to business termination or power failure. is there.

  Incidentally, the converter RG1 and the converter RG3 are provided with a control terminal CTL for controlling whether or not the DC-DC conversion operation of each circuit element is permitted, and the internal circuit functions on condition that the control terminal CTL is at the H level. Then, the DC-DC conversion operation is executed.

  In this embodiment, converter RG2 and converter RG4 use the same circuit element (IC) whose internal configuration is shown in FIG. This circuit element includes a DC input terminal Vin to the built-in DC conversion circuit CNV, a control terminal CTL that controls whether the operation of the DC conversion circuit CNV is permitted, an input terminal Sin2 to the comparator CM2, and a detection terminal that receives an abnormal signal. REF, monitoring terminal Sin1 internally connected to a Zener diode for 5.1V, etc., output terminal Sout2 of comparator CM2, output terminal Sout1 of comparator CM1, and output terminal Vout of DC conversion circuit CNV Configured. For these converters RG2 and RG4, the internal circuit (DC conversion circuit CNV) functions and the DC-DC conversion operation is executed on condition that the control terminal CTL is at the H level.

  As shown in FIG. 4F, the comparator RG2 and the comparator CM2 incorporated in the converter RG4 compare the input voltage to the input terminal Sin2 with the comparison reference voltage 2.5V, and the comparison result of the H / L level. Is output. Specifically, when the voltage at the input terminal Sin2 is higher than the comparison reference voltage 2.5V, an H level comparison result is output to the output terminal Sout2, but the voltage at the input terminal Sin2 is equal to the comparison reference voltage 2. It is configured to output an L level comparison result when the voltage is lower than 0.5V.

  As abbreviated in FIG. 4A, a divided signal DV obtained by appropriately dividing the DC voltage DC35V is supplied to the input terminals Sin2 of the converter RG2 and the converter RG4. The divided voltage signal DV is higher than the comparison reference voltage 2.5V when the DC voltage DC35V is at a normal level, but falls below the comparison reference voltage 2.5V when the DC voltage DC35V drops to a predetermined level. It is set as follows. Therefore, when DC voltage DC35V falls to a predetermined level, converter RG2 and output terminal Sout2 of converter RG4 transition to the L level.

  As shown in FIG. 4A, the output terminal Sout2 of the converter RG2 is connected to the control terminal CTL of the converter RG1 together with its own control terminal CTL. Similarly, the output terminal Sout2 of the converter RG4 is connected to the control terminal CTL of the converter RG3 together with its own control terminal CTL.

  Therefore, when the DC voltage DC35V drops and the output voltage of the output terminal Sout2 of the converter RG2 or the converter RG4 transitions to the L level, the four converters RG1 to RG4 thereafter stop the DC-DC conversion function all at once. It will be. As described above, in this embodiment, when the input voltage to be DC-DC converted (DC35V) drops to an abnormal level, the DC-DC conversion operation is automatically stopped, and hence the subsequent abnormal operation may occur. There is no.

  Returning to FIG. 4 (f), the description will be continued. The input portion of the comparator CM1 has a wired OR configuration, and either one or both of the voltage from the monitoring terminal Sin1 and the voltage from the detection terminal REF are detected. When the comparison reference voltage is less than 2.5 V, an L level detection signal is output to the output terminal Sout1.

  The L level detection signal output from the output terminal Sout1 indicates that the AC power supply (AC24V) has dropped or the DC voltage (5V, 12V) to be distributed to the main control board 21 and the payout control board 24 has dropped. As shown, the power supply abnormality signals ABN1 and ABN2 are distributed to the control boards 21 and 24, respectively.

  In this embodiment, the output terminal Sout1 of the converter RG2 is connected to the detection terminal REF of the converter RG4. Therefore, when the voltage at output terminal Sout1 of converter RG2 transitions to L level and detection terminal REF of converter RG4 transitions to L level, output terminal Sout1 of converter RG4 transitions to L level in response to this operation. It will be.

  Corresponding to such a circuit configuration, in this embodiment, the output voltage DC12V of the converter RG2 is monitored by a voltage dividing circuit using voltage dividing resistors RA and RB, and the output voltage DC5V of the converter RG4 is monitored by the voltage dividing resistors Ra, Monitoring is performed by a voltage dividing circuit using Rb. The monitoring outputs of the voltage dividing circuits are coupled through a diode D7 and supplied as a monitoring voltage DE1 to the detection terminal REF of the converter RG2. Here, the voltage dividing resistors RA and RB and the voltage dividing resistors Ra and Rb are set to values corresponding to the output voltages DC12V and DC5V of the converters RG2 and RG4, respectively. When the output voltage is a predetermined level of 12V and 5V), the monitoring voltage DE1 supplied to the detection terminal REF of the converter RG2 is designed to be about 2.55V.

  Therefore, during normal operation, output terminal Sout1 of converter RG2 (comparator CM1) is at the H level. On the other hand, when one or both of the output voltages of converters RG2 and RG4 fall below a predetermined level of 12V or 5V, output terminal Sout1 of converter RG2 (comparator CM1) drops from H level to L level. As described above, since the output terminal Sout1 of the converter RG2 is connected to the detection terminal REF of the converter RG4, the detection terminal REF of the converter RG4 transitions to the L level together with the output terminal Sout1 of the converter RG2. The output terminal Sout1 of RG4 transitions to the L level.

  Meanwhile, the monitoring voltage DE2 shown in FIG. 4E is supplied to the monitoring terminal Sin1 of the converter RG4 constituting the AC monitoring circuit 64. The monitoring voltage DE2 is originally a pulsating current of 24V AC, but is transmitted to the 5.1V Zener diode via the current limiting resistor R4, so that the detection voltage has an amplitude of about 5.1V. , And supplied to the comparator CM1 of the converter RG4. In FIG. 4 (e), the monitoring voltage DE2 is shown in a pulse waveform. However, unless the AC power supply AC24V is cut off, the monitoring voltage DE2 is based on the capacitance component of the circuit element, the stray capacitance on the wiring, and the like. Never fall below the 2.5V level. That is, even if the instantaneous value of the AC power supply AC 24V in the power supply state is 0V, the monitoring voltage DE2 exceeds the 2.5V level.

  On the other hand, when AC power supply AC24V is interrupted (regardless of the voltage level of detection terminal REF and DC input terminal Vin of converter RG4 at that time), output terminal Sout1 of converter RG4 quickly transitions to the L level. The output from the output terminal Sout1 is transmitted to the main control board 21 and the payout control board 24 as well as the power supply abnormality signals ABN1 and ABN2 described above. Therefore, each control board 21 and 24 can quickly start a necessary backup operation. The backup operation means an operation for storing necessary data so that the game operation before power-off can be resumed after power-on, and the stored data is maintained by the backup power supply BAK (power backup function). . In this embodiment, the memory contents of the RAM of each one-chip microcomputer are designed to be retained for at least several days.

  As described above, the power supply abnormality signals ABN1 and ABN2 are also output when the DC voltage (5V, 12V) to be distributed to the main control board 21 or the payout control board 24 drops to an abnormal level. In other words, in this embodiment, converters RG2 and RG4 and their associated circuits and AC monitoring circuit 64 cooperate to detect an abnormality in AC input voltage AC24V and an abnormality in a plurality of levels of DC output voltages (5V, 12V). Since monitoring is performed collectively, there is an advantage that the main control unit 21 and the payout control unit 24 can quickly cope with all abnormalities. It is as follows when the monitoring operation in the power supply board | substrate 20 is confirmed also including the above point.

  (1) When the AC power supply AC24V is shut off, the monitoring voltage DE2 received from the AC monitoring circuit 64 falls below the comparison reference voltage 2.5V, so that the power supply abnormality output from the output terminal Sout1 of the converter RG4 (AC monitoring circuit 64) The signals ABN1 and ABN2 quickly become L level.

  (2) When the DC output voltage 12V or the DC output voltage 5V transmitted to the main control board 21 or the payout control board 24 drops, the output terminal Sout1 of the converter RG2 is at a timing when the monitoring voltage DE1 falls below the comparison reference voltage 2.5V. Then, detection terminal REF of converter RG4 becomes L level, and power supply abnormality signals ABN1 and ABN2 output from output terminal Sout1 of converter RG4 become L level. The power supply abnormality signals ABN1 and ABN2 are at the L level even when the AC power supply AC24V is being supplied. For example, even when the converters GR2 and RG4 are abnormal, the control boards 21 and 24 require the necessary backup operation. Can start.

  (3) When the DC voltage DC35V output from the power factor correction circuit 62 drops and the monitoring voltage DE1 falls below the comparison reference voltage 2.5V, the output voltage at the output terminal Sout2 of the converter RG2 or the converter RG4 becomes L level. Transition is made and the operations of converters RG1 to RG4 are stopped. As a result, the levels of the DC output voltage 12V and the DC output voltage 5V to be transmitted to the main control board 21 and the payout control board 24 also drop, so that the output from the output terminal Sout1 of the converter RG4 is the same as in the case of (2). The power supply abnormality signals ABN1 and ABN2 are set to L level. This operation also does not matter whether or not the AC power supply AC24V is in a power supply state. For example, the control boards 21 and 24 are necessary even when the DC voltage drops due to an abnormality such as the rectifier circuit 61 or the power factor correction circuit 62. Backup operation can be started.

  The power supply board 20 of the present embodiment does not generate a power supply reset signal indicating that the AC power is turned on, and the power supply reset signal is transmitted to the main control board 21, the payout control board 24, the effect control board 22, and the like. Absent. Therefore, each control board 21, 24, 22 generates a power reset signal based on the distributed DC voltage (5V, 12V). Since the present embodiment adopts such a configuration, unlike the conventional device, there is no possibility that the CPU is abnormally reset by superimposing noise on the signal line for transmitting the power reset signal from the power supply board to each control board. .

  Next, based on the configuration of the power supply board 20 described above, another configuration of the gaming machine GM will be described with reference to FIG.

  As shown in FIG. 3, the main control board 21 is connected to the power supply board 20 via the main board relay board 32, and has three types of DC voltages DC35V, DC12V, and DC5V, a backup power supply BAK, and a power supply abnormality signal. Received ABN1. As described above with reference to FIG. 5, DC35V is transmitted to the various solenoids SLa to SLc via the first power supply line CB1.

  On the other hand, the payout control board 24 is directly connected to the power supply board 20 without going through a relay board, and receives the same power abnormality signal ABN2 and backup power supply BAK as the main control unit 21 receives, with three types of DC voltages DC35V. , DC12V, DC5V together. As shown in FIG. 5, DC35V is transmitted to the firing solenoid SLe via the second power supply line CB2.

  In this embodiment, the RAM clear signal CLR is generated by the main control unit 21 and transmitted to the one-chip microcomputer of the main control unit 21 and the payout control unit 24. Here, the RAM clear signal CLR is a signal for deciding whether or not to initialize all the areas of the built-in RAM of the one-chip microcomputer of each control unit 21 and 24. It has a value corresponding to the / OFF state.

  As shown in FIG. 3, the main control unit 21 transmits a control command CMD ″ to the payout control unit 24 via the main board relay board 32, while the payout control unit 24 issues a game ball payout operation. Is received, a status signal CON relating to an abnormality in the payout operation, and an operation start signal BGN, such as a replenishment signal, a payout shortage error signal, and a lower plate full signal. The operation start signal BGN is a signal that notifies the main control unit 21 that the initial operation of the payout control unit 24 has been completed after the power is turned on.

  The main control unit 21 is connected to each game component of the game board 5 via the game board relay board 31. And while receiving the switch signal of the detection switch built in each winning opening 16-18 on a game board, solenoids SLi, such as an electric tulip, are driven.

  Here, the detection switch is configured to operate with the power supply voltage VB (12 V) distributed from the main control unit 21. Each switch signal indicating a winning state to the symbol start opening 15 is converted to a TTL level or CMOS level switch signal by an interface IC that operates with the power supply voltage VB (12 V) and the power supply voltage Vcc (5 V). And then transmitted to the main control unit 21.

  As shown in FIG. 3, the effect control unit 22 receives three types of DC voltages (5V, 12V, and 32V) from the power supply board 20 via the power supply relay board 33 (see FIGS. 4 and 6). As described above with reference to FIG. 5, DC35V is transmitted to the lamp / motor drive board 30 via the third power feed line CB3, and finally to the drive power supply board 26. The DC 35V is stepped down to a predetermined level Vm by a DC-DC converter CN disposed on the drive power supply board 26, and then returned to the lamp / motor drive board 30 to become the drive voltages of the effect motors M1 to Mn.

  The effect control unit 22 receives a control command CMD and a strobe signal STB from the main control unit 21 (see FIGS. 3 and 6). Then, the effect control unit 22 supplies the lamp drive data SDATA (serial signal) to the LED drivers mounted on the lamp drive board 29 and the lamp / motor drive board 30. Although not particularly limited, the LED driver / motor driver mounted on the lamp driving board 29 and the lamp / motor driving board 30 has the same configuration as the LED driver mounted on the lamp driving board 36.

  In this embodiment, the same LED driver is used to drive the stepping motor, and the effect motor groups M1 to Mn are driven via the lamp / motor drive board 30. In this case, the motor drive data is a serial signal similar to the lamp drive data, and even if the number of production motors is increased in order to enrich production contents, the number of wiring cables does not increase, and the device configuration is simplified. .

  Note that the motor drive data, which is a serial signal, is reproduced as motor drive pulses Φ1 to Φi and output to the production motors M1 to Mn in a motor driver having the same configuration as the LED driver.

  As shown in FIGS. 3 and 6, the effect control unit 22 sends the control command CMD ′ and the strobe signal STB ′, the system reset signal SYS, and two types of DC voltages (12V and 5V) to the image control unit 23. Is output.

  The image control unit 23 drives the display device DS based on the control command CMD 'to execute various image effects. The display device DS emits light by an LED backlight, and is driven by receiving five pairs of LVDS (Low voltage differential signaling) signals and a backlight power supply voltage (12 V) from the image interface board 28. (See FIG. 6).

  Next, the configurations of the effect control unit 22 and the image control unit 23 will be described in more detail. As shown in FIG. 6, the effect control unit 22 stores a one-chip microcomputer 40 that executes processing such as a sound effect, a lamp effect, a notice effect by an effect movable body, and data transfer, and a control program for the one-chip microcomputer 40. A control memory (flash memory) 41, a voice synthesis circuit (voice synthesis IC) 42 that reproduces and outputs a voice signal based on an instruction from the one-chip microcomputer 40, and a compressed voice that is original data of the reproduced voice signal An audio memory 43 that stores data and two digital amplifiers 46a and 46b that receive the digital audio signal from the audio synthesis circuit 42 and amplify the class D are configured.

  The voice memory 43 is a non-volatile memory that can be accessed from the voice synthesis circuit 42, and a series of background music (BGM), a group of performance sounds (notice sound), etc. are converted into phrase compressed data (original sound data). ). Each original sound data is specified by an 11-bit long phrase number (000H to 7FFH), and the speech synthesis circuit 42 and the one-chip microcomputer 40 can specify the original sound data by the phrase number. .

  The amplified output (analog audio signal) of the digital amplifier 46a is supplied to a low-frequency speaker, and the amplified output (analog audio signal) of the digital amplifier 46b is substantially aligned in the left and right positions with respect to the player 2. Is supplied to each speaker.

  The effect control board 22 is supplied with a 4-bit switch signal from a setting switch SET operated by an attendant. Here, the setting switch SET is a board-side member that is arranged on the back side of the game board 5 and is operated when necessary. As shown in FIGS. 3 and 6, the setting switch SET is arranged separately from the volume switch VSW (see FIG. 1) which is a frame side member. When the clerk operates the setting switch SET, the set value of the volume switch VSW set by the player becomes invalid. However, thereafter, the set value of the volume switch VSW set by the player becomes effective except when a serious abnormal situation occurs.

  As shown in FIG. 6, the effect control board 22 receives three types of DC voltages (Vcc = 5V, VB = 12V, 32V) from the power supply board 20 via the power supply relay board 33. Then, the DC voltages Vcc and VB are transferred as they are to the image interface board 28 and the image control board 23, and the DC voltage 32V is transferred as it is from the lamp / motor drive board 30 to the drive power supply board 26 to a predetermined level Vm. After being stepped down, it is utilized as a drive voltage for the production motors M1 to Mn.

  The DC voltage Vcc is used as a power supply voltage for various digital circuits of the effect control board 22, and the DC voltage VB is used as a power supply voltage for the digital amplifiers 46a and 46b and is also transferred to the drive boards 29 and 30. Used for lamp production and motor production.

  In addition, the effect control board 22 is provided with a power supply circuit that generates three types of DC voltages at a drop level based on the DC voltage VB received from the power supply board 20 (see the left side of FIG. 6). Specifically, the power supply circuit includes a first DC-DC converter CONV1 that generates a DC voltage 1.0V from a DC voltage 12V, and a second DC-DC converter CONV2 that generates a DC voltage 3.3V from the DC voltage 12V. And a third DC-DC converter CONV3 that generates a direct-current voltage 1.8V from a direct-current voltage 3.3V.

  The DC voltage 1.0V is a power supply voltage for the core circuit built in the voice synthesis circuit 42, and the DC voltage 3.3V is a one-chip microcomputer 40, a control memory 41, a voice synthesis circuit 42, and a voice memory. 43 is used as the power supply voltage. The DC voltage 3.3 V supplied to the voice synthesis circuit 42 is a power supply voltage for the built-in interface circuit. The DC voltage 1.8V received by the one-chip microcomputer 40 is the power supply voltage of the built-in core circuit, and the DC voltage 3.3V is the power supply voltage of the built-in interface circuit.

  Thus, in the effect control board 22 of the present embodiment, the power supply voltages of the main circuit elements (IC) are less than all Vcc (5 V), specifically, the notarized value 3.3 V or less. In addition, since the power supply voltages of the core circuits that control the arithmetic processing are all not more than 1.8 V, the power consumption can be greatly suppressed even when complicated and sophisticated operations are processed at high speed.

  The effect control board 22 is provided with a reset circuit RST & WDT. Based on two types of DC voltages (DC 12 V and DC 5 V) received from the power supply board 20, the first reset signal SYS and the first reset signal SYS which starts later are provided. Two reset signals RSET are generated. The reset circuit RST & WDT also serves as a watchdog timer.

  Next, another circuit configuration of the effect control unit 22 will be described. First, the one-chip microcomputer 40 has a plurality of parallel input / output ports PIO (Pi + Pi '+ Po + Po') and a plurality of serial output ports SI as shown in FIG. More specifically, the serial output port SI includes three-channel serial ports (S0 to S2). Each of the LED drivers mounted on the lamp driving boards 36, 29, and 30 is connected to each of the LED drivers. Serial drive data SDATA0 to SDATA2 are output in synchronization with clock signals CK0 to CK2.

  That is, the serial port S0 to serial port S2 transmit serial drive data SDATA0 to SDATA2 to the corresponding lamp drive boards 36, 29, and 30 based on the clock synchronization method. The serial drive data SDATA0 to SDATA2 are mostly brightness data (lamp drive data) for adjusting the light emission brightness of each LED by PWM control (pulse width modulation), but drive the production motors M1 to Mn. Motor drive data to be included is also included.

  The parallel output port Po ′ outputs 3-bit operation enable signals ENABLE0 to ENABLE2 to the lamp drive boards 36, 29, 30 and the LED drivers mounted on the lamp drive boards 36, 29, 30. Starts operation based on one of the operation enable signals ENABLE0 to ENABLE2. The output port Po 'outputs a MUTE signal for silencing the outputs of the digital amplifiers 46a and 46b. This MUTE signal is used, for example, when power is turned on, which may cause the operation to become unstable, or when an abnormal operation of the speech synthesis circuit 42 is detected.

  Corresponding to such a configuration, the production control board 22 includes parallel output ports Po ′ of the one-chip microcomputer 40, serial buffer SI, and output buffer circuits 47, 48, and 49 for transmitting various signals to be output. Is provided. Here, the output buffer 47 is related to the LED group of the 0th channel, and outputs the lamp driving data SDATA0, the clock signal CK0, and the operation permission signal ENABLE0 output from the one-chip microcomputer 40 to the frame relay board 34. doing. The output 3-bit signal is transmitted to the LED driver of the lamp driving board 36 via the frame relay board 34 and the frame relay board 35.

  Similarly, the output buffer 48 transmits the lamp drive data SDATA1, the clock signal CK1, and the operation enable signal ENABLE1 output from the one-chip microcomputer 40 to the LED driver of the lamp drive board 29, and the output buffer 49 The drive data SDATA2, the clock signal CK2, and the operation permission signal ENABLE2 are transmitted to the LED driver of the lamp / motor drive board 30. The LED driver of the lamp driving board 29 drives the LED group of the first channel, and the LED driver of the lamp / motor driving board 30 drives the LED group of the second channel and the effect motors M1 to Mn. Yes.

  On the other hand, the control command CMD and the strobe signal STB from the main control unit 21 are input to the input port Pi of the parallel input / output port PIO via the input buffer 44, and the output buffer 45 is input from the command output port Po. A control command CMD ′ and a strobe signal STB ′ are output via the route.

  Specifically, the control command CMD and the strobe signal (interrupt signal) STB output from the main control board 21 correspond to the power supply voltage 3.3 V of the one-chip microcomputer 40 in the input buffer Pi. Is converted to a logical level and supplied to the one-chip microcomputer 40 in units of 8 bits. The interrupt signal STB is supplied to the interrupt terminal of the one-chip microcomputer 40, and the effect control unit 22 is configured to acquire a control command CMD by reception interrupt processing.

  The control command CMD acquired by the one-chip microcomputer 40 of the effect control unit 22 includes (1) abnormality notification and other notification control commands, and (2) various effect operations resulting from winning at the symbol start opening. A control command (variation pattern command) for specifying an outline and a control command (design specifying command) for specifying a symbol type are included. Here, the outline of the production operation specified by the variation pattern command includes the production total time from the production start to the production end and the result of winning or failing in the jackpot lottery.

  In addition, the symbol designating command includes information for identifying information on the jackpot type (15R probability variation, 2R probability variation, 15R normal, 2R normal, etc.) in the case of a jackpot according to the result of the jackpot lottery. In some cases, information for identifying a loss is included. The outline of the production operation specified by the variation pattern command includes the production total time from the production start to the production end, and the result of success or failure in the big hit lottery. In addition to these, the change pattern command including the presence or absence of the reach effect or the notice effect may be specified, but even in this case, the specific content of the effect content is not specified.

  Therefore, when the effect control unit 22 (one-chip microcomputer 40) acquires the variation pattern command, the effect lottery is subsequently performed, and the effect outline specified by the acquired variation pattern command is further specified. For example, the specific contents of the reach effect and the notice effect are determined. Then, in accordance with the determined specific game content, a lamp effect by blinking the LED group and a sound effect preparation operation by the speaker are performed, and the image control unit 23 is synchronized with the effect operation by the lamp and the speaker. The control command CMD ′ relating to the performed image effect is output.

  In order to realize such an image effect synchronized with the effect operation, the effect control unit 22 transmits a control command CMD ′ having a 16-bit length together with a strobe signal (interrupt signal) STB ′ to the image control unit 23 through the command output port Po. Are output toward the image interface board 28. When the design control command 22 receives a design designation command, a notification control command related to the display device DS, or other control command, the production control unit 22 interrupts the control command in a state of collecting the control command in a 16-bit length. It is output to the image interface board 28 together with the signal STB ′.

  An output buffer 45 is provided corresponding to the configuration of the effect control board 22 described above, and outputs a 16-bit control command CMD ′ and a 1-bit interrupt signal STB ′ to the image interface board 28. . These data CMD ′ and STB ′ are transmitted to the image control board 23 via the image interface board 28. These signals are at a logic level corresponding to the power supply voltage 3.3 V of the one-chip microcomputer 40.

  The parallel port Pi 'is supplied with a switch signal from a setting switch SET that is operated by an attendant to set the volume. The level of the switch signal of the setting switch SET is determined when the power is turned on, and an initial volume setting value is determined. After that, the setting position of the setting switch SET is determined regularly, and if there is a change from the initial state, the volume setting value according to the level of the switch signal at that time is obtained.

  In addition, on the effect control board 22, two digital amplifiers 46a and 46b for receiving the audio signal output from the audio synthesis circuit 42 are arranged. As described above, the speech synthesis circuit 42 operates with power supply voltages of 3.3V and 1.0V, and the digital amplifiers 46a and 46b operate with class D amplification with a power supply voltage of 12V. Enables sound production with high volume while suppressing power.

  Next, the drive power supply board 26 will be described with reference to FIG. The third power supply line CB3 is as described with reference to FIG. 5, but the drive power supply board 26 receives the DC 35V of the third power supply line CB3 from the effect control board 22 via the lamp / motor drive board 30. A voltage control signal CTL1 is also received.

  The drive power supply board 26 is configured around the DC-DC converter CN, and the output voltage Vout of the DC-DC converter CN is transmitted to the lamp / motor drive board 30 as the drive voltage Vm of the effect motors M1 to Mn. During the effect production, the production motors M1 to Mn are operated (see FIG. 7B).

  The DC-DC converter CN of the embodiment is configured with a built-in choke coil L (see FIG. 7C), and functions as a synchronous rectification step-down chopper type regulator. Therefore, in the following description, this DC-DC converter will be referred to as a step-down converter CN for convenience.

  The specific circuit configuration of the drive power supply substrate 26 is as shown in FIG. 7A. The step-down converter CN, the variable resistance circuit VR that controls the output voltage Vout of the step-down converter CN, the input capacitor Cin, and the output And a capacitor Cout.

  The capacitance values of the input capacitor Cin and the output capacitor Cout are related to the power consumption of the effect motors M1 to Mn, and are set to optimum values in the range of 20 μF to 800 μF corresponding to the maximum power consumption during the effect production. From this point of view, the illustrated drive power supply board 26 has six capacitance elements of about 10 μF arranged in parallel as the input capacitor Cin, and two capacitance elements of about 220 μF arranged in parallel as the output capacitor Cout. .

  The variable resistance circuit VR includes transistors Q1 and Q2 that perform switching operations in conjunction with each other, bias resistors R1 and R2 of the PNP transistor Q1, collector resistance R3 of the transistor Q1, and bias resistors R5 and R6 of the NPN transistor Q2. It consists of and. In this embodiment, the collector resistance R3 is, for example, about 400 kΩ, and the bias resistances R1, R2 are, for example, about 10 kΩ. The emitter terminal of the transistor Q1 is connected to the output terminal Vout of the step-down converter CN, and the collector resistor R3 is connected to the control terminal Adj of the step-down converter CN. In such a configuration, in this embodiment, since the bias resistor R1 is intentionally arranged in addition to the bias resistor R2, the transistor Q1 can be reliably maintained in the OFF state when the transistor Q2 is OFF.

  That is, when the transistor Q2 is OFF, the collector leakage current Lk flows through the transistor Q2 even though it is slight. If the bias resistor R1 is not present, this collector leakage current Lk is the path from the emitter terminal to the base terminal of the transistor Q1. The transistor Q1 (which becomes saturated when the collector current = several tens of μA) may be amplified or turned on. On the other hand, in this embodiment, a configuration is adopted in which the leakage current Lk flows through the bias resistor R1, and the voltage across the resistor R1 at that time is designed to a voltage value that does not cause the transistor Q1 to operate. Can be reliably maintained in the OFF state.

  As shown in FIG. 5 and FIG. 7A, the transistor Q2 is configured to receive the voltage control signal CTL1 from the effect control board 22. If the voltage control signal CTL1 is at the H level, the transistor Q2 is turned on. .

  When the transistor Q2 is turned on, a current flows through the bias resistors R1 and R2, and a base current of about several mA flows through the path from the emitter terminal to the base terminal, so that the PNP transistor Q1 is reliably turned on. In this embodiment, since the collector resistance R3 is about 400 kΩ, the collector saturation current when the transistor Q2 is turned on is about several tens of μA.

  In any case, when the voltage control signal CTL1 is at the H level, the resistance value between the output terminal Vout of the step-down converter CN and the control terminal Adj is about 400 kΩ corresponding to the resistance value of the collector resistor R3.

  On the other hand, if the voltage control signal CTL1 is at the L level, the transistor Q2 maintains the OFF state, and accordingly, the PNP transistor Q1 also maintains the OFF state. Therefore, when the voltage control signal CTL1 is at the L level, the resistance value between the output terminal Vout of the step-down converter CN and the control terminal Adj is substantially ∞. As described above, the transistor Q1 reliably maintains the OFF state regardless of the collector leakage current Lk of the transistor Q2.

  FIG. 7C is a diagram illustrating an internal configuration of the step-down converter CN. As shown in the figure, the step-down converter CN includes power transistors TR1 and TR2, which are MOS-FETs that perform complementary ON / OFF operations, a PWM circuit that supplies PWM signals with appropriate duty ratios to the transistors TR1 and TR2, and transistors The choke coil L through which the drain currents of TR1 and TR2 flow, the voltage dividing resistors Ra and Rb for dividing the output voltage Vout to obtain the detection voltage Vr, and the detection voltage Vr are compared with the comparison voltage REF to output the comparison voltage Vc. And a comparator COM.

  As illustrated, the voltage dividing resistor Ra is disposed between the output terminal Vout of the step-down converter CN and the control terminal Adj. The PWM circuit outputs a PWM signal with a switching frequency of 140 kHz, and the duty ratio of the PWM signal changes according to the output timing of the comparison voltage Vc.

  Based on the above, the operation content of the step-down converter CN will be described. First, at the timing when the transistor TR1 is in the ON state and the transistor TR2 is in the OFF state, the coil charging current indicated by a solid line shows an increasing tendency and flows through the choke coil L, and the choke coil L is charged with electromagnetic energy. Corresponding to this operation, the output voltage Vout increases, and the detection voltage Vr increases accordingly.

  Then, at the timing when the detection voltage Vr exceeds the comparison voltage REF, the level of the PWM signal transits, so that the transistor TR1 transits to the OFF state and the transistor TR2 transits to the ON state. Thereafter, the coil discharge current indicated by the broken line shows a decreasing tendency and flows through the choke coil L, whereby the electromagnetic energy is discharged.

  Then, at the timing specified by the switching frequency 140 kHz, the transistor TR1 returns to the ON state and the transistor TR2 returns to the OFF state, and the charging operation of the choke coil L described above is performed again.

  As is clear from the above description, the duty ratio of the PWM signal is defined at the timing when the detection voltage Vr exceeds the comparison voltage REF, and the timing is equivalent to the equivalent resistance of the variable resistance circuit VR that is connected in parallel with the voltage dividing resistor Ra. Will be defined by Rx.

  The equivalent resistance Rx changes according to the H / L level of the voltage control signal CTL1, and Rx = 400 kΩ when the voltage control signal CTL1 = H and Rx = ∞ when the voltage control signal CTL1 = L. In other words, when the voltage control signal CTL1 = H, the bias resistance Ra substantially decreases, so that the transition timing from the coil charging operation to the coil discharging operation is advanced, and the output voltage Vout is Will be reduced.

  The output voltage Vout in the reduced state is defined by the resistance value of the collector resistor R3. In this embodiment, by setting R3≈400 kΩ, the output voltage Vout is 15 V when the voltage control signal CTL1 = H. When the voltage control signal CTL1 = L, the output voltage Vout is about 18V.

  That is, in the present embodiment, the output voltage Vout of the step-down converter CN is 15V / 18V according to the H / L level of the voltage control signal CTL1. And this output voltage Vout is supplied to the production motors M1 to Mn as the motor drive voltage Vm.

  Here, the motor drive current changes by about 20% (18/15 = 1.2) depending on whether the motor drive voltage Vm is 15V or 18V. Since the strength of the excitation magnetic flux is proportional to the number of turns of the excitation winding and the drive current flowing in the winding, the rotational torque is set to 20 by controlling the motor drive voltage Vm as in this embodiment. % Can be changed.

  The voltage control signal CTL1 is supplied from the effect control board 22, but may be a fixed value in terms of hardware or software for each model of the gaming machine. May be variable.

  As a configuration in which the voltage control signal CTL1 is set to a fixed value, for example, in a model in which a large movable accessory is to be moved powerfully, the voltage control signal CTL1 = L and the other models are set to have the voltage control signal CTL1 = H. Can be considered. By adopting such a configuration, there is an advantage that the common drive power supply board 26 can be used for all models.

  In addition, as a configuration in which the voltage control signal CTL1 is changed by software, for example, the effect timing when the large movable accessory moves is set to the voltage control signal CTL1 = L, and the effect timing when the small movable accessory moves is It can be considered that the voltage control signal CTL1 = H. In this configuration, the drive voltage Vm supplied to the effect motor for driving the large movable accessory is 18V, and the drive voltage Vm supplied to the effect motor for driving the small movable accessory is 15V. Realistic effect production is realized.

  The embodiment has been described in detail above, but the specific description does not limit the present invention and can be changed as appropriate. For example, in the circuit configuration of FIG. 7, the drive voltage Vm is constantly supplied to the effect motors M1 to Mn. However, it is also preferable to supply the drive voltage Vm only during the effect effect by the movable accessory. is there.

  FIG. 8 is a drawing showing such a modified embodiment, in which a cutoff circuit CUT is arranged between the input capacitor Cin and the step-down converter CN. As shown in the figure, the cutoff circuit CUT includes a PNP type power transistor Q3, bias resistors R7 and R8 of the transistor Q3, an NPN type switching transistor Q4, and bias resistors R9 and R10 of the transistor Q4. .

  In this embodiment, an operation control signal CTL2 for ON / OFF control of the transistor Q4 is supplied from the effect control board 22 to the drive power supply board 26. Prior to this, the step-down converter CN starts to operate by setting the operation control signal CTL2 to CTL2 = H. And after an effect production is complete | finished, useless power consumption can be eliminated by setting operation control signal CTL2 to CTL2 = L.

  By adopting such a configuration, even if the drive pulse Φi for the production motor in the standby state is garbled due to noise and all phases of the production motor are turned on, smoke and fire are prevented. can do.

  As described above, in the embodiments described so far, the voltage control signal CTL1 is supplied from the effect control board 22. However, when the voltage control signal CTL1 is fixed, the voltage control signal CTL1 is generated inside the drive power supply board 26. May be generated.

  FIG. 8B illustrates such a modified embodiment. By arranging voltage dividing resistors R11 and R12 that divide DC35V, a voltage control signal CTL1 of about 17.9V is generated. . In this state, the transistor Q1 is OFF and the output voltage is about 18V. On the other hand, when adopting a circuit configuration in which the bias resistor R12 is short-circuited, the transistor Q1 is turned on, and the output voltage becomes about 15V.

GM gaming machine 21 main control means 22 effect control means 20 power supply means M1 to Mn effect motor SLi inductance member Cin capacitance member TH2 current limiting member

Claims (10)

A gaming machine that executes a lottery process based on a predetermined switch signal and can execute a gaming operation according to the lottery result,
Main control means for controlling the game operation centrally by executing the lottery process, effect control means for executing effect operation based on an instruction from the main control means, the main control means and the effect control means Power generation means for generating various levels of DC voltage for functioning, and the effect operation includes a movable effect executed by the effect motor,
The main control means supplies the first level DC voltage supplied from the power supply means to a predetermined inductance member while maintaining the level, while the effect control means receives the first voltage supplied from the power supply means. After receiving the DC voltage of the level at the capacitance member, the level is lowered and supplied to the effect motor,
The first level DC voltage generated by the power supply means is:
Power is supplied to the main control means without interposing a temperature-dependent current limiting member, while power is supplied to the effect control means via a predetermined current-limiting member having temperature dependency. A gaming machine characterized by being configured. The first level DC voltage has a notarized value of 30 V or more, and is fed via one or a plurality of circuit boards to a drive power supply board on which a step-down circuit is mounted together with the capacitance member,
2. The gaming machine according to claim 1, wherein the first level DC voltage is supplied to the step-down circuit in a state where the first level DC voltage is smoothed by the capacitance member, and the level is lowered.   The first level DC voltage is supplied to the effect control means via a one-touch connector in which a plurality of contacts are connected in one mounting operation and a plurality of contacts are separated in one separating operation. The gaming machine according to claim 1 or 2, wherein the gaming machine is configured.   The gaming machine according to claim 1, wherein the inductance member is driven by a driver IC that exhibits an overheat protection function without requiring a power supply voltage.   5. The gaming machine according to claim 1, wherein the predetermined current limiting member is a thermistor having a resistance value of 25 ° C. and a notarized value of 1Ω to 3Ω.   The gaming machine according to claim 5, wherein the thermistor has a heat dissipation constant δ of 14 mW / ° C to 27 mW / ° C.   The gaming machine according to claim 1, wherein the capacitance member has a capacitance of 20 μF or more.   The power supply means applies a second level DC voltage lower than the first level and a notarized 5V DC voltage lower than the second level to the main control means and the effect control means together with the first level DC voltage. The gaming machine according to any one of claims 1 to 7, wherein power is supplied.   The gaming machine according to any one of claims 1 to 8, wherein the second level DC voltage is used as a driving voltage of a lamp and / or a driving voltage of a sensor that detects the predetermined switch signal.   The gaming machine according to claim 2, wherein the step-down circuit is configured such that its output voltage can be changed.