JP5854104B2 - Semiconductor device - Google Patents

Description

The present invention relates to semiconductor equipment.

  As semiconductor devices are miniaturized and highly integrated, transistor threshold voltage variations due to statistical fluctuations of channel impurities are becoming apparent. The threshold voltage is one of the important parameters that determine the performance of the transistor. In order to manufacture a high-performance and high-reliability semiconductor device, it is important to reduce variations in threshold voltage due to statistical fluctuations of impurities.

  As one technique for reducing the variation in threshold voltage due to statistical fluctuation of impurities, a method of forming a non-doped epitaxial silicon layer on a high-concentration channel impurity layer having a steep impurity concentration distribution has been proposed.

US Pat. No. 6,482,714 US Patent Application Publication No. 2009/0108350

A. Asenov, "Suppression of Random Dopant-Induced Threshold Voltage Fluctuations in Sub-0.1-μm MOSFET's with Epitaxial and δ-Doped Channels", IEEE Transactions on Electrond Devices, Vol. 46, NO. 8, p. 1718, 1999 Woo-Hyeong Lee, "MOS Device Structure Development for ULSI: Low Power / High Speed Operation", Microelectron. Reliab., Vol. 37, No. 9, pp. 1309-1314, 1997 A. Hokazono et al., "Steep Channel Profiles in n / pMOS Controlled by Boron-Doped Si: C Layers for Continual Bulk-CMOS Scaling", IEDM09-673

  However, no specific proposal has been made for a method for incorporating the proposed technique into the semiconductor device manufacturing process. For example, specific studies have not been made on new problems and solutions for the problems that occur when applied to a manufacturing process of a semiconductor device including a low-voltage operation transistor and a high-voltage operation transistor.

An object of the present invention satisfies both requirements of the transistors of the transistor and the high voltage operation of low voltage operation, there is provided a semiconductor equipment capable of high performance and high reliability.

According to one aspect of the embodiment, a semiconductor substrate having a first region and a second region, and a first substrate formed in the first region of the semiconductor substrate and having a first impurity of a first conductivity type. 1 impurity layer, a first semiconductor layer formed on the first impurity layer, a first gate insulating film formed on the first semiconductor layer, and the first gate insulating film A first gate electrode formed thereon; a first source / drain region formed in the semiconductor substrate of the first semiconductor layer and the first region; and the second region of the semiconductor substrate. is formed, said second impurity layer having a first second impurity of a small first conductivity type diffusion constant than the impurity, a second semiconductor formed on the second impurity layer And a layer formed on the second semiconductor layer and thinner than the first gate insulating film A second gate insulating film, a second gate electrode formed on the second gate insulating film, a second source formed on the semiconductor substrate in the second semiconductor layer and the second region / drain region, was closed, the impurity concentration of the first impurity in the first semiconductor layer, said first lower than the impurity concentration of said first impurity in the impurity layer, the second semiconductor The semiconductor device is characterized in that the impurity concentration of the second impurity in the layer is lower than the impurity concentration of the second impurity in the second impurity layer .
According to another aspect of the embodiment, a semiconductor substrate having a first region and a second region, and a first impurity of the first conductivity type formed in the first region of the semiconductor substrate. A first impurity layer comprising: a first semiconductor layer formed on the first impurity layer; a first gate insulating film formed on the first semiconductor layer; A first gate electrode formed on a gate insulating film; a first source / drain region formed in the semiconductor substrate of the first semiconductor layer and the first region; and the first source electrode of the semiconductor substrate. A second impurity layer formed in the second region and having a first impurity and a third impurity that suppresses diffusion of the first impurity, and a second impurity layer formed on the second impurity layer. More than the first gate insulating film formed on the semiconductor layer and the second semiconductor layer A thin second gate insulating film, a second gate electrode formed on the second gate insulating film, and a second semiconductor layer and a second region formed on the semiconductor substrate in the second region. And a source / drain region of the semiconductor device.

According to the semiconductor equipment disclosed, in a transistor having an epitaxial layer on the channel impurity layer, while the channel impurity layer of the low-voltage transistor steep impurity distribution, on a gentle impurity distribution channel impurity layer of the high-voltage transistor can do. Thereby, the threshold voltage of the low voltage transistor can be stabilized, the junction breakdown voltage and hot carrier resistance of the high voltage transistor can be improved, and a semiconductor device having high performance and high reliability can be realized.

FIG. 1 is a schematic cross-sectional view (part 1) illustrating the structure of the semiconductor device according to the first embodiment. FIG. 2 is a schematic cross-sectional view (part 2) illustrating the structure of the semiconductor device according to the first embodiment. FIG. 3 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 3 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 5 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a process cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 7 is a process cross-sectional view (part 5) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a process cross-sectional view (No. 6) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 9 is a process cross-sectional view (No. 7) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view (No. 8) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 11 is a process cross-sectional view (No. 9) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 12 is a process cross-sectional view (No. 10) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 13 is a process cross-sectional view (No. 11) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 14 is a process cross-sectional view (No. 12) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 15 is a process cross-sectional view (No. 13) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 16 is a process cross-sectional view (No. 14) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 17 is a process cross-sectional view (No. 15) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 18 is a process cross-sectional view (No. 16) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 19 is a process cross-sectional view (No. 17) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 20 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 21 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 22 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 23 is a process cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 24 is a process cross-sectional view (part 1) illustrating the method for manufacturing a semiconductor device according to the first reference example; FIG. 25 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first reference example; FIG. 26 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the first reference example; FIG. 27 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the second reference example; FIG. 28 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the second reference example; FIG. 29 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the second reference example; FIG. 30 is a process cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the second reference example; FIG. 31 is a process cross-sectional view (part 5) illustrating the method for manufacturing a semiconductor device according to the second reference example; FIG. 32 is a process cross-sectional view (No. 6) illustrating the method for manufacturing the semiconductor device according to the second reference example.

[First Embodiment]
The semiconductor device and the manufacturing method thereof according to the first embodiment will be described with reference to FIGS.

  1 and 2 are schematic cross-sectional views illustrating the structure of the semiconductor device according to the present embodiment. 3 to 20 are process cross-sectional views illustrating the method for fabricating the semiconductor device according to the present embodiment.

  First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIGS.

  A low voltage NMOS transistor (LV NMOS), a low voltage PMOS transistor (LV PMOS), a high voltage NMOS transistor (HV NMOS), and a high voltage PMOS transistor (HV PMOS) are formed on the silicon substrate 10. Yes. The low voltage transistor is mainly used in a circuit portion that requires high speed operation. The high voltage transistor is used for a circuit portion to which a high voltage is applied such as 3.3 V I / O.

  The low voltage NMOS transistor (LV NMOS) is formed in the low voltage NMOS transistor formation region 16 of the silicon substrate 10.

  A P well 20 and a P type high concentration impurity layer 22 are formed in the silicon substrate 10 in the low voltage NMOS transistor formation region 16. A silicon layer 48 epitaxially grown on the silicon substrate 10 is formed on the P-type high concentration impurity layer 22. On the silicon layer 48, a gate insulating film 64a is formed. A gate electrode 66 is formed on the gate insulating film 64a. Source / drain regions 78 are formed in the silicon layer 48 on both sides of the gate electrode 66 and in the silicon substrate 10. As a result, a low voltage NMOS transistor (LV NMOS) is formed.

  The low voltage PMOS transistor is formed in the low voltage PMOS transistor formation region 24 of the silicon substrate 10.

  An N well 28 and an N type high concentration impurity layer 30 are formed in the silicon substrate 10 in the low voltage PMOS transistor formation region 24. A silicon layer 48 epitaxially grown on the silicon substrate 10 is formed on the N-type high concentration impurity layer 30. On the silicon layer 48, a gate insulating film 64a is formed. A gate electrode 66 is formed on the gate insulating film 64a. Source / drain regions 80 are formed in the silicon layer 48 on both sides of the gate electrode 66 and in the silicon substrate 10. As a result, a low voltage PMOS transistor (LV PMOS) is formed.

  The high voltage NMOS transistor (HV NMOS) is formed in the high voltage NMOS transistor formation region 32 of the silicon substrate 10.

  A P well 36 and a P type impurity layer 38 are formed in the silicon substrate 10 in the high voltage NMOS transistor formation region 32. The P-type impurity layer 38 has a lower impurity concentration and a gentle impurity distribution than the P-type high-concentration impurity layer 22 of the low-voltage NMOS transistor in order to improve junction breakdown voltage and hot carrier resistance. On the P-type impurity layer 38, a silicon layer 48 epitaxially grown on the silicon substrate 10 is formed. On the silicon layer 48, a gate insulating film 60a thicker than the gate insulating film 64a of the low voltage transistor is formed. A gate electrode 66 is formed on the gate insulating film 60a. Source / drain regions 78 are formed in the silicon layer 48 on both sides of the gate electrode 66 and in the silicon substrate 10. As a result, a high voltage NMOS transistor (HV NMOS) is formed.

  The high voltage PMOS transistor (HV PMOS) is formed in the high voltage PMOS transistor formation region 40 of the silicon substrate 10.

  An N well 44 and an N type impurity layer 46 are formed in the silicon substrate 10 in the high voltage PMOS transistor formation region 40. The N-type impurity layer 46 has a lower concentration and gentle impurity distribution than the N-type high-concentration impurity layer 30 of the low-voltage PMOS transistor in order to improve junction breakdown voltage and hot carrier resistance. On the N-type impurity layer 46, a silicon layer 48 epitaxially grown on the silicon substrate 10 is formed. On the silicon layer 48, a gate insulating film 60a thicker than the gate insulating film 64a of the low voltage transistor is formed. A gate electrode 66 is formed on the gate insulating film 60a. Source / drain regions 80 are formed in the silicon layer 48 on both sides of the gate electrode 66 and in the silicon substrate 10. As a result, a high voltage PMOS transistor (HV PMOS) is formed.

  A metal silicide film 84 is formed on the gate electrode 66 and the source / drain regions 78 and 80 of each transistor.

  An interlayer insulating film 86 is formed on the silicon substrate 10 on which four types of transistors are formed. A contact plug 88 connected to the transistor is embedded in the interlayer insulating film 86. A wiring 90 is connected to the contact plug 88.

  Thus, the semiconductor device according to the present embodiment has two types of low voltage transistors and two types of high voltage transistors.

  In each of the low voltage transistors, for example, as shown in FIG. 2, a high concentration impurity layer 108 having a steep impurity concentration distribution and a non-doped silicon layer 110 epitaxially grown on the high concentration impurity layer 108 are formed in the channel region 106. It has. Such a transistor structure is effective for suppressing variation in threshold voltage of the transistor due to statistical fluctuation of impurities. In order to suppress the threshold voltage variation, it is important that the impurity concentration distribution of the high concentration impurity layer 108 is steep.

  In order to realize a steep impurity concentration distribution, carbon for preventing boron diffusion is introduced into the high concentration impurity layer 22 of the low voltage NMOS transistor in addition to boron as an acceptor impurity. In addition, arsenic or antimony having a small diffusion constant is introduced as a donor impurity into the high-concentration impurity layer 30 of the low-voltage PMOS transistor.

  On the other hand, if the impurity layer 38 of the high-voltage NMOS transistor and the impurity layer 46 of the high-voltage PMOS transistor have a high concentration and a steep impurity concentration distribution, the junction breakdown voltage and hot carrier resistance are reduced. For this reason, boron is introduced as an acceptor impurity into the impurity layer 38 of the high-voltage NMOS transistor, but carbon having a diffusion preventing effect is not introduced. Further, phosphorus having a diffusion constant larger than that of arsenic or antimony is introduced into the impurity layer 46 of the high voltage PMOS transistor. As a result, the impurity layer 38 and the impurity layer 46 have a low concentration and a gentle distribution as compared with the high concentration impurity layer 22 and the high concentration impurity layer 30.

  Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.

  First, a groove 12 used as a mark for mask alignment is formed outside a product formation region (for example, a scribe region) of the silicon substrate 10 by photolithography and etching.

  In the method for manufacturing the semiconductor device according to the present embodiment, a well and a channel impurity layer are formed before the element isolation insulating film 58 is formed. The groove 12 is used as a mark for mask alignment in a lithography process (such as formation of a well or a channel impurity layer) performed before the element isolation insulating film 58 is formed.

  The reason why the well and the channel impurity layer are formed before the formation of the element isolation insulating film 58 is to suppress the reduction of the element isolation insulating film 58 when the silicon oxide films 14, 52, 60 are removed (see FIG. (See first reference example below).

  Next, a silicon oxide film 14 as a protective film on the surface of the silicon substrate 10 is formed on the entire surface of the silicon substrate 10 by, eg, thermal oxidation (FIG. 3).

  Next, a photoresist film 18 that exposes the low-voltage NMOS transistor formation region 16 and covers other regions is formed by photolithography. The mark of the groove 12 is used for alignment of photolithography.

  Next, ion implantation is performed using the photoresist film 18 as a mask to form a P well 20 and a P type high concentration impurity layer 22 in the low voltage NMOS transistor formation region 16 of the silicon substrate 10 (FIG. 4).

The P well 20, for example, implants boron ions (B ⁺ ) from four directions inclined with respect to the substrate normal direction under the conditions of acceleration energy 150 keV and dose amount 7.5 × 10 ¹² cm ^−2. To form. The P-type high-concentration impurity layer 22 uses germanium ions (Ge ⁺ ), for example, under conditions of acceleration energy of 50 keV and a dose amount of 5 × 10 ¹⁴ cm ⁻² , carbon ions (C ⁺ ), for example, acceleration energy of 3 keV, Boron ions are formed by ion implantation under conditions of a dose amount of 3 × 10 ¹⁴ cm ⁻² , for example, under an acceleration energy of 2 keV and a dose amount of 3 × 10 ¹³ cm ⁻² . Germanium makes the silicon substrate 10 amorphous to prevent channeling of boron ions, and also makes the silicon substrate 10 amorphous to increase the probability that carbon is arranged at lattice points. Carbon arranged at the lattice points acts to suppress the diffusion of boron. From this point of view, germanium is ion-implanted before carbon and boron. The P well 20 is desirably formed before the P-type high concentration impurity layer 22.

  Next, the photoresist film 18 is removed by, for example, ashing.

  Next, a photoresist film 26 that exposes the low-voltage PMOS transistor formation region 24 and covers other regions is formed by photolithography. The mark of the groove 12 is used for alignment of photolithography.

  Next, ion implantation is performed using the photoresist film 26 as a mask to form an N well 28 and an N type high concentration impurity layer 30 in the low voltage PMOS transistor formation region 24 of the silicon substrate 10 (FIG. 5).

In the N well 28, for example, phosphorus ions (P ⁺ ) are respectively ion-implanted from four directions inclined with respect to the substrate normal direction under the conditions of an acceleration energy of 360 keV and a dose amount of 7.5 × 10 ¹² cm ^−2. To form. The N-type high concentration impurity layer 30 is formed, for example, by ion-implanting arsenic ions under the conditions of an acceleration energy of 6 keV and a dose of 2 × 10 ¹³ cm ⁻² . The N well 28 is desirably formed before the N-type high concentration impurity layer 30.

  Next, the photoresist film 26 is removed by, for example, ashing.

  Next, a photoresist film 34 that exposes the high-voltage NMOS transistor formation region 32 and covers the other regions is formed by photolithography. The mark of the groove 12 is used for alignment of photolithography.

  Next, ion implantation is performed using the photoresist film 34 as a mask to form a P well 36 and a P type impurity layer 38 in the high voltage NMOS transistor formation region 32 of the silicon substrate 10 (FIG. 6).

The P well 36 is formed, for example, by implanting boron ions from four directions inclined with respect to the normal direction of the substrate under conditions of an acceleration energy of 150 keV and a dose of 7.5 × 10 ¹² cm ^−2. To do. The P-type impurity layer 38 is formed by ion-implanting boron ions, for example, under conditions of an acceleration energy of 2 keV and a dose amount of 5 × 10 ¹² cm ⁻² . In the high voltage NMOS transistor, ion implantation of carbon and germanium is not performed from the viewpoint of improving the junction breakdown voltage and hot carrier resistance by smoothing the impurity concentration distribution in the channel region.

  Next, the photoresist film 34 is removed by, for example, ashing.

  Next, a photoresist film 42 that exposes the high-voltage PMOS transistor formation region 40 and covers other regions is formed by photolithography. The mark of the groove 12 is used for alignment of photolithography.

  Next, ion implantation is performed using the photoresist film 42 as a mask to form an N well 44 and an N type impurity layer 46 in the high voltage PMOS transistor formation region 40 of the silicon substrate 10 (FIG. 7).

The N well 44 is formed, for example, by implanting phosphorous ions from four directions inclined with respect to the substrate normal direction under the conditions of an acceleration energy of 360 keV and a dose of 7.5 × 10 ¹² cm ^−2. . The N-type impurity layer 46 is formed by implanting phosphorus ions under the conditions of, for example, acceleration energy of 2 keV and a dose amount of 5 × 10 ¹² cm ⁻² . In the high voltage PMOS transistor, phosphorus having a diffusion constant larger than that of arsenic is used from the viewpoint of improving the junction breakdown voltage and hot carrier resistance by smoothing the impurity concentration distribution in the channel region.

  Next, the photoresist film 42 is removed by, for example, ashing.

  Next, heat treatment is performed in an inert atmosphere to recrystallize the silicon substrate 10 and arrange the implanted impurities at lattice positions. For example, heat treatment is performed at 600 ° C. for 150 seconds in a nitrogen atmosphere, and then heat treatment is performed at 1000 ° C. for 0 second.

  Next, a non-doped silicon layer 48 of, eg, a 30 nm-thickness is epitaxially grown on the surface of the silicon substrate 10 by, eg, CVD (FIG. 8).

  Next, the surface of the silicon layer 48 is wet-oxidized under reduced pressure by, for example, an ISSG (in-situ steam generation) method to form a silicon oxide film 52 having a thickness of 3 nm, for example. The processing conditions are, for example, a temperature of 810 ° C. and a time of 20 seconds.

  Next, a silicon nitride film 54 of, eg, a 70 nm-thickness is deposited on the silicon oxide film 52 by, eg, LPCVD. The processing conditions are, for example, a temperature of 700 ° C. and a time of 150 minutes.

  Next, the silicon nitride film 54, the silicon oxide film 52, the silicon layer 48, and the silicon substrate 10 are anisotropically etched by photolithography and dry etching, and an element isolation region including a region between the transistor formation regions is formed in the element isolation region. A separation groove 56 is formed (FIG. 9). Note that the mark of the groove 12 is used for alignment of photolithography.

  Next, the surface of the silicon layer 48 and the silicon substrate 10 is wet-oxidized under reduced pressure by, for example, the ISSG method, and a silicon oxide film having a thickness of, for example, 2 nm is formed on the inner wall of the element isolation trench 56 as a liner film. The processing conditions are, for example, a temperature of 810 ° C. and a time of 12 seconds.

  Next, a silicon oxide film having a film thickness of, for example, 500 nm is deposited by, for example, high-density plasma CVD, and the element isolation trench 56 is filled with the silicon oxide film.

  Next, the silicon oxide film on the silicon nitride film 54 is removed by, eg, CMP. Thus, the element isolation insulating film 58 is formed from the silicon oxide film embedded in the element isolation trench 56 by the so-called STI (Shallow Trench Isolation) method (FIG. 10).

  Next, using the silicon nitride film 54 as a mask, the element isolation insulating film 58 is etched by, for example, about 30 nm by wet etching using, for example, a hydrofluoric acid aqueous solution. This etching is for adjusting the height of the surface of the silicon layer 48 and the height of the surface of the element isolation insulating film 58 in the completed transistor.

  Next, the silicon nitride film 54 is removed by wet etching using, for example, hot phosphoric acid (FIG. 11).

  Next, the silicon oxide film 52 is removed by wet etching using, for example, a hydrofluoric acid aqueous solution. At this time, in order to completely remove the silicon oxide film 52, the silicon oxide film 52 having a film thickness of 3 nm is etched by a thermal oxide film corresponding to 5 nm.

  The silicon oxide film of the element isolation insulating film 58 is a film deposited by a high density plasma CVD method, and the etching rate for the hydrofluoric acid aqueous solution is about twice that of the thermal oxide film. If ions are implanted into the silicon oxide film, the etching rate further increases although it depends on the ion species. Although an etching rate can be reduced by performing a high-temperature heat treatment, it is not preferable for realizing a steep channel impurity distribution.

  In this embodiment, since impurities are not ion-implanted into the silicon oxide film forming the element isolation insulating film 58, the sinking amount of the element isolation insulating film 58 accompanying the etching of the silicon oxide film 52 is suppressed to 10 nm. Can do.

  Next, a silicon oxide film 60 of, eg, a 7 nm-thickness is formed by thermal oxidation (FIG. 12). The processing conditions are, for example, a temperature of 750 ° C. and a time of 52 minutes.

  Next, a photolithography is performed to form a photoresist film 62 that covers the high-voltage NMOS transistor formation region 32 and the high-voltage PMOS transistor formation region 40 and exposes other regions.

  Next, the silicon oxide film 60 is etched using the photoresist film 62 as a mask, for example, by wet etching using a hydrofluoric acid aqueous solution. Thus, the silicon oxide film 60 in the low voltage NOS transistor formation region 16 and the low voltage PMOS transistor formation region 24 is removed (FIG. 13). At this time, in order to completely remove the silicon oxide film 60, the silicon oxide film 60 having a thickness of 7 nm is etched with a thermal oxide film corresponding to 10 nm.

  The silicon oxide film of the element isolation insulating film 58 is a film deposited by a high density plasma CVD method, and the etching rate for the hydrofluoric acid aqueous solution is about twice that of the thermal oxide film. If ions are implanted into the silicon oxide film, the etching rate further increases although it depends on the ion species. Although an etching rate can be reduced by performing a high-temperature heat treatment, it is not preferable for realizing a steep channel impurity distribution.

  In the present embodiment, since impurities are not ion-implanted into the silicon oxide film forming the element isolation insulating film 58, the sinking amount of the element isolation insulating film 58 accompanying the etching of the silicon oxide film 60 should be kept as small as 20 nm. Can do.

  As a result, the total amount of sinking of the element isolation insulating film 58 when the silicon oxide films 52 and 60 are removed is about 10 nm in the high voltage transistor formation regions 32 and 40 and about 30 nm in the low voltage transistor formation regions 16 and 24. And can be kept small.

  Next, the photoresist film 62 is removed by, for example, ashing.

  Next, a silicon oxide film 64 of, eg, a 2 nm-thickness is formed by thermal oxidation. The processing conditions are, for example, a temperature of 810 ° C. and a time of 8 seconds.

  Next, in a NO atmosphere, for example, heat treatment is performed at 870 ° C. for 13 seconds to introduce nitrogen into the silicon oxide films 60 and 64.

  Thus, the gate insulating film 60a of the silicon oxide film 60 is formed in the high voltage NMOS transistor formation region 32 and the high voltage PMOS transistor formation region 32. Further, a gate insulating film 64a of a silicon oxide film 64 thinner than the silicon oxide film 60 is formed in the low voltage NMOS transistor formation region 16 and the low voltage PMOS transistor formation region 24 (FIG. 14).

  Next, a non-doped polysilicon film of, eg, a 100 nm-thickness is deposited on the entire surface by, eg, LPCVD. The processing conditions are, for example, a temperature of 605 ° C.

  Next, the polysilicon film is patterned by photolithography and dry etching, and a gate electrode 66 is formed in each transistor formation region (FIG. 15).

Next, by photolithography and ion implantation, N-type impurities are selectively ion-implanted into the high-voltage NMOS transistor formation region 32 using the gate electrode 66 as a mask to form an N-type impurity layer 68 that becomes an LDD region. For example, phosphorus ions are ion-implanted under the conditions of an acceleration energy of 35 keV and a dose of 2 × 10 ¹³ cm ⁻² to form the N-type impurity layer 68.

Next, by photolithography and ion implantation, P-type impurities are selectively ion-implanted into the high-voltage PMOS transistor formation region 40 using the gate electrode 66 as a mask to form a P-type impurity layer 70 to be an LDD region. For example, boron ions are ion-implanted under the conditions of an acceleration energy of 10 keV and a dose of 2 × 10 ¹³ cm ⁻² to form the P-type impurity layer 70.

Next, by photolithography and ion implantation, N-type impurities are selectively ion-implanted into the low-voltage NMOS transistor formation region 16 using the gate electrode 66 as a mask to form an N-type impurity layer 72 serving as an extension region. For example, arsenic ions are ion-implanted under the conditions of an acceleration energy of 6 keV and a dose of 2 × 10 ¹⁴ cm ⁻² to form the N-type impurity layer 72.

Next, by photolithography and ion implantation, ions are selectively implanted into the low voltage PMOS transistor formation region 24 using the gate electrode 66 as a mask to form a P-type impurity layer 74 serving as an extension region (FIG. 16). For example, boron ions are ion-implanted under the conditions of an acceleration energy of 0.6 keV and a dose of 7 × 10 ¹⁴ cm ⁻² to form the P-type impurity layer 74.

  Next, a silicon oxide film of, eg, a 80 nm-thickness is deposited on the entire surface by, eg, CVD. The processing conditions are, for example, a temperature of 520 ° C.

  Next, the silicon oxide film deposited on the entire surface is anisotropically etched to selectively remain on the side wall portion of the gate electrode 66. Thereby, sidewall spacers 76 of silicon oxide film are formed (FIG. 17).

Next, ions are selectively implanted into the low voltage NMOS transistor formation region 16 and the high voltage NMOS transistor formation region 32 by photolithography and ion implantation using the gate electrode 66 and the sidewall spacer 76 as a mask. Thereby, an N-type impurity layer 78 to be a source / drain region is formed, and an N-type impurity is added to the gate electrode 66 of the NMOS transistor. As ion implantation conditions, for example, phosphorus ions are set to have an acceleration energy of 8 keV and a dose of 1.2 × 10 ¹⁶ cm ⁻² .

Next, ions are selectively implanted into the low-voltage PMOS transistor formation region 24 and the high-voltage PMOS transistor formation region 40 by photolithography and ion implantation using the gate electrode 66 and the sidewall spacer 76 as a mask. Thereby, a P-type impurity layer 80 to be a source / drain region is formed, and a P-type impurity is added to the gate electrode 66 of the PMOS transistor. As ion implantation conditions, for example, boron ions are set to have an acceleration energy of 4 keV and a dose of 6 × 10 ¹⁵ cm ⁻² .

  Next, short-time heat treatment is performed in an inert gas atmosphere at 1025 ° C. for 0 second, for example, to activate the implanted impurities and diffuse the gate electrode 66. A short-time heat treatment at 1025 ° C. for 0 second is sufficient to diffuse the impurities to the interface between the gate electrode 66 and the gate insulating film.

  The channel portion of the low-voltage NMOS transistor can maintain a steep impurity distribution by suppressing diffusion of boron by carbon, and the channel portion of the low-voltage PMOS transistor can be diffused slowly by arsenic. On the other hand, diffusion is not suppressed in the channel portion of the high-voltage NMOS transistor because carbon is not introduced, and phosphorus having a diffusion constant larger than that of arsenic is introduced in the channel portion of the high-voltage PMOS transistor. Impurity distribution can be formed.

  Thus, four types of transistors are completed on the silicon substrate 10. That is, a low voltage NMOS transistor (LV NMOS) is formed in the low voltage NMOS transistor formation region 16. Further, a low voltage PMOS transistor (LV PMOS) is formed in the low voltage PMOS transistor formation region 24. Further, a high voltage NMOS transistor (HV NMOS) is formed in the high voltage NMOS transistor formation region. Further, a high voltage PMOS transistor (HV PMOS) is formed in the high voltage PMOS transistor formation region (FIG. 18).

  Next, a metal silicide film 84, for example, a cobalt silicide film is formed on the gate electrode 66, the N-type impurity layer 78, and the P-type impurity layer 80 by a salicide process.

  Next, a silicon nitride film of, eg, a 50 nm-thickness is deposited on the entire surface by, eg, CVD, to form a silicon nitride film as an etching stopper film.

  Next, a silicon oxide film of, eg, a 500 nm-thickness is deposited on the silicon nitride film by, eg, high density plasma CVD.

  Thereby, an interlayer insulating film 86 of a laminated film of a silicon nitride film and a silicon oxide film is formed.

  Next, the surface of the interlayer insulating film 86 is polished and planarized by, eg, CMP.

  Thereafter, contact plugs 88 embedded in the interlayer insulating film 86, wirings 90 connected to the contact plugs 88, and the like are formed to complete the semiconductor device (FIG. 19).

  Thus, according to the present embodiment, the high-concentration impurity layer 22 of the low-voltage NMOS transistor is formed of an impurity layer containing boron and carbon, and the high-concentration impurity layer 30 of the low-voltage PMOS transistor is formed of an impurity layer containing arsenic. Therefore, a steep impurity distribution can be realized. On the other hand, since the impurity layer 38 of the high voltage NMOS transistor is formed of an impurity layer containing boron and the impurity layer 46 of the high voltage PMOS transistor is formed of an impurity layer containing phosphorus, a gentle impurity distribution can be realized. As a result, a highly reliable low voltage transistor with a stable threshold voltage can be realized, and a high voltage transistor with high junction breakdown voltage and high hot carrier resistance can be realized.

  In addition, since the element isolation insulating film is formed after the well and channel impurity layers are formed, it is possible to prevent high-concentration channel impurities from being introduced into the element isolation insulating film, and to isolate the element isolation in the etching process. The film loss of the film can be greatly suppressed. As a result, the flatness of the substrate surface is improved and the generation of a parasitic transistor channel can be prevented, and a highly reliable semiconductor device with high performance can be realized.

[Second Embodiment]
A method for fabricating a semiconductor device according to the second embodiment will be described with reference to FIGS. The same components as those of the semiconductor device and the manufacturing method thereof according to the first embodiment shown in FIGS. 1 to 19 are denoted by the same reference numerals, and description thereof will be omitted or simplified.

  20 to 23 are process cross-sectional views illustrating a method of manufacturing a semiconductor device according to this reference example.

  In the manufacturing method of the semiconductor device according to the first embodiment, the amount of sinking of the element isolation insulating film 58 due to etching is about 10 nm in the high voltage transistor formation regions 32 and 40 and about 30 nm in the low voltage transistor formation regions 16 and 24. I was able to keep it small. However, compared with the high voltage transistor formation regions 32 and 40, the sinking amount of the element isolation insulating film 58 in the low voltage transistor formation regions 16 and 24 is large.

  In the present embodiment, a method for further suppressing the sinking amount of the element isolation insulating film 58 in the low voltage transistor formation regions 16 and 24 will be described.

  First, an element isolation insulating film 58 that defines an active region is formed in the same manner as in the semiconductor device manufacturing method according to the first embodiment shown in FIGS. A silicon oxide film 52 having a thickness of about 3 nm remains on the surface of the active region (FIG. 20).

  Next, a photoresist film 92 is formed by photolithography so as to cover the low voltage NMOS transistor formation region 16 and the low voltage PMOS transistor formation region 24 and expose the high voltage NMOS transistor formation region 32 and the high voltage PMOS transistor formation region 40.

  Next, the silicon oxide film 52 is etched using the photoresist film 92 as a mask, for example, by wet etching using a hydrofluoric acid aqueous solution. As a result, the silicon oxide film 52 in the high-voltage NMOS transistor formation region 32 and the high-voltage PMOS transistor formation region 40 is removed (FIG. 21).

  At this time, in order to completely remove the silicon oxide film 52, the silicon oxide film 52 having a film thickness of 3 nm is etched by a thermal oxide film corresponding to 5 nm.

  The silicon oxide film of the element isolation insulating film 58 is a film deposited by a high density plasma CVD method, and the etching rate for the hydrofluoric acid aqueous solution is about twice that of the thermal oxide film. If ions are implanted into the silicon oxide film, the etching rate further increases although it depends on the ion species. Although an etching rate can be reduced by performing a high-temperature heat treatment, it is not preferable for realizing a steep channel impurity distribution.

  In this embodiment, since impurities are not ion-implanted into the silicon oxide film forming the element isolation insulating film 58, the element isolation insulating film 58 in the high-voltage transistor formation regions 32 and 40 sinks as the silicon oxide film 52 is etched. The amount of entrainment can be kept as small as 10 nm. On the other hand, since the low voltage transistor formation regions 16 and 24 are covered with the photoresist film 92, the element isolation insulating film 58 in the low voltage transistor formation regions 16 and 24 is not etched.

  Next, the photoresist film 92 is removed by, for example, ashing.

  Next, a silicon oxide film 60 of, eg, a 7 nm-thickness is formed by thermal oxidation (FIG. 22). The processing conditions are, for example, a temperature of 750 ° C. and a time of 52 minutes.

  At this time, the silicon oxide film 52 remaining in the low voltage transistor formation regions 16 and 24 is also additionally oxidized, and the film thickness becomes about 8 nm.

  Next, a photoresist film 62 is formed by photolithography to cover the high voltage NMOS transistor formation region 32 and the high voltage PMOS transistor formation region 40 and expose the low voltage NMOS transistor formation region 16 and the low voltage PMOS transistor formation region 24.

  Next, the silicon oxide film 60 is etched using the photoresist film 62 as a mask, for example, by wet etching using a hydrofluoric acid aqueous solution. Thereby, the silicon oxide film 60 in the low voltage NOS transistor formation region 16 and the low voltage PMOS transistor formation region 24 is removed (FIG. 23). At this time, in order to completely remove the silicon oxide film 52, the silicon oxide film 52 having a thickness of 8 nm is etched by a thermal oxide film corresponding to 11 nm.

  The silicon oxide film of the element isolation insulating film 58 is a film deposited by a high density plasma CVD method, and the etching rate for the hydrofluoric acid aqueous solution is about twice that of the thermal oxide film. If ions are implanted into the silicon oxide film, the etching rate further increases although it depends on the ion species. Although an etching rate can be reduced by performing a high-temperature heat treatment, it is not preferable for realizing a steep channel impurity distribution.

  In this embodiment, since impurities are not ion-implanted into the silicon oxide film forming the element isolation insulating film 58, the sinking amount of the element isolation insulating film 58 accompanying the etching of the silicon oxide film 52 should be kept as small as 22 nm. Can do.

  As a result, the total amount of sinking of the element isolation insulating film 58 when the silicon oxide films 52 and 60 are removed is about 10 nm in the high voltage transistor formation regions 32 and 40 and about 22 nm in the low voltage transistor formation regions 16 and 24. And can be kept small.

  Compared with the manufacturing method of the semiconductor device according to the first embodiment, the sinking amount of the element isolation insulating film 58 in the low-voltage transistor formation regions 16 and 24 can be improved by about 25%.

  Thereafter, the semiconductor device is completed in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment shown in FIGS.

  As described above, according to this embodiment, the insulating film formed in the high voltage transistor formation region is selectively removed before forming the gate insulating film of the high voltage transistor. The reduction of the element isolation insulating film can be greatly suppressed. Thereby, the flatness of the substrate surface is improved, and a highly reliable semiconductor device with high performance can be realized.

[First Reference Example]
A method of manufacturing a semiconductor device according to the first reference example will be described with reference to FIGS. The same components as those in the semiconductor device and the manufacturing method thereof according to the first and second embodiments shown in FIGS. 1 to 23 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  24 to 26 are process cross-sectional views illustrating a method of manufacturing a semiconductor device according to this reference example.

  In this reference example, a process for performing channel ion implantation of the P-type high concentration impurity layer 22 and the N-type high concentration impurity layer 30 after the formation of the element isolation insulating film 58 will be described.

  First, the element isolation insulating film 58 is formed on the silicon substrate 10 by the STI method.

  Next, a silicon oxide film 14 as a protective oxide film is formed on the active region defined by the element isolation insulating film 58 (FIG. 24A).

  Next, a P-type high concentration impurity layer 22 is formed in the low voltage NMOS transistor formation region 16 by photolithography and ion implantation.

  Next, an N-type high concentration impurity layer 30 is formed in the low voltage PMOS transistor formation region 24 by photolithography and ion implantation.

  Next, a P-type impurity layer 38 is formed in the high-voltage NMOS transistor formation region 32 by photolithography and ion implantation.

  Next, an N-type impurity layer 46 is formed in the high-voltage PMOS transistor formation region 40 by photolithography and ion implantation (FIG. 24B).

  Next, heat treatment is performed to recover the ion implantation damage and activate the implanted impurities.

  Next, the silicon oxide film 14 is removed by wet etching using a hydrofluoric acid aqueous solution, and the silicon substrate 10 in the active region is exposed.

  At this time, since the high-concentration impurities are introduced into the element isolation insulating film 58 by ion implantation when forming the P-type high-concentration impurity layer 22 and the N-type high-concentration impurity layer 30, Etching is accelerated. In particular, when arsenic is ion-implanted for forming the N-type impurity layer 30 for the purpose of obtaining a steep impurity profile, the increase in the etching rate in the low-voltage PMOS transistor formation region 24 is significant.

  As a result, in the low voltage NMOS transistor formation region 16 and the low voltage PMOS transistor formation region 24, the element isolation insulating film 58 is excessively etched when the silicon oxide film 14 is etched, and the side portion of the active region is exposed. .

  The P-type impurity layer 38 and the N-type impurity layer 46 have an impurity concentration that is one digit lower than the P-type high-concentration impurity layer 22 and the N-type high-concentration impurity layer 30. For this reason, the etching amount of the element isolation insulating film 58 in the high voltage NMOS transistor formation region 32 and the high voltage PMOS transistor formation region 40 is relatively small.

  Next, a non-doped silicon layer 48 is epitaxially grown on the silicon substrate 10 (FIG. 25A). At this time, since the growth of the silicon layer 48 proceeds from the surface and side surfaces of the active region, crystal defects are introduced into the overlapping portions of the silicon layers formed along different plane orientations, that is, the end portions of the element isolation insulating film 58. It will be done.

  Crystal defects introduced into the silicon layer 48 are not preferable because they greatly affect transistor characteristics such as an increase in leakage current.

  Next, a silicon oxide film 60 to be a gate insulating film 60a for the high voltage NMOS transistor and the high voltage PMOS transistor is formed on the active region (FIG. 25B).

  Next, the silicon oxide film 60 in the low voltage NMOS transistor formation region 16 and the low voltage PMOS transistor formation region 24 is selectively removed by photolithography and wet etching (FIG. 26A).

  At this time, the element isolation insulating film 58 is also etched together with the etching of the silicon oxide film 60, and in the low voltage NMOS transistor formation region 16 and the low voltage PMOS transistor formation region 24, the lower surface of the silicon layer 48 at the end of the element isolation insulating film 58 Is exposed.

  Next, a silicon oxide film 64 to be a gate insulating film 64a is formed on the active regions of the low voltage NMOS transistor region 16 and the low voltage PMOS transistor region 24 (FIG. 26B).

  Thereafter, when the gate electrode 66 is formed on the gate insulating film 64a, a parasitic transistor channel facing the gate electrode 66 without the silicon layer 48 interposed therebetween is provided below the silicon layer 48 at the end of the element isolation insulating film 58. Will be formed. If the silicon layer 48 is epitaxially grown after the element isolation insulating film 58 is formed and then two or more types of gate insulating films having different film thicknesses are formed, the formation of this parasitic transistor channel is inevitable.

  Further, the reduction of the element isolation insulating film 58 also occurs in the subsequent etching process. When the element isolation insulating film 58 is reduced in film thickness, the flatness of the substrate surface is lowered, which may cause a problem in a subsequent process.

[Second Reference Example]
A method of manufacturing a semiconductor device according to the second reference example will be described with reference to FIGS. The same components as those in the semiconductor device and the manufacturing method thereof according to the first and second embodiments shown in FIGS. 1 to 23 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  27 to 32 are process cross-sectional views illustrating a method of manufacturing a semiconductor device according to this reference example.

  In this reference example, a process for forming the element isolation insulating film 58 after the formation of the P-type high concentration impurity layer 22 and the N-type high concentration impurity layer 30 will be described.

  First, grooves 12 used as marks for mask alignment are formed outside the product formation region of the silicon substrate 10 by photolithography and etching.

  Next, a silicon oxide film 14 is formed on the entire surface of the silicon substrate 10 as a protective film on the surface of the silicon substrate 10 (FIG. 27A).

Next, the P well 20 and the P type high concentration impurity layer 22 are formed in the low voltage NMOS transistor formation region 16 and the high voltage NMOS transistor formation region 32 by photolithography and ion implantation. The P well 20 and the P-type high concentration impurity layer 22 are formed by, for example, double ion implantation of boron or boron fluoride (BF ₂ ).

  Next, the N well 28 and the N type high concentration impurity layer 30 are formed in the low voltage PMOS transistor formation region 24 and the high voltage PMOS transistor formation region 40 by photolithography and ion implantation (FIG. 27B). The N well 28 and the N-type high concentration impurity layer 30 are formed by, for example, double ion implantation of phosphorus, arsenic, or antimony (Sb).

  Next, heat treatment is performed to recover the ion implantation damage and activate the implanted impurities.

  Next, the silicon oxide film 14 is removed by wet etching using a hydrofluoric acid aqueous solution.

  Next, a non-doped silicon layer 48 is epitaxially grown on the silicon substrate 10 (FIG. 28A).

  Next, an element isolation insulating film 58 is formed on the silicon substrate 10 and the silicon layer 48 by the STI method (FIG. 28B).

  Next, a silicon oxide film 60 to be a gate insulating film 60a for the high voltage NMOS transistor and the high voltage PMOS transistor is formed on the active region (FIG. 29A).

  Next, the silicon oxide film 60 in the low voltage NMOS transistor formation region 16 and the low voltage PMOS transistor formation region 24 is selectively removed by photolithography and wet etching (FIG. 29B).

  Next, a silicon oxide film 64 to be a gate insulating film 64a is formed on the active regions of the low voltage NMOS transistor region 16 and the low voltage PMOS transistor region 24 (FIG. 30A).

  Next, a polysilicon film 66a is formed on the entire surface.

  Next, an N-type impurity is added to the polysilicon film 66a in the low-voltage NMOS transistor region 16 and the high-voltage NMOS transistor formation region 32 by photolithography and ion implantation. Further, a P-type impurity is added to the polysilicon film 66a in the low-voltage PMOS transistor region 24 and the high-voltage PMOS transistor formation region 40 (FIG. 30B).

  Next, the polysilicon film 66a is patterned to form a gate electrode 66 in each transistor formation region.

  Next, an N-type impurity layer 72 serving as an extension region is formed in the low voltage NMOS transistor region 16 by photolithography and ion implantation. Further, a P-type impurity layer 74 serving as an extension region is formed in the low voltage PMOS transistor region 24. Further, an N-type impurity layer 68 to be an LDD region is formed in the high voltage NMOS transistor formation region 32. Further, a P-type impurity layer 70 to be an LDD region is formed in the high voltage PMOS transistor formation region 40 (FIG. 31A).

  Next, a silicon oxide film is deposited and anisotropically etched to form sidewall spacers 68 on the sidewall portions of the gate electrode 66 (FIG. 31B).

  Next, an N-type impurity layer 78 to be a source / drain region is formed in the low voltage NMOS transistor region 16 and the high voltage NMOS transistor formation region 32 by photolithography and ion implantation. Further, a P-type impurity layer 80 to be a source / drain region is formed in the low voltage PMOS transistor region 24 and the high voltage PMOS transistor formation region 40 (FIG. 32).

  Next, heat treatment is performed to activate the implanted impurities.

  Thus, a low voltage NMOS transistor, a low voltage PMOS transistor, a high voltage NMOS transistor, and a high voltage PMOS transistor are formed on the silicon substrate 10.

  In this reference example, the well of the low voltage transistor (including the channel impurity layer) and the well of the high voltage transistor (including the channel impurity layer) are formed at the same time. However, a steep impurity distribution is required for the channel impurity layer of the low-voltage transistor, while the channel impurity layer layer of the high-voltage transistor does not require a steep impurity distribution. Rather, it is not preferable because it causes a decrease in junction breakdown voltage and a decrease in hot carrier resistance due to a steep distribution. From this point of view, it is desirable to form the well of the low voltage transistor and the well of the high voltage transistor separately.

[Modified Embodiment]
The present invention is not limited to the above embodiment, and various modifications are possible.

  For example, in the above embodiment, germanium is ion-implanted for amorphization when forming the P-type high-concentration impurity layer 22, but the ion species used for the amorphization is limited to this. It is not something. For example, silicon, nitrogen, argon, xenon, or the like may be used.

  In the above embodiment, a silicon substrate is used as the underlying semiconductor substrate. However, the underlying semiconductor substrate is not necessarily a bulk silicon substrate. Other semiconductor substrates such as an SOI substrate may be applied.

  Moreover, in the said embodiment, although the silicon layer was used as an epitaxial semiconductor layer, it does not necessarily need to be a silicon layer. Instead of the silicon layer, another semiconductor layer such as a SiGe layer or a SiC layer may be applied.

  In addition, the structure, constituent materials, manufacturing conditions, and the like of the semiconductor device described in the above embodiment are merely examples, and can be appropriately modified or changed according to technical common sense of those skilled in the art.

  Regarding the above embodiment, the following additional notes are disclosed.

(Additional remark 1) The process of ion-implanting the 1st conductivity type 1st impurity into the said 1st area | region using the 1st mask which exposes the 1st area | region of a semiconductor substrate,
Using the second mask exposing the second region of the semiconductor substrate, the second impurity of the first conductivity type having a smaller diffusion constant than the first impurity in the second region; or Ion-implanting a first impurity and a third impurity that suppresses diffusion of the first impurity;
Activating the first impurity and the second impurity to form a first impurity layer in the first region and a second impurity layer in the second region;
Epitaxially growing a semiconductor layer on the semiconductor substrate on which the first impurity layer and the second impurity layer are formed;
Growing a first gate insulating film on the first region and the second region of the semiconductor layer;
Removing the first gate insulating film in the second region using a third mask exposing the second region;
Growing a second gate insulating film thinner than the first gate insulating film on the second region of the semiconductor layer;
Forming a first gate electrode on the first gate insulating film and forming a second gate electrode on the second gate insulating film, respectively.

(Additional remark 2) In the manufacturing method of the semiconductor device of Additional remark 1,
The first impurity is boron;
The method for manufacturing a semiconductor device, wherein the third impurity is carbon.

(Additional remark 3) In the manufacturing method of the semiconductor device of Additional remark 2,
Prior to the ion implantation of the first impurity and the third impurity, a fourth impurity for amorphizing the surface region of the semiconductor substrate is ion-implanted into the second region. A method for manufacturing a semiconductor device.

(Additional remark 4) In the manufacturing method of the semiconductor device of Additional remark 3,
The method for manufacturing a semiconductor device, wherein the fourth impurity is germanium.

(Additional remark 5) In the manufacturing method of the semiconductor device of Additional remark 1,
The first impurity is phosphorus;
The method of manufacturing a semiconductor device, wherein the second impurity is arsenic.

(Appendix 6) In the method for manufacturing a semiconductor device according to any one of appendices 1 to 4,
After the step of forming the semiconductor layer, the method further includes the step of forming an element isolation insulating film on the semiconductor substrate on which the semiconductor layer is formed.

(Appendix 7) In the method for manufacturing a semiconductor device according to any one of appendices 1 to 5,
In the step of growing the first gate insulating film, etching is performed using a third mask that exposes the first region, the surface of the semiconductor layer in the first region is exposed, and then the first region is exposed. A method for manufacturing a semiconductor device, comprising: growing a gate insulating film.

(Appendix 8) Ion implantation of a first impurity into the first region using a first mask exposing the first region of the semiconductor substrate;
Ion-implanting a second impurity having the same conductivity type as the first impurity into the second region using a second mask exposing the second region of the semiconductor substrate;
Ion-implanting a third impurity having a conductivity type opposite to that of the first impurity into the third region by using a third mask exposing the third region of the semiconductor substrate;
Ion-implanting a fourth impurity having a conductivity type opposite to the first impurity into the fourth region using a fourth mask exposing the fourth region of the semiconductor substrate;
The first impurity, the second impurity, the third impurity, and the fourth impurity are activated, a first impurity layer is formed in the first region, and a second impurity layer is formed in the second region. Forming a third impurity layer in the third region and a fourth impurity layer in the fourth region;
Epitaxially growing a semiconductor layer on the semiconductor substrate on which the first impurity layer, the second impurity layer, the third impurity layer, and the fourth impurity layer are formed;
Growing a first gate insulating film on the first region, on the second region, on the third region, and on the fourth region of the semiconductor layer;
Removing the first gate insulating film in the second region and the fourth region using a fifth mask exposing the second region and the fourth region;
Growing a second gate insulating film thinner than the first gate insulating film on the second region and the fourth region of the semiconductor layer;
A first gate electrode on the first gate insulating film in the first region, a second gate electrode on the second gate insulating film in the second region, and a third gate electrode on the third region. Forming a third gate electrode on the first gate insulating film and forming a fourth gate electrode on the second gate insulating film in the fourth region, respectively. A method for manufacturing a semiconductor device.

(Supplementary note 9) In the method for manufacturing a semiconductor device according to supplementary note 8,
The first impurity is boron;
The second impurity includes boron and carbon,
The third impurity is phosphorus;
The method of manufacturing a semiconductor device, wherein the fourth impurity is arsenic or antimony.

(Additional remark 10) In the manufacturing method of the semiconductor device of Additional remark 8 or 9,
In the step of ion-implanting the second impurity, a fifth impurity for amorphizing the surface region of the semiconductor substrate is ion-implanted prior to ion implantation of the second impurity. A method for manufacturing a semiconductor device.

(Additional remark 11) In the manufacturing method of the semiconductor device of Additional remark 10,
The fifth impurity is germanium. A method of manufacturing a semiconductor device, wherein the fifth impurity is germanium.

(Appendix 12) In the method for manufacturing a semiconductor device according to any one of appendices 8 to 11,
After the step of forming the semiconductor layer, the method further includes the step of forming an element isolation insulating film on the semiconductor substrate on which the semiconductor layer is formed.

(Supplementary note 13) In the method for manufacturing a semiconductor device according to any one of supplementary notes 8 to 12,
In the step of growing the first gate insulating film, etching is performed using a sixth mask exposing the first region and the third region, and the first region and the third region are etched. After the surface of the semiconductor layer is exposed, the first gate insulating film is grown. A method for manufacturing a semiconductor device, comprising:

(Supplementary Note 14) A first impurity layer formed in a first region of a semiconductor substrate and containing boron;
A first epitaxial semiconductor layer formed on the first impurity layer;
A first gate insulating film formed on the first epitaxial semiconductor layer;
A first gate electrode formed on the first gate insulating film;
A first transistor having the first epitaxial semiconductor layer and a first source / drain region formed in the semiconductor substrate of the first region;
A third impurity layer formed in the second region of the semiconductor substrate and containing boron and carbon;
A second epitaxial semiconductor layer formed on the second impurity layer;
A second gate insulating film formed on the second epitaxial semiconductor layer and thinner than the first gate insulating film;
A second gate electrode formed on the second gate insulating film;
A second transistor having the second epitaxial semiconductor layer and a second source / drain region formed in the semiconductor substrate of the second region;
A third impurity layer formed in a third region of the semiconductor substrate and containing phosphorus;
A third epitaxial semiconductor layer formed on the third impurity layer;
A third gate insulating film formed on the third epitaxial semiconductor layer and having the same thickness as the first gate insulating film;
A third gate electrode formed on the third gate insulating film;
A third transistor having the third epitaxial semiconductor layer and a third source / drain region formed in the semiconductor substrate of the third region;
A third impurity layer formed in a fourth region of the semiconductor substrate and containing arsenic or antimony;
A fourth epitaxial semiconductor layer formed on the fourth impurity layer;
A fourth gate insulating film formed on the fourth epitaxial semiconductor layer and having the same thickness as the second gate insulating film;
A fourth gate electrode formed on the fourth gate insulating film;
And a fourth transistor having the fourth epitaxial semiconductor layer and a fourth source / drain region formed in the semiconductor substrate of the fourth region.

(Supplementary Note 15) In the semiconductor device according to Supplementary Note 14,
The semiconductor device, wherein the second impurity layer contains germanium.

DESCRIPTION OF SYMBOLS 10 ... Silicon substrate 12 ... Groove 14, 52, 60, 64 ... Silicon oxide film 16 ... Low-voltage NMOS transistor formation area 18, 26, 34, 42, 50, 62 ... Photoresist film 20, 36 ... P well 22 ... P High-concentration impurity layer 24... Low-voltage PMOS transistor formation regions 28 and 44 N-well 30 N-type high-concentration impurity layer 32 High-voltage NMOS transistor formation regions 38 70 and 74 P-type impurity layer 40 High-voltage PMOS Transistor forming regions 46, 68, 72 ... N-type impurity layer 48 ... Silicon layer 54 ... Silicon nitride film 56 ... Element isolation trench 58 ... Element isolation insulating film 60a, 64a ... Gate insulating film 66a ... Polysilicon film 66 ... Gate electrode 76 ... Sidewall spacer 78 ... N-type impurity layer (source / drain region)
80... P-type impurity layer (source / drain region)
84 ... Metal silicide film 86 ... Interlayer insulating film 88 ... Contact plug 90 ... Wiring 100 ... Silicon substrate 102 ... Source region 104 ... Drain region 106 ... Channel region 108 ... High concentration impurity layer 110 ... Silicon layer 112 ... Gate insulating film 114 ... Gate electrode

Claims (7)

A semiconductor substrate having a first region and a second region;
A first impurity layer formed in the first region of the semiconductor substrate and having a first impurity of a first conductivity type;
A first semiconductor layer formed on the first impurity layer;
A first gate insulating film formed on the first semiconductor layer;
A first gate electrode formed on the first gate insulating film;
A first source / drain region formed in the semiconductor substrate of the first semiconductor layer and the first region;
Said formed on the second region of the semiconductor substrate, the second impurity layer having a second impurity of a small first conductivity type diffusion constant than the first impurity,
A second semiconductor layer formed on the second impurity layer;
A second gate insulating film formed on the second semiconductor layer and thinner than the first gate insulating film;
A second gate electrode formed on the second gate insulating film;
A second source / drain region formed in the semiconductor substrate of the second semiconductor layer and the second region;
I have a,
The impurity concentration of the first impurity in the first semiconductor layer is lower than the impurity concentration of the first impurity in the first impurity layer,
The semiconductor device according to claim 1, wherein an impurity concentration of the second impurity in the second semiconductor layer is lower than an impurity concentration of the second impurity in the second impurity layer . A semiconductor substrate having a first region and a second region;
A first impurity layer formed in the first region of the semiconductor substrate and having a first impurity of a first conductivity type;
A first semiconductor layer formed on the first impurity layer;
A first gate insulating film formed on the first semiconductor layer;
A first gate electrode formed on the first gate insulating film;
A first source / drain region formed in the semiconductor substrate of the first semiconductor layer and the first region;
A second impurity layer formed in the second region of the semiconductor substrate and having a third impurity for suppressing diffusion of the first impurity and the first impurity;
A second semiconductor layer formed on the second impurity layer;
A second gate insulating film formed on the second semiconductor layer and thinner than the first gate insulating film;
A second gate electrode formed on the second gate insulating film;
A second source / drain region formed in the semiconductor substrate of the second semiconductor layer and the second region;
A semiconductor device comprising: The second impurity layer has the second impurity;
The first impurity is phosphorus;
The semiconductor device according to claim 1 , wherein the second impurity is arsenic or antimony. The second impurity layer includes the first impurity and the third impurity;
The impurity concentration of the first impurity in the first semiconductor layer is lower than the impurity concentration of the first impurity in the first impurity layer,
The impurity concentration of said first impurity of the second semiconductor layer, the semiconductor device according to claim 2, wherein the lower than the impurity concentration of said second impurity of the second impurity layer. The second impurity layer includes the first impurity and the third impurity;
The first impurity is boron;
The semiconductor device according to claim 2, wherein the third impurity is carbon. The semiconductor device according to claim 5, wherein the second impurity layer contains germanium. A first well of the first conductivity type formed in a first region of the semiconductor substrate and located under the first impurity layer;
A first well of the second conductivity type formed in a second region of the semiconductor substrate and located under the second impurity layer;
Have
The impurity concentration of the first impurity layer is higher than the impurity concentration of the first well and the impurity concentration of the first semiconductor layer,
7. The impurity concentration of the second impurity layer is higher than the impurity concentration of the second well and the impurity concentration of the second semiconductor layer. 7. Semiconductor device.

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