JP5514726B2 - Junction type semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a junction type semiconductor device and a manufacturing method thereof, and in particular, a junction suitable for suppressing recombination between a main current flowing between main electrodes and a control current flowing through a control electrode and increasing a current amplification factor. The present invention relates to a type semiconductor device and a method for manufacturing the same.

  Silicon carbide (Silicon Carbide, hereinafter referred to as “SiC”) has a characteristic that it has a larger band gap energy than silicon that is widely applied to semiconductor devices. Therefore, a semiconductor device using SiC is suitable for high voltage, high power, and high temperature operation conditions, and is expected to be applied to power devices and the like. The structures of SiC power devices currently being researched and developed are mainly classified into two types, “MOS type” and “junction type”.

  Here, it demonstrates from a viewpoint of the performance improvement of a junction type SiC power device. The junction type SiC power device includes a static induction transistor (hereinafter referred to as “SIT”), a junction field effect transistor (hereinafter referred to as “JFET”), or bipolar. There are junction transistors (Bipolar Junction Transistor, hereinafter referred to as “BJT”). In the following, SIT, JFET, and BJT are collectively referred to as “junction transistors”.

As an example of a conventional SIT, for example, one having a structure disclosed in Patent Document 1 is known. The SIT disclosed in Patent Document 1 includes an n ⁺ type first high resistance layer, a p type channel doped layer, an n ⁺ type 4H-SiC (0001) surface substrate serving as a drain region from the bottom side. ^A- type second high resistance layer and an n ⁺ type source region are stacked in this order. In the SIT, the source region is separated and formed by etching in a predetermined planar pattern shape from the top surface to the source region and the middle of the second high resistance layer in the stacked structure. The SIT has a plurality of source regions separated on the upper surface based on a predetermined pattern shape. In the region between the plurality of separated source regions, an Al ion implantation process is subsequently performed to form a p-type gate region. Accordingly, each of the plurality of separated source regions is surrounded by the gate region when viewed in the planar shape of the SIT. The SIT disclosed in Patent Document 1 has a structure in which the SiC surface in the SIT is covered with a surface recombination suppressing semiconductor layer between the source region and the gate region. This surface recombination suppressing semiconductor layer has a function of suppressing recombination of electrons flowing out of the source region (n ⁺ type source region and n ⁻ type second high resistance layer) and holes flowing out of the gate region. doing. As a result, recombination of electrons from the source region and holes from the gate region is suppressed, and an improvement in the current amplification factor of the junction type semiconductor layer device is achieved.

Further, as an example of a conventional BJT, there is one having a structure described in Non-Patent Document 1, for example. The BJT is laminated on the low resistance n ⁺ type 4H-SiC (0001) plane 8 degree off substrate in the order of the n ⁻ type high resistance region, the p type base region, and the n ⁺ type emitter region from below. It is formed. The emitter region is composed of a number of elongated regions. In the emitter region, the base region (base contact region), and the collector region, electrodes for external electrical connection are formed.

  FIG. 13 shows a cross-sectional structure diagram of the BJT disclosed in Non-Patent Document 1. As shown in FIG. 13, the BJT 500 surrounds the collector region 501, which is an n-type low resistance layer, the n-type high resistance region 502, the base region 503 of the p-type region, the emitter region 504 of n-type low resistance, and the emitter region. The base contact region 505 of the p-type low resistance region is formed. A collector electrode 506, a base electrode 507, and an emitter electrode 508 for electrical connection are joined to the outside of the collector region 501, the base region 503 (base contact region 505), and the emitter region. Further, the entire exposed surface other than the electrodes of the BJT 500 is covered with a surface protective film 509.

JP 2006-269681 A

J. Zhang et al., “High Power (500V-70A) and High Gain (44-47) 4H-SiC Bipolar Junction Transistors” Materials Science Forum Vols. 457-460 (2004) pp. 1149-1152.

  In a junction transistor such as SIT or BJT, a control electrode called a gate or a base is formed by a pn junction. In order to pass a current between main electrodes such as between a source and a drain or between an emitter and a collector, it is necessary to pass a current through the control electrode. When the current flowing between the main electrodes is “main current Id” and the current flowing through the control electrode is “control current Ig”, the ratio of both currents (Id / Ig) is called “current amplification factor”. In the development of junction transistors, increasing the value of the current amplification factor is an important issue.

  As a factor for reducing the current amplification factor, recombination of holes flowing from the control electrode (carrier of the control current Ig) and electrons flowing between the main electrodes (carrier of the main current Id) can be mentioned. The value of the recombination current depends on the electron density, hole density, and recombination level density, and the higher the density, the larger the recombination current.

  The SiC surface is known as a site where recombination is likely to occur. In order to reduce the density of recombination levels on the SiC surface, various proposals have been made in the process of forming a protective film by oxidizing the SiC surface. This point is also described in Patent Document 1. Further, in Patent Document 1, in order to reduce the recombination probability, a surface recombination suppressing semiconductor layer composed of a p-type region having a low concentration is provided on the SiC surface. When such a surface recombination-inhibiting semiconductor layer is formed, a potential barrier against electrons is formed on the SiC surface, so that the electron density on the SiC surface can be lowered. Furthermore, the hole density can be kept low by forming a high resistance layer on the SiC surface in a p-type region having a low concentration. By forming such a surface recombination suppressing semiconductor layer, even if a recombination level exists on the SiC surface of the junction transistor, the recombination probability can be reduced and the current amplification factor of the junction transistor is increased. be able to.

  As described above, in the junction transistor, many attempts have been made to increase the current amplification factor by suppressing recombination on the SiC surface. However, it is known that the recombination probability of electrons and holes is high also in the p-type gate region of SIT and the p-type base contact region of BJT. However, in the development of a conventional junction transistor, there is no attempt to suppress recombination in this region.

  Here, the above problem will be described in terms of phenomena based on a structural example of SIT. In a typical SIT cross-sectional structure, the p-type gate region is formed by a high energy and high concentration Al ion implantation step and a subsequent activation heat treatment step. Since many defects are generated in the crystal by high energy and high concentration Al ion implantation, the crystallinity is restored by activation heat treatment. However, crystallinity cannot be completely recovered, and defects remain in the vicinity of the p-type gate region. The defect acts as a recombination center of electrons and holes, and causes a decrease in current amplification factor. In order to suppress the recombination, a method of increasing the distance between the gate region and the source region and keeping the electrons away can be considered. However, since this method is contrary to the design concept of miniaturizing the junction transistor, it is impossible to achieve both improvement of the current amplification factor and improvement of the current density by miniaturization.

  The above-mentioned problem relating to SIT is a problem that also occurs in BJT.

  The object of the present invention is to reduce the recombination probability of electrons and holes in the surrounding region such as the gate region of SIT or the base region of BJT, and between the main current flowing between the main electrodes and the control current flowing to the control electrode. It is an object of the present invention to provide a junction type semiconductor device and a method for manufacturing the same that can suppress recombination of the semiconductor layer, improve the current amplification factor, and improve the current density by miniaturization.

  A junction type semiconductor device according to the present invention includes a first main electrode region (a first region corresponding to one main electrode) which is a substrate made of a silicon carbide (SiC) semiconductor crystal, and one of the substrates. A second main electrode region formed on the side of the surface (a second region corresponding to the other main electrode), a high resistance layer formed between the first and second main electrode regions, A control electrode region (a region corresponding to the control electrode) formed around the two main electrode regions, and a recombination suppression region formed so as to cover at least the side surface of the control electrode region. Characterized.

  In the above junction type semiconductor device, according to SIT or BJT, the first main electrode region is a drain region or a collector region, and the second main electrode region is a source region or an emitter region. The region is a gate region or a base region. Since the recombination suppression region is provided so as to cover at least a predetermined range of the side surface of the control electrode region such as the gate region, for example, an electron is present in a region where many recombination levels exist in the manufacturing process of the junction type semiconductor device. Is provided, and electrons flowing from the source region or the like can be kept away from the recombination suppression region.

  In the above junction type semiconductor device, preferably, the high resistance layer has a channel dope layer in contact with the control electrode region, and the recombination suppression region is formed to a depth position where the channel dope layer is formed.

  Furthermore, the recombination suppression region can be formed so as to cover the side surface and the bottom surface of the control electrode region.

  In the above junction type semiconductor device, preferably, the first main electrode region is a drain region made of a first conductive type low resistance layer, and the second main electrode region is a first conductive type low resistance layer. A source region composed of a resistive layer, the control electrode region is a gate region of a second conductivity type, the recombination suppression region has the same second conductivity type as the gate region, and the resistivity of the recombination suppression region Is higher than the resistivity of the gate region, or the recombination suppression region has the same first conductivity type as the high resistance layer, and the resistivity of the recombination suppression region is higher than that of the high resistance layer.

  In the above junction type semiconductor device, preferably, the first main electrode region is a drain region composed of a low resistance layer of the second conductivity type, and the second main electrode region is a second conductivity type of low resistance. A source region composed of a resistance layer, the control electrode region is a gate region of the first conductivity type, the recombination suppression region has the same first conductivity type as the gate region, and the resistivity of the recombination suppression region Is higher than the resistivity of the gate region, or the recombination suppression region has the same second conductivity type as the high resistance layer, and the resistivity of the recombination suppression region is higher than that of the high resistance layer.

  In the above junction type semiconductor device, preferably, the first main electrode region is a collector region made of a first conductivity type low-resistance layer, and the second main electrode region is a first conductivity type low resistance layer. An emitter region composed of a resistance layer, the control electrode region is a second contact type base contact region, the recombination suppression region has the same second conductivity type as the base contact region, and the recombination suppression region The resistivity is higher than the resistivity of the base contact region, or the recombination suppression region has the same first conductivity type as the high resistance layer, and the recombination suppression region has a higher resistivity than the high resistance layer.

  In the above junction type semiconductor device, preferably, the first main electrode region is a collector region made of a low resistance layer of the second conductivity type, and the second main electrode region is a low conductivity type of the second conductivity type. An emitter region composed of a resistive layer, the control electrode region is a base contact region of the first conductivity type, the recombination suppression region has the same first conductivity type as the base contact region, The resistivity is higher than the resistivity of the base contact region, or the recombination suppression region has the same second conductivity type as the high resistance layer, and the recombination suppression region has a higher resistivity than the high resistance layer.

  A method for manufacturing a junction type semiconductor device according to the present invention includes a first step of forming a high resistance layer on a substrate made of a silicon carbide semiconductor crystal and serving as a first main electrode region, and a high resistance layer. A second step of forming a low-resistance layer serving as a second main electrode region on the first layer; a third step of forming a control electrode region by ion implantation in a predetermined region on the surface side of the high-resistance layer; And a fourth step of forming a recombination suppression region by ion implantation so as to cover at least the side surface of the control electrode region.

  A method for manufacturing a junction type semiconductor device according to the present invention includes a first step of forming a high resistance layer on a substrate made of a silicon carbide semiconductor crystal and serving as a first main electrode region, and a high resistance. A second step of forming a low resistance layer serving as a second main electrode region on the layer; and a third step of forming a recombination suppression region by ion implantation in a predetermined region on the surface side of the high resistance layer; The recombination suppression region includes a fourth step of forming a control electrode region by ion implantation from the surface side of the recombination suppression region.

  In the above method for manufacturing a junction type semiconductor device, preferably, the impurity concentration implanted to form the recombination suppression region is lower than the impurity concentration implanted to form the control electrode region. It is characterized by.

  In the manufacturing method of the junction type semiconductor device, preferably, a step for forming a channel dope layer in the high resistance layer is provided.

  In the method for manufacturing a junction semiconductor device, preferably, the substrate, the high resistance layer, and the low resistance layer are of a first conductivity type, and the control electrode region is of a second conductivity type. .

  In the method for manufacturing a junction semiconductor device, preferably, the substrate, the high resistance layer, and the low resistance layer are of the second conductivity type, and the control electrode region is of the first conductivity type. .

  In the manufacturing method of the junction type semiconductor device, preferably, the first main electrode, the second main electrode, and the control are provided in each of the first main electrode region, the second main electrode region, and the control electrode region. A step of forming an electrode; and a step of forming an upper layer electrode on the upper side of the second main electrode and the control electrode.

  According to the junction type semiconductor device according to the present invention, the recombination suppression region is provided in contact with the gate region or the base region of the SiC semiconductor device so as to cover at least a side surface of the SiC semiconductor device within a predetermined range. Can be suppressed, and the current amplification factor can be improved. Further, in the junction type semiconductor device, even if miniaturization is performed, the current density of the main current can be improved.

  According to the method for manufacturing a junction type semiconductor device according to the present invention, the recombination suppression region that is in contact with the gate region or the base region of the SiC semiconductor device and can cover at least a side surface thereof in a predetermined range is formed in the depth direction. Therefore, the junction type semiconductor device having a high current amplification factor can be manufactured easily and reliably by suppressing the recombination between the gate and the source as described above.

1 is a partial longitudinal sectional view of a junction type semiconductor device (SIT) according to a first embodiment of the present invention. 1 is a plan view of a part of a junction type semiconductor device (SIT) according to a first embodiment. It is a fragmentary longitudinal cross-section explaining the problem of operation | movement of the conventional junction type semiconductor device (SIT). It is a fragmentary longitudinal cross-section explaining operation | movement of the junction type semiconductor device (SIT) by 1st Example. It is a flowchart explaining the manufacturing method of the junction type semiconductor device (SIT) by 1st Example. It is a fragmentary longitudinal cross-section which shows the device structure corresponding to each process of the manufacturing method of the junction type semiconductor device (SIT) by 1st Example. It is a fragmentary longitudinal cross-section which shows the device structure corresponding to each process of the manufacturing method of the junction type semiconductor device (SIT) by 1st Example. It is a fragmentary longitudinal cross-sectional view for demonstrating the device structure corresponding to the characteristic process in the manufacturing method of the junction type semiconductor device (SIT) by 1st Example. It is a fragmentary longitudinal cross-sectional view for demonstrating the device structure corresponding to the other characteristic process in the manufacturing method of the junction type semiconductor device (SIT) by 1st Example. It is a partial longitudinal cross-sectional view of the junction type semiconductor device (SIT) by 2nd Example of this invention. It is a partial longitudinal cross-sectional view of the junction type semiconductor device (SIT) by 3rd Example of this invention. It is a fragmentary longitudinal cross-sectional view of the junction type semiconductor device (BJT) by 4th Example of this invention. It is a fragmentary longitudinal cross-sectional view of the junction type semiconductor device (BJT) by 5th Example of this invention. It is a fragmentary longitudinal cross-section explaining the structure of the conventional junction type semiconductor device (BJT).

  Several preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

<First embodiment>
A junction type semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a partial longitudinal sectional view showing a unit structure of a junction type semiconductor device according to the first embodiment, and FIG. 2 is a plan view of the junction type semiconductor device. FIG. 1 shows a longitudinal sectional view of a portion including at least one source electrode in the cross section taken along the line AA in FIG. This junction type semiconductor device shows an example of SIT (electrostatic induction transistor).

  As shown in FIG. 2, the SIT 10 includes, for example, five source electrodes 19 arranged in parallel in a specific unit region on the upper surface of the device.

In the longitudinal cross-sectional structure shown in FIG. 1, the SIT 10 has a drain region 11 formed of an n-type low resistance layer (n ⁺ layer) formed on a lower surface portion having a SiC (silicon carbide) crystal, and the SiC crystal. A source region 12 made of an n-type low resistance layer (n ⁺ layer) formed on the upper side surface portion is provided. The layer forming the drain region 11 is a substrate.

As shown in FIG. 2, a gate electrode 20 is formed around each of the plurality of source electrodes 19 so as to surround the source electrode 19 in the positional relationship of the plan view. This means that the source region 12 located below the source electrode 19 is surrounded by the p-type gate region 13 located below the gate electrode 20. The gate region 13 is formed up to a predetermined deep position. Further, in the SIT 10, an n-type high resistance layer (n ⁻ layer) 14 is formed between the upper source region 12 and the lower drain region 11. Further, in the high resistance layer 14, a p-type channel dope layer 15 is formed so as to be connected to the gate region 13.

  In this embodiment, the “n-type” is a “first conductivity type”, and the “p-type” is a “second conductivity type”.

In the SIT 10 according to the present embodiment, a p-type recombination suppression region is preferably formed at a boundary region between the gate region 13 and the n-type high resistance layer 14, preferably up to a depth position exceeding the channel dope layer 15. 16 is provided. The formation position of the recombination suppression region 16 in the depth direction can be appropriately set according to the purpose as described later. The recombination suppression region 16 is provided all around the side surface of the gate region 13. The recombination suppression region 16 is formed of a p ⁻ semiconductor having a higher resistivity than the gate region 13 or an n ⁻ semiconductor having a higher resistivity than the high resistance layer 14.

  In the structure of the SIT 10, as shown in FIG. 1, the drain electrode 18 is joined to the lower surface of the drain region 11, the source electrode 19 is joined to the upper surface of the source region 12, and the upper side of the gate region 13. A gate electrode 20 is bonded to the surface. On the upper surface of the SIT 10, the exposed surface between the source electrode 19 and the gate electrode 20 is covered and protected by the surface protective film 17.

  As shown in FIG. 2, an upper layer electrode 21 is provided above each of the source electrode 19 and the gate electrode 20. In FIG. 1, the upper layer electrode 21 is not shown.

  In the SIT 10, the main current is an electron flow that flows from the source region 12 (or the source electrode 19) to the drain region 11 (or the drain electrode 18). Energization (ON) and non-energization (OFF) of the main current are controlled based on a gate voltage applied to the gate electrode 20, that is, a control signal applied between the gate region 13 and the source region 12. When the applied voltage between the gate and the source is 0 V or less, the main current does not flow through the SIT 10 and it is turned off. When a voltage of a certain level or higher is applied between the gate and the source, the main current flows through the SIT 10 and shifts to the on state. In the on state, the pn junction formed between the gate region 13 and the source region 12 is forward-biased, and a hole current that is a control current flows through the source region 12 in the gate region 13.

  The characteristic structure of the SIT 10 will be described with reference to FIGS. 3 and 4 while comparing the conventional SIT structure with the SIT structure according to the present embodiment.

  In FIG. 3, the same elements as those described in FIG. In the SIT 10A having the conventional structure, a region 31 having a large number of recombination levels 31a is formed around the gate region 13. In the on state of the SIT 10A, in the region 31, the holes 32 flowing from the gate region 13 and the electrons 33 flowing from the source region 12 coexist. Therefore, in the region 31, recombination of electrons 33 and holes 32 occurs actively, an invalid gate current that does not contribute to the operation of the SIT 10A flows, and the current amplification factor of the SIT 10A decreases. In FIG. 3, I1 is a main current.

  In contrast to the SIT 10A having the conventional structure, in the SIT 10 according to the present embodiment, as shown in FIG. 4, the recombination suppression region 16 is formed at the boundary with the n-type high resistance layer 14 around the side surface of the gate region 13. Yes. The recombination suppression region 16 is formed, for example, by performing ion implantation on the main portion of the region 31 where many recombination levels 31a exist.

The recombination suppression region 16 has the same conductivity type as the gate region 13 and is a p ^- semiconductor having a higher resistivity than the gate region 13, or the same conductivity type as the high resistance layer 14 and a higher resistivity than the high resistance layer 14. N ^- semiconductor. Since the recombination suppression region 16 is designed to have a high resistance, the density of holes is low when “p ⁻ ” and the density of electrons is low when “n ⁻ ”.

  Further, since a potential barrier against electrons or holes is formed between the recombination suppression region 16 and the high resistance layer 14 or between the gate region 13 and the recombination suppression region 16, electrons or holes are recombined. Intrusion into the suppression region 16 is suppressed. As a result, electrons 33 flowing from the source region 12 flow into the drain region 11 as the main current I2 without being consumed as a recombination current in the region 31 where a large number of recombination levels exist. In this way, the current amplification factor of the SIT 10 is improved.

  Also when forming the recombination suppression region 16, an ion implantation method of Al or the like is used as in the case of forming the gate region 13. However, the implantation concentration is extremely low compared to the ion implantation for forming the gate region 13, and the energy required for the ion implantation is also low. Therefore, in the ion implantation for forming the recombination suppression region 16, the density of recombination levels can be suppressed low.

  Next, a specific example of the impurity concentration and dimensions of each high resistance layer of the SIT 10 according to the first embodiment will be described.

The SIT 10 is designed with a target of a blocking voltage of 600V, for example. As the substrate portion, a low resistance n-type 4H—SiC substrate which is turned off by 8 degrees from the (0001) plane is used. In SIT 10, the substrate portion becomes the drain region 11. The high resistance layer 14 on the substrate is a layer for preventing a high voltage applied between the source and the drain. In the present embodiment, the high resistance layer 14 is set to have a thickness of 10 μm and an impurity concentration of 1 × 10 ¹⁶ cm ⁻³ , for example, so as to block a voltage of 600 V or higher.

The p-type channel doped layer 15 on the high resistance layer 14 has a thickness so that the SIT 10 does not turn on even when a gate-source voltage V _GS = 0 V when a high voltage is applied between the source and the drain. And impurity concentration is set. In this embodiment, the p-type channel dope layer 15 has a thickness of 0.1 to 0.5 μm and an impurity concentration of 4 × 10 ¹⁷ to 2 × 10 ¹⁸ cm ⁻³ . On the channel dope layer 15, a thickness of 0.5 to 0.4 μm and a high resistance layer 14 having an impurity concentration of 5 × 10 ¹⁵ cm ^{−3 to} 5 × 10 ¹⁷ cm ⁻³ are interposed. A low-resistance n-type source region 12 having 2.0 μm and an impurity concentration of 1 to 5 × 10 ¹⁹ cm ⁻³ is provided.

Further, a low-resistance gate region 13 having a thickness of 1 to 2 μm and an impurity concentration of about 1 × 10 ¹⁸ to 1 × 10 ¹⁹ cm ⁻³ is provided around the source region 12. As shown in FIG. 2, the planar shape of the source region 12 is an elongated island shape. One SIT 10 includes a plurality of source regions 12. The dimensions of one source region 12 are about 3 to 10 μm in width and about 100 to 1000 μm in length. The period of the unit structure including the gate region 13 and the source region 12 is about 10 to 30 μm.

  Next, the manufacturing method of SIT10 is demonstrated with reference to FIGS. FIG. 5 shows a flowchart of the manufacturing method. 6A and 6B show a semiconductor device manufactured in each step.

  The manufacturing method of SIT10 consists of the following processes (1) to (11) (steps S11 to S21). As shown in FIG. 5, the process is executed in the order from step S11 to step S21.

(1) High resistance layer forming process (step S11)
(2) Channel dope layer forming process (step S12)
(3) High resistance layer formation process (step S13)
(4) Low resistance layer formation process (step S14)
(5) Source etching process (step S15)
(6) Gate region formation process (step 16)
(7) Recombination suppression region formation process (step S17)
(8) Ion implantation layer activation process (step S18)
(9) Surface protective film formation process (step S19)
(10) Electrode formation process (step S20)
(11) Upper layer electrode formation process (step S21)

  By performing the above steps S11 to S14, the structure shown in FIG. 6A (a) is formed.

In the high resistance layer formation process (step S11), a high resistance in which nitrogen having a thickness of 10 μm and a concentration of 1 × 10 ¹⁶ cm ⁻³ is doped as an impurity on an n-type substrate 40 formed of SiC by an epitaxial growth method. Layer 41 is grown. As the substrate 40, “4H—SiC (0001) 8 ° off” is used. The substrate 40 becomes the drain region 11 of the n-type low resistance layer described above.

In the channel dope layer forming process (step S12), 0.1 ^% in concentration of 4 × 10 ¹⁷ to 2 × 10 ¹⁸ cm ⁻³ with aluminum (Al) as an impurity is formed on the n-type high resistance layer 41 by an epitaxial growth method. A p-type channel doped layer 42 of ~ 0.5 μm is grown.

In the high resistance layer forming process (step S13), nitrogen having a thickness of 0.1 to 0.4 μm and a concentration of 5 × 10 ^{15 to} 5 × 10 ¹⁷ cm ⁻³ is formed on the channel dope layer 42 by an epitaxial growth method. An n-type high-resistance layer 43 doped with impurities is grown.

In the low resistance layer forming process (step S14), nitrogen of 0.5 to 2.0 μm in thickness and 1 to 5 × 10 ¹⁹ cm ⁻³ is doped on the n-type high resistance layer 43 by an epitaxial growth method. An n-type low resistance layer 44 doped as follows is grown. The low resistance layer 44 forms the source region 12 described above.

In the next source etching process (step S15), in the structure shown in FIG. 6A (a), a silicon oxide film 51 is deposited on the upper surface by CVD, photolithography is performed, and then silicon oxide is oxidized by RIE. The film 51 is etched. Thus, a mask is formed. Thereafter, using this silicon oxide film 51, SiC etching of the low resistance layer 44 is performed by RIE, thereby forming the source region 12. SF ₆ gas or the like is used for RIE of SiC etching. The resulting structure is shown in FIG. 6A (b). The etching depth is, for example, about 0.5 to 2.3 μm.

In the gate region formation process (step S16), as shown in FIG. 6A (c), the mask 52 is formed so that the surface portion for forming the gate region 13 is further exposed. The mask 52 is formed by depositing a silicon oxide film by a CVD method, performing photolithography, and then etching the silicon oxide film by RIE. Thereafter, the gate region 13 is formed by ion implantation. The ions to be implanted are aluminum (Al), and the depth of implantation is, for example, 1 to 2 μm. The amount of ion implantation is 1 × 10 ¹⁸ to 1 × 10 ¹⁹ cm ⁻³ , and the energy required for ion implantation is 700 KeV to 2 MeV or more.

In the process (S17) for forming the recombination suppression region, a mask for forming the recombination suppression region 16 is formed as shown in FIG. 6D (d). In this mask formation, a mask 53 (silicon oxide film) for forming a gate region is used. In the mask 52 shown in FIG. 6A (c), for example, isotropic etching such as wet etching is used to remove only the portion for forming the recombination suppression region. Thereafter, ion implantation of aluminum (Al) as an impurity (ion species) is performed. The region to be implanted is wider than the gate region 13 and narrower than the gate-source distance. In terms of dimensions, for example, it is 0.5 μm on each side of the gate width. The depth of implantation is, for example, about 0.4 μm. Furthermore, the recombination suppression region 16 may be formed from the gate surface to the deepest depth of the gate region. The ion implantation amount is about 5 × 10 ^{15 to} 5 × 10 ¹⁷ cm ⁻³ , and a value around the n ⁻ type high resistance layers 41 and 43 is desirable. The energy required for ion implantation is, for example, about 400 KeV, but is determined according to the implantation depth. In this way, the recombination suppression region 16 is formed at a required depth all around the side surface of the gate region 13. In consideration of the planar shape shown in FIG. 2, the recombination suppression region 16 is formed so as to cover the entire periphery of the side surface of the gate region 13.

  The recombination suppression region 16 which is a p-type region does not have a function as a gate, and is intended to reduce the density of holes and electrons in a region where a large number of recombination levels exist. Therefore, both the implantation amount and the implantation energy are set to be smaller than the ion implantation at the time of forming the gate region. As a result, damage to the crystal due to ion implantation can be kept low, and adverse effects on the device characteristics of the SIT due to the manufacturing process can be suppressed.

  Regarding the process of forming the gate region 13 and the recombination suppression region 16 (steps S16 and S17), the main parts are conceptually shown in more detail as shown in FIGS. In FIG. 7, only the gate region 13 and the recombination suppression region 16 are shown, and the source region and the channel dope region are omitted.

FIG. 7A shows a process of implanting ions (Al ⁺ ) 61 to form the gate region 13, and FIG. 7B shows a mask 62 for forming a recombination suppression region around the side surface of the gate region 13. A process for forming the oxide film by wet etching is shown, and (c) shows a process for implanting ions (Al ⁺ ) 61 in order to form the recombination suppression region 16.

  In this process, Al ions 61 are selectively implanted into the SiC 63 to form the gate region 13 using the mask 62 formed of a silicon oxide film or the like, and then the mask 62 is just the SiC surface of the recombination suppression region 16. Etching is performed so that is exposed. The width of the SiC surface newly exposed by etching is, for example, 0.5 μm. Al ions are again implanted into the SiC 63 in order to form the recombination suppression region 16 using the mask 62 after the etching. In FIG. 7C, the depth of the recombination suppression region 16 is represented by d. Since the mask alignment process is not used for forming the ion implantation mask 62 for forming the recombination suppression region 16 in this way, a self-alignment process in which the positional relationship between the gate region 13 and the recombination suppression region 16 does not occur. It has become.

  In addition to the process of forming the gate region 13 and the recombination suppression region 16, there is a formation method as shown in FIG. In FIG. 8, only the gate region 13 and the recombination suppression region 16 are shown, and the source region and the channel dope region are omitted.

  The formation method will be described with reference to FIG. In this forming method, first, a mask 62 is formed so that ion implantation 61 for forming a recombination suppression region can be performed, and ion implantation 61 for forming the recombination suppression region 16 is performed (FIG. 8A). ). Thereafter, an oxide film 64 is deposited on the entire surface by CVD (FIG. 8B). The oxide film 64 formed on the surface is etched by anisotropic etching to expose the surface 65 that forms the gate region (FIG. 8C). The surface 65 is the upper surface of the recombination suppression region 16 described above. Thereafter, ion implantation 61 for forming the gate region 13 is performed on the exposed surface 65 (FIG. 8D).

  As described above, the gate region 13 is formed. Also in this case, the recombination suppression region 16 is formed around the side surface of the gate region 13 with a depth d from the surface of the gate region 13. This method is also a self-alignment process, and no positional deviation occurs between the gate region 13 and the recombination suppression region 16. In addition, regarding the formation of the gate region 13 and the recombination suppression region 16, a mask may be formed for each using a photo process. This method is particularly effective when the width of the recombination suppression region is widened to about 1 μm or more.

  Next, the depth d and the impurity concentration of the recombination suppression region 16 will be described in more detail.

  Since it is desirable that the recombination suppression region 16 cover the gate as much as possible, the depth d is desired to be approximately the same as the depth of the gate region. On the other hand, in SiC, an ion implantation method is used as a method for forming the recombination suppression region 16, but high energy is required to implant ions into a deep portion, and ion implantation with high energy is a new method. A defect will be generated. Therefore, it is desirable that the depth d is shallow from the viewpoint of not generating new defects. In determining the depth d in this way, it is necessary to consider the conflicting phenomenon of forming the recombination suppression region 16 over as wide a range as possible and minimizing the formation of new defects. There is.

  As described above, recombination level density, electron density, and hole density affect the occurrence of recombination. It is important to form the recombination suppression region 16 in the higher density portion of the device. When limited to the gate peripheral region of the SIT structure of FIG. 1, the region near the channel dope layer 15 from the SiC surface is a region where both the electron density and the hole density are high.

  Considering these points, it is desirable that the depth d of the recombination suppression region 16 reaches the channel dope layer at least. In this case, the depth d is about 0.1 to 0.3 μm, and even if it is formed by ion implantation, it is possible to minimize the generation of new defects with low energy. The upper limit of the depth d is about the same as the depth of the gate region 13, but this value is determined when forming the depth of the gate region 13 of an individual device and the recombination suppression region 16 of that depth. This is determined in consideration of a new defect density generated by ion implantation energy.

p ^- The recombination-inhibiting region 16, to suppress the electronic entry into the recombination-inhibiting region 16 by forming a pn junction with the high resistance layer, and it is required hole concentration is low. For this reason, the impurity concentration in the recombination suppression region 16 is appropriately the same as or slightly higher than that of the high resistance layer.

In the case of the first embodiment of FIG. 1, since the impurity concentration of the high resistance layer 14 is about 5 × 10 ^{15 to} 5 × 10 ¹⁷ cm ⁻³ , the appropriate value of the impurity concentration of the recombination suppression region 16 is 5 × 10 ^{15 to} 5 × 10 ¹⁷ cm ⁻³ or a slightly higher value than this.

The recombination suppression region 16 may be formed of an n ⁻ region having a higher resistivity than the high resistance layer 14. In that case, the electron concentration in the recombination suppression region 16 becomes low, and the junction potential of the pn junction formed between the gate region 13 and the recombination suppression region 16 becomes a potential barrier against holes, and The flow into the region 31 is suppressed. As a result, recombination in the region 31 is suppressed. When the n ⁻ type recombination suppression region 16 is formed, the implanted impurity concentration is appropriately the same as or slightly lower than that of the high resistance layer 14, and ions are implanted from the n type impurity concentration in the high resistance layer 14. A value obtained by subtracting the p-type impurity concentration is a substantial impurity concentration in the recombination suppression region. In the case of the first embodiment of FIG. 1, a value slightly lower than 5 × 10 ^{15 to} 5 × 10 ¹⁷ cm ⁻³ is an appropriate value of the impurity concentration.

  Therefore, it can be said that a value around the same as the impurity concentration of the high resistance layer 14 is appropriate as the ion implantation amount into the recombination suppression region 16.

  In the process of activating the ion-implanted layer (step S18), after the ion implantation, the implanted ions are electrically activated in the semiconductor and a heat treatment is performed to eliminate crystal defects generated by the ion implantation (FIG. 6B ( e)). In this activation heat treatment, both the implanted ions in the gate region 13 and the implanted ions in the recombination suppression region 16 are activated at the same time. Heat treatment is performed for about 10 minutes at a high temperature of about 1700 to 1800 ° C. using a high-frequency heat treatment furnace or the like. For example, argon gas (Ar) is used as the atmospheric gas.

In the process of forming the surface protective film (step S19), as shown in FIG. 6B (f), first, in order to remove the surface layer generated in the ion implantation step and the activation step, the oxide film is removed after the thermal oxidation. Perform sacrificial oxidation. The oxidation condition is, for example, 1100 ° C. for 20 hours in dry oxygen. Hydrogen fluoride is used to remove the oxide film. After the sacrificial oxidation, thermal oxidation is performed again to form an oxide film 54. The thermal oxide film formation conditions are, for example, a temperature of 1100 ° C., a time of 5 hours, and an atmosphere of wet. Thereafter, heat treatment (POA: Post Oxidation Anneal) is performed to reduce the impurity level at the interface of the SiC oxide film. POA is performed in a hydrogen, nitric oxide (NO, N ₂ O) or argon atmosphere at a high temperature of about 800 to 1300 ° C. for about 10 to 30 minutes. After POA, a CVD oxide film or a CVD nitride film is formed.

  In the process of forming electrodes (step S20), the source electrode 19, the gate electrode 20, and the drain electrode 18 are formed on the surfaces of the source region 12 (low resistance layer 44), the gate region 13, and the drain region 11 (substrate 40). (FIG. 6B (g)). The source electrode 19 and the drain electrode 18 are made of nickel or titanium, and the gate electrode 20 is made of a titanium / aluminum laminated film. Each electrode 18, 19, 20 is formed by vapor deposition or sputtering. For the formation of the electrode pattern, dry etching, wet etching, lift-off method or the like is used. In addition, after the electrodes 18 to 20 are formed, heat treatment is performed to reduce the contact resistance between the metal portion and the semiconductor portion. The heat treatment conditions are a temperature condition of 800 to 1000 ° C. and a time condition of about 10 to 30 minutes.

  Finally, an upper electrode formation process (step S21) is performed. In this upper layer electrode formation process (step S21), an upper layer wiring 56 for taking out the plurality of separated source electrodes 19 to one electrode is formed (FIG. 6B (h)). After a silicon oxide film or the like is formed as the interlayer film 55 by the CVD method, the silicon oxide film or the like in the portion of the source electrode 19 is removed by photolithography and etching. After the source electrode 19 is exposed in this way, the upper layer electrode 56 is deposited. For example, aluminum (Al) is used as the material of the upper layer electrode 56.

  In this way, the SIT 10 shown in FIGS. 1 and 2 is manufactured. The SIT 10 is a high-performance junction type semiconductor device having normally-off characteristics.

  In the first embodiment, the combinations of the first and second conductivity types such as the drain region, the source region, the high resistance layer, the gate region, and the recombination suppression region may be reversed. This also applies to the embodiments described below.

<Second embodiment>
A second embodiment of the junction type semiconductor device according to the present invention will be described with reference to FIG. The junction type semiconductor device according to the second embodiment is also SIT. 9, elements that are substantially the same as the elements described in FIG. The SIT 100 according to the second embodiment is characterized in that the recombination suppression region 71 formed on the side surface of the gate region 13 is formed at a position shallower than the portion where the channel dope layer 15 is formed. Other configurations are the same as those described in the first embodiment.

  The configuration of the SIT 100 has the following advantages. Since the recombination suppression region 71 is formed by ion implantation, although it is a small amount, damage occurs during ion implantation. This damage is not completely eliminated by the subsequent activation heat treatment. In order to improve this, it is effective to reduce the energy for ion implantation and to form a recombination suppression region 71 with less damage and higher quality during ion implantation. The recombination of holes and electrons occurs violently in a region shallower than the channel dope layer 15 where current tends to concentrate. Therefore, even if the recombination suppression region 71 is formed only in the region, the effect of the present invention is sufficiently obtained. Can be achieved. The configuration of the second embodiment is particularly effective when the thickness of the second high resistance layer 14 located on the upper side of the device structure of the SIT 100 is large.

<Third embodiment>
A third embodiment of the junction type semiconductor device according to the present invention will be described with reference to FIG. The junction type semiconductor device according to the third embodiment is SIT. 10, elements that are substantially the same as those described in FIG. 1 are denoted by the same reference numerals. In the SIT 200 according to the third embodiment, the recombination suppressing region 72 is formed so as to cover the entire region that forms the boundary portion between the side surface and the bottom surface portion of the gate region 13, that is, the other portion of the gate region 13. Other configurations are the same as those described in the first embodiment.

  According to the configuration of the SIT 200, almost all of the recombination levels generated by ion implantation at the time of forming the gate region can be covered by the recombination suppression region 72. The manufacturing method of the SIT 200 can be realized by applying the manufacturing method shown in FIG. That is, the SIT 200 having the structure shown in FIG. 10 can be manufactured by forming the recombination suppression region 16 deeper than the depth of the gate region 13 in the manufacturing method shown in FIG. Although the implantation energy for ion implantation for forming the recombination suppression region 16 is high, the ion implantation amount in the recombination suppression region 16 is much less than the ion implantation amount in the gate region 13, thereby reducing damage to the crystal. be able to. The configuration of the third embodiment is more effective when the gate region 13 is shallow.

<Fourth embodiment>
With reference to FIG. 11, a description will be given of a fourth embodiment of the junction type semiconductor device according to the present invention. The junction type semiconductor device according to the fourth embodiment shows an example of BJT (bipolar junction transistor). In FIG. 11, the BJT 300 includes a collector region 311, an emitter region 312, a base contact region 313, upper and lower high resistance layers 314, and a base region 315.

  The base region 315 of the BJT 300 corresponds to the aforementioned channel dope layer of the SIT. Further, a collector electrode 321, an emitter electrode 322, and a base electrode 323 are joined to the collector region 311, the emitter region 312, and the base contact region 313, respectively.

  In the BJT 300, electrons that are the main current flow from the emitter region 312 to the collector region 311. The base contact region 313 corresponds to the gate region 13 of the SIT 10 described above and is supplied with a control signal. A surface protective film 316 is provided on the exposed surface between the emitter electrode 322 and the base electrode 323 on the device surface of the BJT 300. Also in the BJT 300 according to the present embodiment, the entire peripheral surface of the side surface and the bottom surface of the base contact region 313 is covered with the recombination suppression region 317.

<Fifth embodiment>
A fifth embodiment of the junction type semiconductor device according to the present invention will be described with reference to FIG. The junction type semiconductor device according to the fifth embodiment also shows an example of BJT as in the fourth embodiment. 12, the same elements as those described in FIG. 11 are denoted by the same reference numerals, and the description thereof is omitted. The BJT 400 according to the fifth embodiment is characterized in that the recombination suppression region 411 is formed in the range around the side surface of the base contact region 313 and above the base region 315.

  As described above, unlike the conventional junction type semiconductor device, the present invention is provided with the recombination suppression region on the side surface of the gate region or the base contact region. For this reason, for example, recombination of minority carriers injected from the gate region and majority carriers injected from the source region is suppressed, the current amplification factor of the junction semiconductor device can be improved, and the on-voltage (resistance) can be reduced.

  Specific numerical values shown in this embodiment such as the thickness of each layer and the amount of ion implantation energy are merely examples, and can be appropriately changed within the scope of realizing the present invention.

  In this embodiment, a reverse polarity type in which the polarities of p and n in the description of the steps of the manufacturing method are reversed may be used. Furthermore, in the present embodiment, an example of SiC has been described, but the present invention can also be applied to other semiconductors in which recombination is a problem.

  The configurations, shapes, sizes, and arrangement relationships described in the above embodiments are merely schematically shown to the extent that the present invention can be understood and implemented. Further, numerical values and compositions (materials) of the respective components, etc. Is merely an example. Therefore, the present invention is not limited to the described embodiments, and can be modified in various forms without departing from the scope of the technical idea shown in the claims.

  The present invention can be used for manufacturing a high-performance junction type semiconductor device.

10 Junction semiconductor devices (SIT)
DESCRIPTION OF SYMBOLS 11 Drain region 12 Source region 13 Gate region 14 High resistance layer 15 Channel dope layer 16 Recombination suppression region 17 Surface protective film 18 Drain electrode 19 Source electrode 20 Gate electrode 21 Upper layer electrode 40 Substrate 41, 43 High resistance layer 42 Channel dope layer 44 Low resistance layer 100 Junction type semiconductor device (SIT)
200 Junction semiconductor devices (SIT)
300 Junction semiconductor device (BJT)
400 Junction type semiconductor device (BJT)

Claims (13)

A first main electrode region of one conductivity type of the first conductivity type or the second conductivity type, which is a substrate made of a silicon carbide semiconductor crystal;
A second main electrode region of the one conductivity type formed on one surface side of the substrate;
The one conductive type high-resistance layer formed between the first main electrode region and the second main electrode region in a cross-sectional view;
A control electrode region of the other conductivity type of the first conductivity type or the second conductivity type formed around the second main electrode region in plan view;
A channel doped layer of the other conductivity type in contact with the control electrode region in the high resistance layer;
It is formed so as to cover at least the side surface of the control electrode region, and flows between one of holes or electrons from the control electrode region and the first main electrode region and the second main electrode region. A recombination suppression region that suppresses recombination with the other of the holes or the electrons;
Have
The high resistance layer has a higher resistivity than the second main electrode region,
The recombination suppression region has the same conductivity type as the other conductivity type and has a higher resistivity than the control electrode region, or the same conductivity type as the one conductivity type and the high resistance layer Has a higher resistivity,
In a cross-sectional view, the side surface of the control electrode region includes all of the boundary portion between the high resistance layer and the control electrode region located above the channel dope layer, and the recombination suppression region includes the recombination suppression region. A junction type semiconductor device, wherein the channel doped layer is formed to a depth position where it is formed.   In a cross-sectional view, the side surface of the control electrode region further includes a boundary portion between the high resistance layer located below the channel dope layer and the control electrode region, and the recombination suppression region is the control The junction type semiconductor device according to claim 1, wherein the junction type semiconductor device is formed up to a depth position where the electrode region is formed. The recombination suppression region is formed so as to cover the side surface and the bottom surface of the control electrode region,
In a cross-sectional view, the side surface and the bottom surface of the control electrode region further include all of a boundary portion between the high resistance layer located below the channel dope layer and the control electrode region, and the recombination The junction type semiconductor device according to claim 1, wherein the suppression region is formed to a depth position where the control electrode region is formed. The first main electrode region is a drain region composed of a low resistance layer having a lower resistivity than the high resistance layer of the first conductivity type,
The second main electrode region is a source region composed of a low resistance layer having a lower resistivity than the high resistance layer of the first conductivity type,
4. The junction type semiconductor device according to claim 1, wherein the control electrode region is a gate region of the second conductivity type. 5. The first main electrode region is a drain region made of a low resistance layer having a lower resistivity than the high conductivity layer of the second conductivity type,
The second main electrode region is a source region composed of a low resistance layer having a lower resistivity than the high conductivity layer of the second conductivity type,
4. The junction type semiconductor device according to claim 1, wherein the control electrode region is a gate region of the first conductivity type. 5. A first main electrode region of one conductivity type of the first conductivity type or the second conductivity type, which is a substrate made of a silicon carbide semiconductor crystal;
A second main electrode region of the one conductivity type formed on one surface side of the substrate;
The one conductive type high-resistance layer formed between the first main electrode region and the second main electrode region in a cross-sectional view;
A control electrode region of the other conductivity type of the first conductivity type or the second conductivity type formed around the second main electrode region in plan view;
The base layer of the other conductivity type in contact with the control electrode region in the high resistance layer;
It is formed so as to cover at least the side surface of the control electrode region, and flows between one of holes or electrons from the control electrode region and the first main electrode region and the second main electrode region. A recombination suppression region that suppresses recombination with the other of the holes or the electrons;
Have
The high resistance layer has a higher resistivity than the second main electrode region,
The recombination suppression region has the same conductivity type as the other conductivity type and has a higher resistivity than the control electrode region, or the same conductivity type as the one conductivity type and the high resistance layer Has a higher resistivity,
In a cross-sectional view, the side surface of the control electrode region includes all of the boundary portion between the high resistance layer located above the base layer and the control electrode region, and the recombination suppression region is the base. Formed to the depth position where the layer was formed,
The first main electrode region is a collector region composed of a low resistance layer having a lower resistivity than the high conductivity layer of the first conductivity type,
The second main electrode region is an emitter region composed of a low resistance layer having a lower resistivity than the high resistance layer of the first conductivity type,
Said region control electrode junction type semiconductor device, characterized in that the said base contact region of the second conductivity type. A first main electrode region of one conductivity type of the first conductivity type or the second conductivity type, which is a substrate made of a silicon carbide semiconductor crystal;
A second main electrode region of the one conductivity type formed on one surface side of the substrate;
The one conductive type high-resistance layer formed between the first main electrode region and the second main electrode region in a cross-sectional view;
A control electrode region of the other conductivity type of the first conductivity type or the second conductivity type formed around the second main electrode region in plan view;
The base layer of the other conductivity type in contact with the control electrode region in the high resistance layer;
It is formed so as to cover at least the side surface of the control electrode region, and flows between one of holes or electrons from the control electrode region and the first main electrode region and the second main electrode region. A recombination suppression region that suppresses recombination with the other of the holes or the electrons;
Have
The high resistance layer has a higher resistivity than the second main electrode region,
The recombination suppression region has the same conductivity type as the other conductivity type and has a higher resistivity than the control electrode region, or the same conductivity type as the one conductivity type and the high resistance layer Has a higher resistivity,
In a cross-sectional view, the side surface of the control electrode region includes all of the boundary portion between the high resistance layer located above the base layer and the control electrode region, and the recombination suppression region is the base. Formed to the depth position where the layer was formed,
The first main electrode region is a collector region made of a low resistance layer having a lower resistivity than the high conductivity layer of the second conductivity type,
The second main electrode region is an emitter region composed of a low resistance layer having a lower resistivity than the high conductivity layer of the second conductivity type,
Said region control electrode junction type semiconductor device, characterized in that the said base contact region of the first conductivity type. A high resistance layer of one conductivity type is formed on a substrate made of a semiconductor crystal of silicon carbide and serving as a first main electrode region of one conductivity type of the first conductivity type or the second conductivity type A first step of:
A second step of forming a low resistance layer to be the second main electrode region of the one conductivity type on the high resistance layer;
A third step of forming a control electrode region of the other conductivity type of the first conductivity type or the second conductivity type by ion implantation in a predetermined region on the surface side of the high resistance layer;
A fourth step of forming a recombination suppression region by ion implantation so as to cover at least a side surface of the control electrode region;
A method for manufacturing a junction type semiconductor device including:
Providing a step for forming a channel dope layer or a base layer in the high resistance layer;
The recombination suppression region includes one of holes or electrons from the control electrode region and the other of the holes or electrons flowing between the first main electrode region and the second main electrode region. Suppresses recombination of
The high resistance layer has a higher resistivity than the second main electrode region,
The recombination suppression region has the same conductivity type as the other conductivity type and has a higher resistivity than the control electrode region, or the same conductivity type as the one conductivity type and the high resistance layer Has a higher resistivity,
In the cross-sectional view of the junction type semiconductor device, the side surface of the control electrode region includes all of the boundary portion between the high resistance layer and the control electrode region located above the channel dope layer or the base layer. And the recombination suppression region is formed to a depth position where the channel dope layer or the base layer is formed.   9. The junction type according to claim 8, wherein an impurity concentration ion-implanted to form the recombination suppression region is lower than an impurity concentration ion-implanted to form the control electrode region. A method for manufacturing a semiconductor device. Forming a first main electrode, a second main electrode, and a control electrode in each of the first main electrode region, the second main electrode region, and the control electrode region;
Forming an upper layer electrode above the two main electrodes and the control electrode;
The method for manufacturing a junction type semiconductor device according to claim 8, wherein: A high resistance layer of one conductivity type is formed on a substrate made of a semiconductor crystal of silicon carbide and serving as a first main electrode region of one conductivity type of the first conductivity type or the second conductivity type A first step of:
A second step of forming a low resistance layer to be the second main electrode region of the one conductivity type on the high resistance layer;
A third step of forming a recombination suppression region by ion implantation in a predetermined region on the surface side of the high resistance layer;
A fourth step of forming, in the recombination suppression region, a control electrode region of the other conductivity type of the first conductivity type or the second conductivity type by ion implantation from the surface side of the recombination suppression region; ,
A method for manufacturing a junction type semiconductor device including:
Providing a step for forming a channel dope layer or a base layer in the high resistance layer;
The recombination suppression region includes one of holes or electrons from the control electrode region and the other of the holes or electrons flowing between the first main electrode region and the second main electrode region. Suppresses recombination of
The high resistance layer has a higher resistivity than the second main electrode region,
The recombination suppression region has the same conductivity type as the other conductivity type and has a higher resistivity than the control electrode region, or the same conductivity type as the one conductivity type and the high resistance layer Has a higher resistivity,
In the cross-sectional view of the junction type semiconductor device, the side surface of the control electrode region includes all of the boundary portion between the high resistance layer and the control electrode region located above the channel dope layer or the base layer. And the recombination suppression region is formed to a depth position where the channel dope layer or the base layer is formed.   12. The junction type according to claim 11, wherein an impurity concentration ion-implanted to form the recombination suppression region is lower than an impurity concentration ion-implanted to form the control electrode region. A method for manufacturing a semiconductor device. Forming a first main electrode, a second main electrode, and a control electrode in each of the first main electrode region, the second main electrode region, and the control electrode region;
Forming an upper layer electrode above the two main electrodes and the control electrode;
The method of manufacturing a junction type semiconductor device according to claim 11, comprising:

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