JP5410465B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Semiconductor device and manufacturing method of semiconductor device Download PDF

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JP5410465B2
JP5410465B2 JP2011038169A JP2011038169A JP5410465B2 JP 5410465 B2 JP5410465 B2 JP 5410465B2 JP 2011038169 A JP2011038169 A JP 2011038169A JP 2011038169 A JP2011038169 A JP 2011038169A JP 5410465 B2 JP5410465 B2 JP 5410465B2
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semiconductor device
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正彦 小早川
雅秀 前田
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Rohm Co Ltd
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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
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    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
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    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
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    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

本願発明は、半導体装置および半導体装置の製造方法に関する。 The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device .

半導体装置としては、従来より図１５（ａ）に示したようなものがある。この図に示した半導体装置９は、第１および第２導体９０，９１、半導体チップ９２を有している。第１および第２導体９０，９１は、端子面９０ａ，９１ａおよび接続面９０ｂ，９１ｂを有している。第１導体９０は、端子面９０ａに対応する部分以外は、厚み寸法（図の上下方向の寸法）の小さい薄肉部９０ｃとされている。   Conventionally, there is a semiconductor device as shown in FIG. The semiconductor device 9 shown in this figure has first and second conductors 90 and 91 and a semiconductor chip 92. The first and second conductors 90 and 91 have terminal surfaces 90a and 91a and connection surfaces 90b and 91b. The first conductor 90 is a thin-walled portion 90c having a small thickness dimension (a vertical dimension in the drawing) except for a portion corresponding to the terminal surface 90a.

半導体チップ９２は、上面および下面に電極（図示略）が形成されている。第１導体９０の接続面９０ｂ上には、下面の電極と導通するようにして半導体チップ９２が搭載されている。この半導体チップ９２の上面の電極は、ワイヤ９３を介して第２導体９１の接続面９１ｂと導通接続されている。半導体チップ９２およびワイヤ９３は、樹脂パッケージ９４により封止されており、この樹脂パッケージ９４の底面９４ａからは第１および第２導体９０，９１の端子面９０ａ，９１ａが露出している。   The semiconductor chip 92 has electrodes (not shown) formed on the upper and lower surfaces. A semiconductor chip 92 is mounted on the connection surface 90b of the first conductor 90 so as to be electrically connected to the electrode on the lower surface. The electrode on the upper surface of the semiconductor chip 92 is electrically connected to the connection surface 91 b of the second conductor 91 via the wire 93. The semiconductor chip 92 and the wire 93 are sealed with a resin package 94, and the terminal surfaces 90 a and 91 a of the first and second conductors 90 and 91 are exposed from the bottom surface 94 a of the resin package 94.

このような半導体装置９は、次のようにして製造される。まず、第１および第２導体９０，９１となるべき要素が形成された半導体装置製造用のフレームに対して、半導体チップ９２を搭載した後に、ワイヤ９３をボンディングを行う。そして、半導体チップ９２およびワイヤ９３を樹脂封止した後にダイシングを行うことにより、図１５（ａ）に示したような半導体装置９が得られる。   Such a semiconductor device 9 is manufactured as follows. First, a semiconductor chip 92 is mounted on a frame for manufacturing a semiconductor device in which elements to be first and second conductors 90 and 91 are formed, and then a wire 93 is bonded. Then, dicing is performed after the semiconductor chip 92 and the wire 93 are sealed with the resin, whereby the semiconductor device 9 as shown in FIG. 15A is obtained.

半導体装置９では、第１導体９０に薄肉部９０ｃが形成されているため、先に説明した半導体装置９の製造方法では、エッチング処理により半導体装置製造用のフレームが製造されていた。より具体的には、図１６（ａ）に示したように板状導体９５の両面にマスク９６を形成し、板状導体９５の両面からエッチング処理を施すことにより形成される。マスク９６は、エッチング処理すべき部分に対応した開口９７Ａ，９７Ｂを有している。そのため、図１６（ｂ）に示したようにエッチング液により板状導体９５の厚みの半分程度にまでエッチング処理を施せば、板状導体９５の一面側にのみ開口９７Ｂが形成されている部分については板状導体９５の厚みの半分程度の薄肉部９８とされる。一方、板状導体９５の両面側に開口９７Ａ，９７Ｂが形成された部分については貫通孔９９とされる。このようなマスク９６は、フォトリソグラフィの手法により形成することができる。   In the semiconductor device 9, since the thin portion 90c is formed in the first conductor 90, in the manufacturing method of the semiconductor device 9 described above, the frame for manufacturing the semiconductor device is manufactured by the etching process. More specifically, as shown in FIG. 16A, the mask 96 is formed on both surfaces of the plate-like conductor 95, and etching is performed from both surfaces of the plate-like conductor 95. The mask 96 has openings 97A and 97B corresponding to portions to be etched. Therefore, as shown in FIG. 16B, if etching is performed to about half the thickness of the plate-like conductor 95 with the etching solution, the portion where the opening 97B is formed only on one surface side of the plate-like conductor 95. Is a thin portion 98 that is about half the thickness of the plate-like conductor 95. On the other hand, the portions where the openings 97 </ b> A and 97 </ b> B are formed on both sides of the plate-like conductor 95 are made through holes 99. Such a mask 96 can be formed by a photolithography technique.

しかしながら、板状導体９５に対してマスク９６を形成し、この状態でエッチング処理を施して半導体装置製造用のフレームを製造する場合には、次の問題があった。   However, when a mask 96 is formed on the plate-like conductor 95 and etching is performed in this state to manufacture a frame for manufacturing a semiconductor device, there are the following problems.

第１に、フープ状とされた板状導体については、フープラインでのマスク形成およびエッチング処理が困難であるため、たとえば短冊状の板状導体についてマスク９６を形成した後に、エッチング処理を施す必要がある。そのため、フープラインにおいて、半導体装置製造用のフレームの製造、半導体チップの実装、およびワイヤボンディングを一連に行うことができないため、作業性が悪化する。   First, since it is difficult to form a mask at the hoop line and to perform an etching process on the hoop-shaped plate-shaped conductor, for example, it is necessary to perform an etching process after forming the mask 96 on a strip-shaped plate-shaped conductor. There is. For this reason, in the hoop line, the manufacture of the frame for manufacturing the semiconductor device, the mounting of the semiconductor chip, and the wire bonding cannot be performed in series, so that workability is deteriorated.

第２に、半導体装置製造用のフレームの製造に当たっては、板状導体９５にマスク９６を形成する必要があるばかりか、エッチング処理後にマスク９６を除去する必要もあるため、作業性が悪く、しかもコスト高となってしまう。   Secondly, in manufacturing a frame for manufacturing a semiconductor device, not only the mask 96 needs to be formed on the plate-like conductor 95 but also the mask 96 needs to be removed after the etching process, and the workability is poor. Cost will be high.

第３に、図１５（ｂ）に示したように、エッチング処理では、第１導体９０を平面視矩形状の形態とすべく開口９７ａに直角な角部を設けたとしても、エッチング液の回り込みにより第１導体９０の角部が丸まってしまう。そのため、半導体チップ９２が平面視矩形状である場合には、第１導体９２の周縁部９２ａを半導体チップ９２の実装領域として有効に利用できないばかりか、半導体装置９の大型化を招来してしまう。   Third, as shown in FIG. 15B, in the etching process, even if a corner portion perpendicular to the opening 97a is provided so that the first conductor 90 has a rectangular shape in plan view, the etching solution wraps around. As a result, the corners of the first conductor 90 are rounded. Therefore, when the semiconductor chip 92 has a rectangular shape in plan view, the peripheral portion 92a of the first conductor 92 cannot be effectively used as a mounting region for the semiconductor chip 92, and the semiconductor device 9 is increased in size. .

本願発明は、このような事情のもとに考えだされたものであって、大型化を招来することなく、作業性良く、コスト的に有利に製造できる半導体装置およびその製造方法を提供することを課題としている。 The present invention has been conceived under such circumstances, and provides a semiconductor device that can be manufactured with good workability and cost effectiveness without incurring an increase in size and a method for manufacturing the same. Is an issue.

本願発明では、上記した課題を解決するために次の技術的手段を講じている。   In the present invention, the following technical means are taken in order to solve the above-described problems.

すなわち、本願発明により提供される半導体装置の製造方法は、リードフレームを用いて半導体装置を製造する方法であって、上記リードフレームは、板状導体に対して貫通孔を形成する貫通孔形成工程と、上記板状導体の厚みに対して相対的に厚みが小さく、上記貫通孔の内方を向く自由端を有する薄状部を形成する薄状部形成工程と、上記板状導体に対して、少なくとも上記薄状部の一部を除去して当該薄状部に由来する薄肉部を形成する不要部分除去工程と、上記薄肉部の上面ないしこれに連続する上記薄肉部以外の部分の上面にわたって半導体チップを搭載する工程と、を含んで製造されることを特徴としている。 That is, the semiconductor device manufacturing method provided by the present invention is a method of manufacturing a semiconductor device using a lead frame, wherein the lead frame forms a through hole in a plate-like conductor. A thin portion forming step of forming a thin portion having a relatively small thickness with respect to the thickness of the plate-like conductor and having a free end facing the inside of the through hole; and An unnecessary portion removing step of removing at least a part of the thin portion to form a thin portion derived from the thin portion, and an upper surface of the thin portion or an upper surface of a portion other than the thin portion continuous to the thin portion. manufactured includes a step of mounting the semiconductor chip, the is characterized in Rukoto.

本願発明により提供される半導体装置の製造方法はまた、リードフレームを用いて半導体装置を製造する方法であって、上記リードフレームは、板状導体に対して貫通孔を形成する貫通孔形成工程と、半導体チップを搭載する面の反対側からの加工により、上記貫通孔に沿って上記板状導体の厚みに対して相対的に厚みが小さい薄状部を形成する薄状部形成工程と、上記板状導体に対して、少なくとも上記薄状部の一部を除去して当該薄状部に由来する薄肉部を形成する不要部分除去工程と、上記薄肉部の上面ないしこれに連続する上記薄肉部以外の部分の上面にわたって半導体チップを搭載する工程と、を含んで製造されることをも特徴とする。 The method of manufacturing a semiconductor device provided by the present invention is also a method of manufacturing a semiconductor device using a lead frame, wherein the lead frame includes a through-hole forming step of forming a through-hole in a plate-like conductor. A thin portion forming step of forming a thin portion having a relatively small thickness with respect to the thickness of the plate conductor along the through hole by processing from the opposite side of the surface on which the semiconductor chip is mounted; and An unnecessary part removing step for forming at least a part of the thin part to form a thin part derived from the thin part with respect to the plate-shaped conductor, and the upper part of the thin part or the thin part continuous thereto And a step of mounting the semiconductor chip over the upper surface of the other part .

本願発明により提供される半導体装置の製造方法はさらに、リードフレームを用いて半導体装置を製造する方法であって、上記リードフレームは、板状導体に対して内方に向けて突出する半島部を有する貫通孔を形成する貫通孔形成工程と、上記半島部に、上記板状導体の厚みに対して相対的に厚みが小さい薄状部を形成する薄状部形成工程と、上記板状導体に対して、少なくとも上記薄状部の一部を除去して当該薄状部に由来する薄肉部を形成する不要部分除去工程と、上記薄肉部の上面ないしこれに連続する上記薄肉部以外の部分の上面にわたって半導体チップを搭載する工程と、を含んで製造されることをも特徴とする。 The method of manufacturing a semiconductor device provided by the present invention is a method of manufacturing a semiconductor device using a lead frame, wherein the lead frame has a peninsula portion protruding inward with respect to the plate-like conductor. A through hole forming step for forming a through hole, a thin portion forming step for forming a thin portion relatively thin with respect to the thickness of the plate conductor in the peninsula portion, and a plate conductor. On the other hand, an unnecessary part removing step of removing at least a part of the thin part to form a thin part derived from the thin part, and an upper surface of the thin part or a part other than the thin part continuous to the thin part. And a step of mounting the semiconductor chip over the upper surface .

この場合において好ましい実施の形態では、上記薄状部は、上記半島部の先端方に形成される。 In a preferred embodiment in this case, the thin-shaped section, Ru is formed on the tip side of the peninsula.

この場合において好ましい実施の形態では、上記貫通孔形成工程では、上記半島部の基端部に位置する第２の貫通孔が同時に形成される。 In this case, in a preferred embodiment, in the through hole forming step, the second through hole located at the base end of the peninsula is formed at the same time .

この場合において好ましい実施の形態では、上記薄状部は、上記半島部の先端方に形成される部分から、上記半島部の幅方向中央領域を通って上記第２の貫通孔までつながるように形成される。 In this case, in a preferred embodiment, the thin portion is formed so as to be connected from the portion formed toward the tip of the peninsula portion to the second through hole through the central region in the width direction of the peninsula portion. Ru is.

この場合において好ましい実施の形態では、上記不要部分除去工程では、上記半島部に由来する幅方向左右一対の厚肉部と、上記薄状部に由来する薄肉部とが、全体として矩形半島状に形成される。 In a preferred embodiment in this case, in the unnecessary portion removing step, the pair of left and right thick portions derived from the peninsula portion and the thin portions derived from the thin portion are formed into a rectangular peninsular shape as a whole. Ru is formed.

好ましい実施の形態では、上記薄状部は、スタンピング加工によって形成される。 In a preferred embodiment, the thin-shaped section is formed by stamping.

本願発明のその他の利点および特徴については、以下に行う発明の実施の形態の説明から、より明らかとなるであろう。   Other advantages and features of the present invention will become more apparent from the following description of embodiments of the invention.

本願発明の半導体装置の一例を示す全体斜視図である。It is a whole perspective view which shows an example of the semiconductor device of this invention. 図１の半導体装置を底面側からみた全体斜視図である。FIG. 2 is an overall perspective view of the semiconductor device of FIG. 1 viewed from the bottom side. 図１のIII−III線に沿う断面図である。It is sectional drawing which follows the III-III line of FIG. 本願発明に係る半導体装置の製造方法を説明するためのフープラインの一例を示す概略図である。It is the schematic which shows an example of the hoop line for demonstrating the manufacturing method of the semiconductor device which concerns on this invention. フープにおける第１回目の打ち抜き加工を施した部分を示す要部斜視図である。It is a principal part perspective view which shows the part which gave the punching process of the 1st time in a hoop. フープにおけるスタンピング加工を施した部分を示す要部斜視図である。It is a principal part perspective view which shows the part which gave the stamping process in a hoop. フープにおける第２回目の打ち抜き加工を施した部分を示す要部斜視図である。It is a principal part perspective view which shows the part which gave the punching process of the 2nd time in a hoop. フープラインでの作業を終了した中間製造物を示す全体斜視図である。It is a whole perspective view which shows the intermediate product which finished the operation | work in a hoop line. 本願発明の半導体装置の他の例を示す断面図である。It is sectional drawing which shows the other example of the semiconductor device of this invention. 本願発明の半導体装置のさらに他の例を示す断面図である。It is sectional drawing which shows the further another example of the semiconductor device of this invention. 本願発明の半導体装置のさらに他の例を示す断面図である。It is sectional drawing which shows the further another example of the semiconductor device of this invention. 本願発明の半導体装置のさらに他の例を示す断面図である。It is sectional drawing which shows the further another example of the semiconductor device of this invention. 本願発明の半導体装置のさらに他の例を示す断面図である。It is sectional drawing which shows the further another example of the semiconductor device of this invention. 本願発明の半導体装置のさらに他の例を示す断面図である。It is sectional drawing which shows the further another example of the semiconductor device of this invention. エッチング処理によりリードフレームが製造された半導体装置の一例を示す断面図である。It is sectional drawing which shows an example of the semiconductor device with which the lead frame was manufactured by the etching process. リードフレームの製造方法を説明するための要部断面図である。It is principal part sectional drawing for demonstrating the manufacturing method of a lead frame.

以下、本願発明の好ましい実施の形態について、図面を参照して具体的に説明する。図１ないし図３は、本願発明に係る半導体装置の一例を示している。   Hereinafter, preferred embodiments of the present invention will be specifically described with reference to the drawings. 1 to 3 show an example of a semiconductor device according to the present invention.

半導体装置Ｘ１は、第１導体１、２つの第２導体２、半導体チップ３、ワイヤ４および樹脂パッケージ５を有している。   The semiconductor device X1 includes a first conductor 1, two second conductors 2, a semiconductor chip 3, wires 4, and a resin package 5.

第１導体１は、平面視矩形状の形態を有している。第１導体１の第１面１１は平坦面とされており、第１面１１が接続面を構成している。一方、第１導体１の第２面１２は、２つの凸部１３が設けられて凹凸状とされている。凸部１３の表面１４は平坦面とされており、この平坦面は、樹脂パッケージ５の底面５０から露出して端子面を構成している。第１導体１は、凸部１３が形成された部分以外は、厚み寸法が小さくされており、当該部分が薄肉部１５を構成している。   The first conductor 1 has a rectangular shape in plan view. The first surface 11 of the first conductor 1 is a flat surface, and the first surface 11 constitutes a connection surface. On the other hand, the 2nd surface 12 of the 1st conductor 1 is provided with two convex parts 13, and is made uneven. The surface 14 of the convex portion 13 is a flat surface, and this flat surface is exposed from the bottom surface 50 of the resin package 5 and constitutes a terminal surface. The thickness of the first conductor 1 is reduced except for the portion where the convex portion 13 is formed, and the portion constitutes the thin portion 15.

第２導体２は、直方体状の本体部２０から薄肉部２１が延出した形態とされている。この第２導体の第１面２２は、平坦面とされて接続面を構成している。第２面２３は、本体部２０が突出して凸面とされており、本体部２０の表面２４が樹脂パッケージ５の底面５０から露出して端子面を構成している。   The 2nd conductor 2 is made into the form which the thin part 21 extended from the rectangular parallelepiped main-body part 20. As shown in FIG. The first surface 22 of the second conductor is a flat surface and forms a connection surface. The second surface 23 protrudes from the main body portion 20 to be a convex surface, and the surface 24 of the main body portion 20 is exposed from the bottom surface 50 of the resin package 5 to constitute a terminal surface.

半導体チップ３は、図面上に表れていないが上面および下面に電極が形成されている。この半導体チップ３は、ハンダペーストや銀ペーストなどの導電性材料を用いた実装作業により第１導体１の接続面１１上に実装されている。半導体チップ３の下面には電極が形成されていることから、導電性材料を用いて第１導体１上に半導体チップ３を実装すれば、第１導体１と半導体チップ３の下面の電極とが導通する。一方、半導体チップ３の上面の電極は、ワイヤ４を介して第２導体２の接続面２２と導通接続されている。   The semiconductor chip 3 is not shown in the drawing, but has electrodes formed on the upper surface and the lower surface. The semiconductor chip 3 is mounted on the connection surface 11 of the first conductor 1 by a mounting operation using a conductive material such as solder paste or silver paste. Since the electrode is formed on the lower surface of the semiconductor chip 3, if the semiconductor chip 3 is mounted on the first conductor 1 using a conductive material, the first conductor 1 and the electrode on the lower surface of the semiconductor chip 3 are connected. Conduct. On the other hand, the electrode on the upper surface of the semiconductor chip 3 is conductively connected to the connection surface 22 of the second conductor 2 via the wire 4.

樹脂パッケージ５は、半導体チップ３およびワイヤ４を封止している。この樹脂パッケージ５の底面５０からは、上述したように端子面１４，２４が露出している。これにより、半導体装置Ｘ１が回路基板などに対して面実装可能とされている。また、第１および第２導体１，２は、薄肉部１５，２１を有しているので、この薄肉部１５，２１が樹脂パッケージ４に食い込むことによって樹脂パッケージ４と第１および第２導体１，２とが分離することが抑制されている。   The resin package 5 seals the semiconductor chip 3 and the wires 4. The terminal surfaces 14 and 24 are exposed from the bottom surface 50 of the resin package 5 as described above. As a result, the semiconductor device X1 can be surface-mounted on a circuit board or the like. Further, since the first and second conductors 1 and 2 have thin portions 15 and 21, the thin portions 15 and 21 bite into the resin package 4, whereby the resin package 4 and the first and second conductors 1 and 2. , 2 are prevented from separating.

以上の構成を有する半導体装置Ｘ１は、半導体装置製造用のフレームの製造工程、ダイボンディング工程、ワイヤボンディング工程、、フレームカット工程、樹脂パッケージング工程、およびダイシング工程（あるいはフレームカット工程）を経て製造される。なお、以下に説明する製造方法においては、上記した工程のうち、フレームの製造工程、ダイボンディング工程、ワイヤボンディング工程およびフレームカット工程が同一のフープラインにおいて行われるものとする。   The semiconductor device X1 having the above configuration is manufactured through a frame manufacturing process, a die bonding process, a wire bonding process, a frame cutting process, a resin packaging process, and a dicing process (or frame cutting process) for manufacturing a semiconductor device. Is done. In the manufacturing method described below, among the above-described processes, the frame manufacturing process, the die bonding process, the wire bonding process, and the frame cutting process are performed in the same hoop line.

図４に示したように、フープラインにおいては、ロール状に巻き取られたフープ状の板状導体６が、ロールＲから引き出されつつ支持台６０に沿ってピッチ送りされる。フレーム製造工程においては、板状導体６の搬送が停止した瞬間に、板状導体６に対して第１回目の打ち抜き加工、スタンピング加工、および第２回目の打ち抜き加工が施される。第１回目および第２回目の打ち抜き加工は、打ち抜き領域に対応して打ち抜き刃が形成された金型７０，７１を上方側から押し付けることにより行われる。スタンピング加工は、スタンピング領域に対応した凸部を有する金型７２を、下方側から押し付けることにより行われる。   As shown in FIG. 4, in the hoop line, the hoop-like plate-like conductor 6 wound up in a roll shape is pitched along the support base 60 while being drawn out from the roll R. In the frame manufacturing process, the first punching process, the stamping process, and the second punching process are performed on the plate conductor 6 at the moment when the conveyance of the plate conductor 6 is stopped. The first punching process and the second punching process are performed by pressing the dies 70 and 71 formed with punching blades corresponding to the punching region from above. The stamping process is performed by pressing a mold 72 having a convex portion corresponding to the stamping region from below.

第１回目の打ち抜き加工を施した場合には、たとえば図５（板状導体６を裏面側から見た状態を示してある）に示したように半導体装置Ｘ１における第１および第２導体１，２となるべき領域Ｅが複数形成される。各領域Ｅには、大小の貫通孔Ｅ１，Ｅ２が設けられている。大の貫通孔Ｅ１は、略矩形状の領域から半島部ｅ１が突出した形態とされているとともに、切欠ｅ２が形成されている。   When the first punching process is performed, the first and second conductors 1 and 2 in the semiconductor device X1 as shown in FIG. 5 (the state in which the plate-like conductor 6 is viewed from the back side) is shown, for example. A plurality of regions E to be 2 are formed. Each region E is provided with large and small through holes E1 and E2. The large through hole E1 has a shape in which a peninsula e1 protrudes from a substantially rectangular region, and is formed with a notch e2.

スタンピング加工においては、図６（板状導体６を裏面側から見た状態を示してある）に示したように半島部ｅ１、小の貫通孔Ｅ２における半島部ｅ1側の周辺部、および切欠ｅ２の周辺部が、板状導体６の厚みの半分程度にまで圧し潰されてスタンピング部ｅ３，ｅ４が形成される。これらのスタンピング部ｅ３，ｅ４は、後において半導体装置Ｘ１の薄肉部１５，２１を構成するものである。板状導体６には大小の貫通孔Ｅ１，Ｅ２や切欠ｅ２が設けられているから、スタンピング加工を施した場合には、上記した部位Ｅ１，Ｅ２，ｅ２を利用してスタンピング領域を拡げることができる。そのため、スタンピング領域に作用する応力がスタンピング領域が拡がることによって緩和されるため、形成されたスタンピング部ｅ３，ｅ４にはさほど大きな応力が残存することもなく、歪みの発生が抑制される。   In the stamping process, as shown in FIG. 6 (showing the state where the plate-like conductor 6 is viewed from the back side), the peninsula e1, the peripheral part on the peninsula e1 side in the small through hole E2, and the notch e2 Are stamped and crushed to about half the thickness of the plate-like conductor 6 to form stamping portions e3 and e4. These stamping portions e3 and e4 will later constitute the thin portions 15 and 21 of the semiconductor device X1. Since the plate-like conductor 6 is provided with large and small through-holes E1, E2 and a notch e2, when the stamping process is performed, the stamping region can be expanded using the above-described portions E1, E2, e2. it can. Therefore, the stress acting on the stamping region is relaxed by the expansion of the stamping region, so that a large amount of stress does not remain in the formed stamping portions e3 and e4, and the generation of distortion is suppressed.

第２回目の打ち抜き加工においては、図７（板状導体６を裏面側から見た状態を示してある）に示したように半導体装置Ｘ１における第１および第２導体１，２となるべき第１および第２部分１Ａ，２Ａやそれらを支持するフレームＦ１，Ｆ２，Ｆ３を除いた領域が打ち抜かれる。つまり、スタンピング部ｅ３，ｅ４の周縁部を含む不要部分が除去されてフレーム６Ａが形成される。このとき、半導体装置Ｘ１の薄肉部１５，２１となるべき薄肉部ｅ３′，ｅ４′が形成される。スタンピング部ｅ３，ｅ４については、周縁部の厚みが他の部分に比べて小さくてエッジがシャープではないが、その周縁部を打ち抜き加工により除去した薄肉部ｅ３′，ｅ４′では、厚みが一様で、エッジ（端面）が平坦面とされた薄肉部１５，２１を形成することができる。薄肉部１５，２１に限らず、第１部分１Ａの他の端面および第２部分２Ａの端面についても、平坦面とすることができる。このため、半導体装置Ｘ１が製造されたときに第１および第２部分１Ａ，２Ａの端面が樹脂パッケージ５から露出する場合には、図１５（ａ）に示したようにエッチング処理により端面が非平坦面になる場合に比べれば、その部分への樹脂バリの付着が抑制され、バリ取りも容易となる。また、エッチング処理を施す場合では、図１５（ｂ）を参照して説明したようにエッチング液の周り込みにより角部が丸まってしまうが、打ち抜き加工では、金型７１の打ち抜き刃の形状に則して第１部分１Ａの形状を設定できるため、図７に良く表れているように第１部分１Ａや第２部分２Ａの角部を直角に近づけることができる。そのため、第１部分１Ａの周縁により近いところまでを半導体チップ３の実装領域とすることができ、半導体チップ３の実装領域を大きく確保できるようになる、また第２部分２Ａにおけるワイヤボンディング領域を大きく確保できるようになる。   In the second punching process, the first and second conductors 1 and 2 in the semiconductor device X1 as shown in FIG. 7 (shown when the plate-like conductor 6 is viewed from the back side) are shown. The areas excluding the first and second portions 1A, 2A and the frames F1, F2, F3 supporting them are punched out. That is, unnecessary portions including peripheral portions of the stamping portions e3 and e4 are removed to form the frame 6A. At this time, thin portions e3 ′ and e4 ′ to be the thin portions 15 and 21 of the semiconductor device X1 are formed. Regarding the stamping portions e3 and e4, the thickness of the peripheral portion is smaller than the other portions and the edge is not sharp, but the thin portions e3 ′ and e4 ′ in which the peripheral portion is removed by punching processing have a uniform thickness Thus, it is possible to form the thin portions 15 and 21 whose edges (end surfaces) are flat. Not only the thin portions 15 and 21, but also the other end surface of the first portion 1A and the end surface of the second portion 2A can be flat surfaces. Therefore, when the end surfaces of the first and second portions 1A and 2A are exposed from the resin package 5 when the semiconductor device X1 is manufactured, the end surfaces are not etched by the etching process as shown in FIG. Compared to a flat surface, the resin burrs are prevented from adhering to the portion, and deburring is facilitated. Further, in the case of performing the etching process, as described with reference to FIG. 15B, the corner portion is rounded by the wrapping of the etching solution. Since the shape of the first portion 1A can be set, the corners of the first portion 1A and the second portion 2A can be brought close to a right angle as shown well in FIG. Therefore, it is possible to make the mounting region of the semiconductor chip 3 as far as the periphery of the first portion 1A, so that a large mounting region of the semiconductor chip 3 can be secured, and the wire bonding region in the second portion 2A is increased. It can be secured.

ダイボンディング工程は、図４に示したように下面の電極にハンダペーストなどの導電性材料が塗布された半導体チップ３を、吸着コレット７３を用いてリードフレーム６Ａの第１部分１Ａの一面側に載置した後に、加熱炉７４においてハンダペーストなどをリフローさせることにより行われる。   In the die bonding process, as shown in FIG. 4, the semiconductor chip 3 in which a conductive material such as solder paste is applied to the electrode on the lower surface is placed on one surface side of the first portion 1A of the lead frame 6A using the suction collet 73. After the mounting, this is performed by reflowing solder paste or the like in the heating furnace 74.

ワイヤボンディング工程は、既存のワイヤボンダーを用いて行われる。より具体的には、ワイヤボンディング工程は、ワイヤボンダーのキャピラリ７５から突出したワイヤ４の先端部を溶融させて半導体チップ３における上面の電極に押し付けた後、キャピラリ７５からワイヤを引出しつつ第２部分２Ａの上面（図７参照）にワイヤ４を押し付けて切断することにより行われる。   The wire bonding process is performed using an existing wire bonder. More specifically, in the wire bonding step, the tip of the wire 4 protruding from the capillary 75 of the wire bonder is melted and pressed against the electrode on the upper surface of the semiconductor chip 3, and then the second part is drawn out from the capillary 75. This is done by pressing the wire 4 against the upper surface of 2A (see FIG. 7) and cutting it.

板状導体６Ａでは、第１および第２部分１Ａ，２Ａでの歪みの発生が抑制されているために第１および第２部分１Ａ，２Ａにおけるダイボンディング部位やワイヤボンディング部位の平坦性が十分に確保されており、ダイボンディング工程およびワイヤボンディング工程を適切に行うことができる。   In the plate-like conductor 6A, since the occurrence of distortion in the first and second portions 1A and 2A is suppressed, the flatness of the die bonding portion and the wire bonding portion in the first and second portions 1A and 2A is sufficient. The die bonding process and the wire bonding process can be appropriately performed.

リードカット工程は、切断刃７６を有する金型を用いて行われ、これにより図８に示したように短寸のフレーム６Ｂが得られる。   The lead cut process is performed using a mold having a cutting blade 76, whereby a short frame 6B is obtained as shown in FIG.

樹脂パッケージング工程は、短寸のフレーム６Ｂに対して、上金型および下金型を用いて行われる。これらの金型は、型締め状態においてキャビティ空間を形成するものである。すなわち、樹脂パッケージング工程は、キャビティ空間内に半導体チップ３およびワイヤ４を収容した状態でキャビティ空間内に熱硬化性樹脂を注入した後に熱硬化性樹脂を熱硬化させることにより行われる。なお、樹脂パッケージング工程においては、全ての半導体チップ３を収容する１つのキャビティを形成可能な金型を用いて、全ての半導体チップ３に対して一括して樹脂封止を行ってもよいし、複数のキャビティを形成可能な金型を用いて、個々の半導体チップ３毎に個別に樹脂封止を行ってもよい。   The resin packaging process is performed on the short frame 6B using an upper mold and a lower mold. These molds form a cavity space in a clamped state. That is, the resin packaging process is performed by injecting a thermosetting resin into the cavity space in a state where the semiconductor chip 3 and the wire 4 are accommodated in the cavity space and then thermosetting the thermosetting resin. In the resin packaging process, all the semiconductor chips 3 may be collectively sealed with a mold that can form a single cavity that accommodates all the semiconductor chips 3. Alternatively, resin sealing may be performed for each individual semiconductor chip 3 using a mold capable of forming a plurality of cavities.

ダイシング工程は、ダイヤモンドカッタなどの既存の切断手段により、フレームＦ２，Ｆ３やこれに対応する樹脂封止部分を切断することにより行うことができる。これにより、図１ないし図３に示したような個々の半導体装置Ｘ１が複数得られる。また、個々の半導体チップ３に対して個別に樹脂パッケージ３を形成する場合には、必ずしも樹脂パッケージ３を切断する必要はなく、その場合にはダイシング工程は不要となる。その代わり、フレームＦ２，Ｆ３などを切断するためのフレームカット工程が必要となる。   The dicing process can be performed by cutting the frames F2 and F3 and the resin sealing portions corresponding to the frames F2 and F3 with an existing cutting means such as a diamond cutter. Thereby, a plurality of individual semiconductor devices X1 as shown in FIGS. 1 to 3 are obtained. Further, when the resin package 3 is individually formed for each semiconductor chip 3, it is not always necessary to cut the resin package 3, and in that case, the dicing process is not necessary. Instead, a frame cutting process for cutting the frames F2, F3, etc. is required.

以上に説明した半導体装置Ｘ１の製造方法では、打ち抜き加工とスタンピング加工とを組み合わせた機械的加工により、図７に示したような薄肉部を有するフレーム６Ａを製造することができる。このフレーム６Ａは、ダイボンディングやワイヤボンディングと同一のフープラインにおいて製造できるため、フープラインにより半導体装置製造用フレームを製造することのできないエッチング処理に比べれば、作業性が良くて製造コスト的に有利である。また、板状導体（フープ）に対するマスクの形成・除去も不要となるため、この点からも作業性が良くて製造コスト的に有利であるといえる。   In the manufacturing method of the semiconductor device X1 described above, the frame 6A having a thin portion as shown in FIG. 7 can be manufactured by mechanical processing combining punching processing and stamping processing. Since this frame 6A can be manufactured on the same hoop line as that for die bonding and wire bonding, it is more workable and advantageous in terms of manufacturing cost as compared with an etching process in which a semiconductor device manufacturing frame cannot be manufactured by the hoop line. It is. In addition, since it is not necessary to form and remove the mask from the plate-like conductor (hoop), it can be said that the workability is good and the manufacturing cost is advantageous.

上記した半導体装置の製造方法は、図１ないし図３を参照して説明した半導体装置Ｘ１に限らず、薄肉部を有する半導体装置の全般、たとえば図９ないし図１４に例示した半導体装置Ｘ２〜Ｘ１５にも適用可能である。   The manufacturing method of the semiconductor device described above is not limited to the semiconductor device X1 described with reference to FIGS. 1 to 3, but the whole semiconductor device having a thin portion, for example, the semiconductor devices X2 to X15 illustrated in FIGS. It is also applicable to.

図９に示した半導体装置Ｘ２は、第１および第２導体１，２を有し、第１導体１に薄肉部１５が形成され、第１導体１に半導体チップ３が搭載されている点において先に説明した半導体装置Ｘ１と共通している。その一方で、半導体装置Ｘ２においては、ワイヤ４に代えて、導体片を折り曲げた接続片４′によって半導体チップ３の上面の電極と第２導体２との導通接続が図られている点において異なっている。   The semiconductor device X2 shown in FIG. 9 has first and second conductors 1 and 2, a thin portion 15 is formed on the first conductor 1, and a semiconductor chip 3 is mounted on the first conductor 1. This is common with the semiconductor device X1 described above. On the other hand, in the semiconductor device X2, a conductive connection between the electrode on the upper surface of the semiconductor chip 3 and the second conductor 2 is achieved by a connecting piece 4 ′ obtained by bending a conductor piece instead of the wire 4. ing.

図１０に示した半導体装置Ｘ３は、第１導体１と第２導体２との間を跨ぐようにして半導体チップ３が搭載されている点において半導体装置Ｘ１と異なっている。半導体装置Ｘ３においても、図９に示した半導体装置Ｘ２と同様に、ワイヤ４に代えて導体片４′を用いて半導体チップ３と第２導体２との間の導通接続を図ったものであってもよい。   The semiconductor device X3 shown in FIG. 10 is different from the semiconductor device X1 in that the semiconductor chip 3 is mounted so as to straddle between the first conductor 1 and the second conductor 2. Similarly to the semiconductor device X2 shown in FIG. 9, the semiconductor device X3 uses a conductor piece 4 ′ instead of the wire 4 to achieve a conductive connection between the semiconductor chip 3 and the second conductor 2. May be.

図１１に示した半導体装置Ｘ４は、第１導体１の全体が薄肉部１５とされ、この第１導体１の両サイドに第２導体２が配置されている。この半導体装置Ｘ４においては、第１導体１の一部が図１１に仮想線で示したように凸部とされていてもよい。もちろん、ワイヤ４に代えて図９に示した半導体装置Ｘ２のように導体片４′を用いて半導体チップ３と第２導体２との間を導通接続してもよい。   In the semiconductor device X4 shown in FIG. 11, the entire first conductor 1 is a thin portion 15, and the second conductor 2 is disposed on both sides of the first conductor 1. In the semiconductor device X4, a part of the first conductor 1 may be a convex portion as indicated by a virtual line in FIG. Of course, the semiconductor chip 3 and the second conductor 2 may be conductively connected by using a conductor piece 4 ′ as in the semiconductor device X 2 shown in FIG. 9 instead of the wire 4.

図１２に示した半導体装置Ｘ５は、第１および第２導体１，２の双方が薄肉部１５，２５を有するとともに、これらの導体部を繋ぐようにして半導体チップ３が搭載されている。そして、第１および第２導体１，２とはワイヤ４を介して半導体チップ３が導通接続されている。半導体装置Ｘ５においては、ワイヤ４を用いずに、半導体チップ３をフェイスダウン方式で実装し、半導体チップ３の電極と第１および第２導体１，２との間を接続したものであってもよい。   In the semiconductor device X5 shown in FIG. 12, both the first and second conductors 1 and 2 have thin portions 15 and 25, and the semiconductor chip 3 is mounted so as to connect these conductor portions. The semiconductor chip 3 is electrically connected to the first and second conductors 1 and 2 via wires 4. In the semiconductor device X5, even if the semiconductor chip 3 is mounted by the face-down method without using the wire 4, and the electrode of the semiconductor chip 3 and the first and second conductors 1 and 2 are connected. Good.

図１３（ａ）ないし（ｅ）に示した半導体装置Ｘ６〜Ｘ１０のように、先に説明した半導体装置Ｘ１〜Ｘ５において、第１および第２導体１，２に端部を上方側から下方に凹入させて、第１および第２導体１，２の端部に薄肉部１５′２５′を形成したものであってもよい。   As in the semiconductor devices X6 to X10 shown in FIGS. 13A to 13E, in the semiconductor devices X1 to X5 described above, the end portions of the first and second conductors 1 and 2 are extended from the upper side to the lower side. A thin wall portion 15'25 'may be formed at the end portions of the first and second conductors 1 and 2 by being recessed.

さらに、図１４（ａ）ないし（ｅ）に示した半導体装置Ｘ１１〜Ｘ１５のように、第１および第２導体１，２の端子面１４，２３が樹脂パッケージ５の外部に延出した形態のものであっても、薄肉部を有する限りは、本願発明の技術思想を適用することができる。もちろん、端子面１４，２３の全体が樹脂パッケージ５の外部に延出しているものであってもよい。   Further, as in the semiconductor devices X11 to X15 shown in FIGS. 14A to 14E, the terminal surfaces 14 and 23 of the first and second conductors 1 and 2 extend to the outside of the resin package 5. Even if it is a thing, as long as it has a thin part, the technical idea of this invention can be applied. Of course, the entire terminal surfaces 14 and 23 may extend to the outside of the resin package 5.

Ｘ１〜Ｘ１５ 半導体装置
１ 第１導体
１１ （第１導体の）接続面
１４ （第１導体の）端子面
１５ 薄肉部
２ 第２導体
２１ 薄肉部
２２ （第２導体の）接続面
２４ （第２導体の）端子面
５ 樹脂パッケージ
５０ （樹脂パッケージの）底面
６ 板状導体
６Ａ （フープ状の）フレーム
６Ｂ （短寸の）フレーム
Ｅ２ 貫通孔
ｅ２ 切欠
ｅ３ スタンピング部 X1 to X15 Semiconductor device 1 First conductor 11 (first conductor) connection surface 14 (first conductor) terminal surface 15 Thin portion 2 Second conductor 21 Thin portion 22 (second conductor) connection surface 24 (second) Terminal surface of conductor 5 Resin package 50 Bottom surface of resin package 6 Plate conductor 6A (Hoop) frame 6B (Short) frame E2 Through hole e2 Notch e3 Stamping part

Claims (22)

リードフレームを用いて半導体装置を製造する方法であって、
上記リードフレームは、
板状導体に対して貫通孔を形成する貫通孔形成工程と、
上記板状導体の厚みに対して相対的に厚みが小さく、上記貫通孔の内方を向く自由端を有する薄状部を形成する薄状部形成工程と、
上記板状導体に対して、少なくとも上記薄状部の一部を除去して当該薄状部に由来する薄肉部を形成する不要部分除去工程と、
上記薄肉部の上面ないしこれに連続する上記薄肉部以外の部分の上面にわたって半導体チップを搭載する工程と、
を含んで製造されることを特徴とする、半導体装置の製造方法。 A method of manufacturing a semiconductor device using a lead frame,
The lead frame is
A through hole forming step of forming a through hole with respect to the plate-shaped conductor;
A thin portion forming step of forming a thin portion having a relatively small thickness with respect to the thickness of the plate conductor and having a free end facing the inside of the through hole;
For the plate-like conductor, at least a part of the thin part is removed to form a thin part derived from the thin part, and an unnecessary part removing step,
Mounting the semiconductor chip over the upper surface of the thin portion or the upper surface of the portion other than the thin portion continuous with the thin portion; and
Characterized Rukoto be comprise producing method of manufacturing a semiconductor device. リードフレームを用いて半導体装置を製造する方法であって、
上記リードフレームは、
板状導体に対して貫通孔を形成する貫通孔形成工程と、
半導体チップを搭載する面の反対側からの加工により、上記貫通孔に沿って上記板状導体の厚みに対して相対的に厚みが小さい薄状部を形成する薄状部形成工程と、
上記板状導体に対して、少なくとも上記薄状部の一部を除去して当該薄状部に由来する薄肉部を形成する不要部分除去工程と、
上記薄肉部の上面ないしこれに連続する上記薄肉部以外の部分の上面にわたって半導体チップを搭載する工程と、
を含んで製造されることを特徴とする、半導体装置の製造方法。 A method of manufacturing a semiconductor device using a lead frame,
The lead frame is
A through hole forming step of forming a through hole with respect to the plate-shaped conductor;
A thin part forming step of forming a thin part having a relatively small thickness with respect to the thickness of the plate conductor along the through hole by processing from the opposite side of the surface on which the semiconductor chip is mounted;
For the plate-like conductor, at least a part of the thin part is removed to form a thin part derived from the thin part, and an unnecessary part removing step,
Mounting the semiconductor chip over the upper surface of the thin portion or the upper surface of the portion other than the thin portion continuous with the thin portion; and
A method for manufacturing a semiconductor device , comprising: リードフレームを用いて半導体装置を製造する方法であって、
上記リードフレームは、
板状導体に対して内方に向けて突出する半島部を有する貫通孔を形成する貫通孔形成工程と、
上記半島部に、上記板状導体の厚みに対して相対的に厚みが小さい薄状部を形成する薄状部形成工程と、
上記板状導体に対して、少なくとも上記薄状部の一部を除去して当該薄状部に由来する薄肉部を形成する不要部分除去工程と、
上記薄肉部の上面ないしこれに連続する上記薄肉部以外の部分の上面にわたって半導体チップを搭載する工程と、
を含んで製造されることを特徴とする、半導体装置の製造方法。 A method of manufacturing a semiconductor device using a lead frame,
The lead frame is
A through hole forming step of forming a through hole having a peninsula projecting inward with respect to the plate-shaped conductor;
A thin part forming step of forming a thin part having a relatively small thickness with respect to the thickness of the plate conductor on the peninsula part,
For the plate-like conductor, at least a part of the thin part is removed to form a thin part derived from the thin part, and an unnecessary part removing step,
Mounting the semiconductor chip over the upper surface of the thin portion or the upper surface of the portion other than the thin portion continuous with the thin portion; and
A method for manufacturing a semiconductor device , comprising: 上記薄状部は、上記半島部の先端方に形成される、請求項３に記載の半導体装置の製造方法。 The thin shape section, Ru is formed on the tip side of the peninsula, a method of manufacturing a semiconductor device according to claim 3. 上記貫通孔形成工程では、上記半島部の基端部に位置する第２の貫通孔が同時に形成される、請求項４に記載の半導体装置の製造方法。 In the through hole forming step, the second through-hole located in the proximal end of the peninsula portion Ru simultaneously formed, the manufacturing method of the semiconductor device according to claim 4. 上記薄状部は、上記半島部の先端方に形成される部分から、上記半島部の幅方向中央領域を通って上記第２の貫通孔までつながるように形成される、請求項５に記載の半導体装置の製造方法。 The thin-shaped section, the portion formed on the tip side of the peninsula portion through the widthwise center area of the peninsula portion Ru is formed so as to be connected to the second through-hole, according to claim 5 A method for manufacturing a semiconductor device. 上記不要部分除去工程では、上記半島部に由来する幅方向左右一対の厚肉部と、上記薄状部に由来する薄肉部とが、全体として矩形半島状に形成される、請求項６に記載の半導体装置の製造方法。 Above the unnecessary portion removing step, the width direction a pair of left and right thick portions derived from the peninsula, a thin portion from the thin shape section, Ru is formed as a whole in a rectangular peninsular, claim 6 Semiconductor device manufacturing method. リードフレームを用いて半導体装置を製造する方法であって、
上記リードフレームは、
板状導体に対して、外方に向けて凹入する切欠を有する貫通孔を形成する貫通孔形成工程と、
上記板状導体の厚みに対して相対的に厚みが小さく、上記切欠を埋める薄状部を形成する薄状部形成工程と、
上記板状導体に対して、少なくとも上記薄状部の一部を除去して当該薄状部に由来する薄肉部を形成する不要部分除去工程と、を含んで製造され、
上記不要部分除去工程では、上記切欠の幅方向両側に位置していた部分により形成された一対の矩形厚肉部の各先端方から互いに向かい合って延びる一対の上記薄肉部が形成されることを特徴とする、半導体装置の製造方法。 A method of manufacturing a semiconductor device using a lead frame,
The lead frame is
A through hole forming step for forming a through hole having a notch recessed toward the outside with respect to the plate-shaped conductor;
A thin part forming step of forming a thin part that has a relatively small thickness with respect to the thickness of the plate conductor and fills the notch,
An unnecessary part removing step for removing at least a part of the thin part and forming a thin part derived from the thin part with respect to the plate-shaped conductor,
In the unnecessary portion removing step, a pair of the thin portions extending from each front end of the pair of rectangular thick portions formed by the portions located on both sides in the width direction of the notches are formed. A method for manufacturing a semiconductor device. リードフレームを用いて半導体装置を製造する方法であって、
上記リードフレームは、
板状導体に対して、内方に向けて突出する半島部と、当該半島部と対向する部位において外方に向けて凹入する切欠を有する貫通孔を形成する貫通孔形成工程と、
上記半島部の先端方に、上記板状導体の厚みに対して相対的に厚みが小さい第１の薄状部と、上記切欠を埋め、上記板状導体に対して相対的に厚みが小さい第２の薄状部とを形成する薄状部形成工程と、
上記板状導体に対して、少なくとも上記第１の薄状部の一部および上記第２の薄状部の一部を除去して、第１および第２の薄状部にそれぞれ由来する薄肉部を形成する不要部分除去工程と、
を含み、
上記貫通孔形成工程では、上記半島部の基端部に位置する第２の貫通孔が同時に形成され、
上記第１の薄状部は、上記半島部の先端方に形成される部分から、上記半島部の幅方向中央領域を通って上記第２の貫通孔までつながるように形成され、
上記不要部分除去工程では、上記半島部に由来する幅方向左右一対の厚肉部と、上記第１の薄状部に由来する第１の薄肉部とが、全体として矩形半島状の第１部分として形成されるとともに、上記切欠の幅方向両側に位置していた部分により形成された一対の矩形厚肉部の各先端方から互いに向かい合って延びる一対の上記第２の薄状部に由来する第２の薄肉部とが、全体として矩形外形をもつ第２部分として形成されることを特徴とする、半導体装置の製造方法。 A method of manufacturing a semiconductor device using a lead frame,
The lead frame is
A penetrating hole forming step for forming a penetrating hole having a notch recessed toward the outside in a portion facing the peninsula portion, and a peninsula portion projecting inward toward the plate-like conductor,
A first thin portion having a relatively small thickness relative to the thickness of the plate-shaped conductor and a first portion having a relatively small thickness with respect to the plate-shaped conductor are embedded at the distal end of the peninsula portion. A thin portion forming step for forming two thin portions;
Thin portions derived from the first and second thin portions by removing at least part of the first thin portion and part of the second thin portion from the plate-like conductor, respectively. An unnecessary portion removing step of forming
Including
In the through hole forming step, a second through hole located at the base end of the peninsula is formed at the same time,
The first thin portion is formed so as to be connected to the second through hole from the portion formed at the tip of the peninsula portion through the central region in the width direction of the peninsula portion,
In the unnecessary portion removing step, the pair of left and right thick portions derived from the peninsula portion and the first thin portion derived from the first thin portion are rectangular peninsula-shaped first portions as a whole. And a pair of second thin portions extending from the front ends of the pair of rectangular thick portions formed by the portions located on both sides in the width direction of the notches. The method of manufacturing a semiconductor device , wherein the two thin-walled portions are formed as a second portion having a rectangular outer shape as a whole . 上記第１部分と上記第２部分とは、同一幅を有している、請求項９に記載の半導体装置の製造方法。The method for manufacturing a semiconductor device according to claim 9, wherein the first portion and the second portion have the same width. 上記第１部分の第１面は平面であり、当該第１面と反対側の第２面は、上記左右一対の厚肉部が凸部を形成しているとともに、上記第２部分の第１面は平面であり、当該第１面と反対側の第２面は、上記一対の矩形厚肉部が凸部を形成している、請求項１０に記載の半導体装置の製造方法。The first surface of the first portion is a flat surface, and the second surface opposite to the first surface has the pair of left and right thick portions forming convex portions, and the first portion of the second portion. 11. The method of manufacturing a semiconductor device according to claim 10, wherein the surface is a flat surface, and the second surface opposite to the first surface has the pair of rectangular thick portions forming protrusions. 上記第１部分の第１面には、半導体チップが搭載され、上記第２部分の第１面には、上記半導体チップに導通するワイヤが接続される、請求項１１に記載の半導体装置の製造方法。The semiconductor device manufacturing method according to claim 11, wherein a semiconductor chip is mounted on the first surface of the first portion, and a wire conducting to the semiconductor chip is connected to the first surface of the second portion. Method. 上記第１部分、上記第２部分、上記半導体チップおよび上記ワイヤが、樹脂封止されて樹脂パッケージング工程が行われる、請求項１２に記載の半導体装置の製造方法。The method of manufacturing a semiconductor device according to claim 12, wherein the first part, the second part, the semiconductor chip, and the wire are resin-sealed and a resin packaging process is performed. 上記樹脂パッケージング工程においては、上記第１部分の第２面の凸部と、上記第２部分の第２面の凸部とが、合計４つの端子として樹脂パッケージの底面に露出させられる、請求項１３に記載の半導体装置の製造方法。In the resin packaging step, the convex portion of the second surface of the first portion and the convex portion of the second surface of the second portion are exposed on the bottom surface of the resin package as a total of four terminals. Item 14. A method for manufacturing a semiconductor device according to Item 13. 上記合計４つの端子が、樹脂パッケージの矩形底面の４隅に対応して位置するようにダイシングされる、請求項１４に記載の半導体装置の製造方法。The method of manufacturing a semiconductor device according to claim 14, wherein the total four terminals are diced so as to correspond to four corners of a rectangular bottom surface of the resin package. 上記リードフレームは連続しており、当該リードフレームにより、複数の半導体装置が製造される、請求項１ないし１５のいずれかに記載の半導体装置の製造方法。16. The method of manufacturing a semiconductor device according to claim 1, wherein the lead frame is continuous, and a plurality of semiconductor devices are manufactured by the lead frame. 請求項１ないし１６のいずれかに記載の方法によって製造されたことを特徴とする、半導体装置。A semiconductor device manufactured by the method according to claim 1. 端子面および半導体チップと機械的または電気的に接続される接続面のうちの少なくとも一方を有する複数の導体を備えるとともに、上記端子面が露出または延出するようにして上記半導体チップが樹脂パッケージ内に封止された半導体装置であって、上記複数の導体を半導体装置製造用のフレームから形成し、かつ上記複数の導体のうちの少なくとも１つが薄肉部を有する半導体装置を製造する方法において、The semiconductor chip includes a plurality of conductors having at least one of a terminal surface and a connection surface mechanically or electrically connected to the semiconductor chip, and the semiconductor chip is disposed in the resin package such that the terminal surface is exposed or extended. In the method of manufacturing a semiconductor device, wherein the plurality of conductors are formed from a frame for manufacturing a semiconductor device, and at least one of the plurality of conductors has a thin portion.
上記半導体装置製造用のフレームは、板状導体に対して貫通孔を形成した後に半導体チップを搭載する面の反対側から加工を施して相対的に厚みが小さく、かつ上記フレームにつながる基端から先端の自由端まで延びる薄状部を形成し、その後に上記薄状部の不要部分を除去して上記薄肉部を形成することにより製造され、The frame for manufacturing the semiconductor device has a relatively small thickness by processing from the side opposite to the surface on which the semiconductor chip is mounted after forming a through hole in the plate-like conductor, and from the base end connected to the frame It is manufactured by forming a thin portion that extends to the free end of the tip, and then removing the unnecessary portion of the thin portion to form the thin portion,
上記半導体チップは、上記薄肉部の上面ないしこれに連続する上記薄肉部以外の部分の上面にわたって搭載されることを特徴とする、半導体装置の製造方法。The method of manufacturing a semiconductor device, wherein the semiconductor chip is mounted over an upper surface of the thin portion or an upper surface of a portion other than the thin portion continuous to the thin portion. 上記貫通孔の形成においては、第１導体となるべき領域の周りに位置するとともに、上記薄状部形成の際の上記薄状部の上記自由端の拡がりを許容する貫通孔を形成する、請求項１８に記載の半導体装置の製造方法。In the formation of the through-hole, a through-hole that is located around a region to be the first conductor and that allows the free end of the thin portion to be widened when the thin portion is formed is formed. Item 19. A method for manufacturing a semiconductor device according to Item 18. 請求項１８または１９の方法によって製造される半導体装置であって、上記薄肉部を有する上記導体は、上記薄肉部が上記樹脂パッケージ中に埋設されるようにしてその一面が上記端子面として上記樹脂パッケージの底面に面一に露出していることを特徴とする、半導体装置。20. The semiconductor device manufactured by the method according to claim 18 or 19, wherein the conductor having the thin-walled portion has the one surface serving as the terminal surface such that the thin-walled portion is embedded in the resin package. A semiconductor device characterized by being exposed flush with a bottom surface of a package. 上記樹脂パッケージの底面は矩形状であり、その底面には、４つ以下の上記端子面が面一状に露出している、請求項２０に記載の半導体装置。21. The semiconductor device according to claim 20, wherein the bottom surface of the resin package has a rectangular shape, and four or less of the terminal surfaces are exposed on the bottom surface. ロール状に巻き取られたフープ状の板状導体を用いて半導体装置を製造する方法であって、A method of manufacturing a semiconductor device using a hoop-shaped plate-shaped conductor wound up in a roll shape,
上記板状導体に対して貫通孔を形成する貫通孔形成工程と、A through hole forming step of forming a through hole with respect to the plate-shaped conductor;
上記板状導体の厚みに対して相対的に厚みが小さく、上記貫通孔の内方を向く自由端を有する薄状部を形成する薄状部形成工程と、A thin portion forming step of forming a thin portion having a relatively small thickness with respect to the thickness of the plate conductor and having a free end facing the inside of the through hole;
上記板状導体に対して、少なくとも上記薄状部の一部を除去して当該薄状部に由来する薄肉部を形成する不要部分除去工程と、For the plate-like conductor, at least a part of the thin part is removed to form a thin part derived from the thin part, and an unnecessary part removing step,
上記薄肉部の上面ないしこれに連続する上記薄肉部以外の部分の上面にわたって半導体チップを搭載する工程と、Mounting the semiconductor chip over the upper surface of the thin portion or the upper surface of the portion other than the thin portion continuous with the thin portion; and
を含んで製造されることを特徴とする、半導体装置の製造方法。A method for manufacturing a semiconductor device, comprising:
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