JP5325452B2 - Switch drive device - Google Patents

Description

  The present invention relates to a switch driving device including an overcurrent protection circuit.

  Conventionally, many switching regulators are provided with an overcurrent protection circuit as one of abnormality protection means. FIG. 12 is a circuit block diagram showing a conventional example of a switching regulator provided with an overcurrent protection circuit. Note that the conventional overcurrent protection circuit constantly monitors the current i flowing through the switching element Q1 (power transistor) while the switching regulator is operating, and performs switching when detecting that this has entered an overcurrent state. The element Q1 is forcibly turned off.

Patent document 1 can be mentioned as an example of the prior art relevant to the above.
JP 2002-153047 A

  Certainly, in the case of the above conventional switching regulator, even if an overcurrent caused by an output short circuit or the like occurs, the switching element is forcibly turned off by using an overcurrent protection circuit. It is possible to increase the safety of the device by shutting down the output operation.

  By the way, the above conventional switching regulator performs on / off control of the switching element Q1 according to the gate signal SG, thereby generating a rectangular-wave-like switch voltage Vsw from the input voltage Vin, and by rectifying and smoothing the switch voltage Vsw. The desired output voltage Vout is generated.

  At this time, since the current path through the switching element Q1 is conducted during the ON period of the switching element Q1, the current i flows through the switching element Q1, but during the OFF period of the switching element Q1, the switching element Q1 Since the current path via is interrupted, the current i flowing through the switching element Q1 has a zero value (see FIG. 13).

  However, the overcurrent protection circuit provided in the conventional switching regulator is configured to always monitor the current i flowing through the switching element Q1 without depending on the on / off state of the switching element Q1. In such a configuration, even when the switching element Q1 is turned off and the current path that generates the overcurrent is interrupted, the overcurrent protection circuit is always activated and consumes unnecessary circuit current. Was. In particular, at the time of light load or no load at which the switching pulse generation frequency of the gate signal SG is reduced, the ratio of the current consumption of the overcurrent protection circuit to the current consumption of the entire switching regulator increases, and thus the above-described problem is apparent. It was converted. Such a problem is not limited to a switching regulator, but is common to all switch drive devices including an overcurrent protection circuit.

  In view of the above problems, an object of the present invention is to provide a switch driving device capable of reducing waste of current in an overcurrent protection circuit.

  In order to achieve the above object, a switch drive device according to the present invention is a switch drive device that performs on / off control of a switching element, and monitors overcurrent flowing through the switching element to perform overcurrent protection. A protection circuit; and an enable control circuit that activates the overcurrent protection circuit when the switching element is on and deactivates the overcurrent protection circuit when the switching element is off. 1).

  In the switch drive device having the first configuration, the enable control circuit uses a pulse signal used for on / off control of the switching element as an enable signal for the overcurrent protection circuit (second configuration). ).

  In the switch driving device having the second configuration, the pulse signal is a first logic when the switching element is turned on, and a second logic when the switching element is turned off. The enable control circuit may have a configuration (third configuration) that is a delay circuit that generates the enable signal by delaying the timing at which the pulse signal is set to the second logic.

  In the switch driving device having the third configuration, when the pulse signal is continuously oscillated, the delay circuit always maintains the overcurrent protection circuit in an operating state, and the pulse signal is intermittently oscillated. It is preferable to adopt a configuration (fourth configuration) in which a delay time is set so that the overcurrent protection circuit is inactive only when

  With the switch drive device according to the present invention, waste of current in the overcurrent protection circuit can be reduced.

  FIG. 1 is a circuit block diagram showing an embodiment of a switching regulator according to the present invention. As shown in the figure, the switching regulator of this embodiment includes a switching regulator IC 100, a diode (Schottky diode) D1, an inductor L1, resistors R1 to R4, and capacitors C1 and C2 that are externally connected thereto. It consists of

  The switching regulator IC 100 includes an internal voltage generation unit 1, a reference voltage generation unit 2, a soft start voltage generation unit 3, an error amplifier 4, a PWM [Pulse Width Modulation] comparator 5, a slope voltage generation unit 6, and an oscillator. 7, OR operator 8, reset priority RS flip-flop 9, pre-driver 10, P-channel MOS [Metal Oxide Semiconductor] field effect transistor 11, sense resistor 12 (resistance value R), Comparator 13, DC voltage source 14 (electromotive voltage Vth1), delay circuit 15, latch circuit 16, timer circuit 17, constant current source 18, N-channel MOS field effect transistors 19 and 20, and diode array 21, a P-channel MOS field effect transistor 22, a resistor 23, a low voltage driver 24, a comparator A motor 25, a DC voltage source 26 (electromotive voltage Vth2), the made by integrating a switch driving unit that performs on / off control of the switching element (transistor 11). In the present embodiment, the configuration in which the transistor 11 is incorporated in the switching regulator IC 100 will be described as an example. However, the configuration of the present invention is not limited to this, and the transistor 11 may be externally attached. Absent.

  The internal voltage generation unit 1 is a unit that generates a predetermined internal voltage Vreg from the input voltage Vin and supplies it to each unit (such as the reference voltage generation unit 2) of the switching regulator IC 100. The circuit configuration and operation of the internal voltage generator 1 will be described in detail later.

  The reference voltage generator 2 is means for generating a predetermined reference voltage Vref from the internal voltage Vreg and outputting it to the first non-inverting input terminal (+) of the error amplifier 4.

  The soft start voltage generation unit 3 is a means for generating a soft start voltage Vss that gradually increases from the time of activation of the switching regulator IC 100 and outputting it to the second non-inverting input terminal (+) of the error amplifier 4.

  The error amplifier 4 has a reference voltage Vref applied to the first non-inverting input terminal (+) and a soft start voltage Vss applied to the second non-inverting input terminal (+), whichever is lower, and the inverting input. An error voltage ERR is generated by amplifying the difference between the feedback voltage Vfb (the divided voltage of the output voltage Vout drawn from the connection node between the resistor R1 and the resistor R2) applied to the end (−), and this is generated as a PWM comparator. 5 is a means for outputting to the inverting input terminal (−). That is, after the switching regulator IC 100 is activated, the difference between the soft start voltage Vss and the feedback voltage Vfb is amplified until the soft start voltage Vss reaches the reference voltage Vref. After reaching Vref, the difference between the reference voltage Vref and the feedback voltage Vfb is amplified. A phase compensation resistor R3 and a capacitor C2 are externally connected to the output terminal of the error amplifier 4.

  The PWM comparator 5 compares the slope voltage SL applied to the non-inverting input terminal (+) and the error voltage ERR applied to the inverting input terminal (−) to generate a comparison signal CMP, and performs an OR operation on the comparison signal CMP. Means for outputting to the first input terminal of the device 8. FIG. 2 is a timing chart for explaining the generation operation of the pulse signal PWM used for on / off control of the transistor 11. In FIG. 2, in order from the top, the error voltage ERR, the slope voltage SL, the comparison signal CMP (the reset signal R of the RS flip-flop 9), the clock signal CLK (the set signal S of the RS flip-flop 9), and the pulse signal The PWM (the output signal Q of the RS flip-flop 9) is depicted. As shown in FIG. 2, when the slope voltage SL is higher than the error voltage ERR, the comparison signal CMP is at a high level, and when the slope voltage SL is lower than the error voltage ERR, the comparison signal CMP is at a low level.

  The slope voltage generator 6 is means for generating the slope voltage SL shown in FIG. 2 based on the clock signal CLK and outputting it to the non-inverting input terminal (+) of the PWM comparator 5. In FIG. 2, the configuration for generating the triangular wave-shaped slope voltage SL is taken as an example. However, the configuration of the present invention is not limited to this, and a configuration for generating the sawtooth-shaped slope voltage SL may be used. Absent.

  The oscillator 7 is means for generating a rectangular wave clock signal CLK and outputting it to the slope voltage generator 6 and the set end (S) of the RS flip-flop 9. The oscillation frequency of the clock signal CLK can be arbitrarily adjusted according to the resistance value of the resistor R4.

  The logical sum operator 8 generates a logical sum operation signal OR of the comparison signal CMP applied to the first input terminal and the overcurrent protection signal S3 applied to the second input terminal, and outputs the logical sum operation signal OR to the RS flip-flop 9. Output to the reset terminal (R). More specifically, when the overcurrent protection signal S3 is at a low level, the comparison signal CMP is passed through the logical sum calculator 8, and the comparison signal CMP is supplied to the reset terminal (R) of the RS flip-flop 9. The OR operation signal OR having the same logic level is input. On the other hand, when the overcurrent protection signal S3 is at a high level, the comparison signal CMP is masked by the logical sum calculator 8, and the reset terminal (R) of the RS flip-flop 9 is not dependent on the comparison signal CMP. Therefore, the high-level OR operation signal OR is always input.

  As shown in FIG. 2, the RS flip-flop 9 sets the pulse signal PWM output from the output terminal (Q) to a high level using the rising edge of the clock signal CLK input to the set terminal (S) as a trigger, The pulse signal PWM output from the output terminal (Q) is reset to a low level with the rising edge of the OR operation signal OR (corresponding to the comparison signal CMP when no overcurrent is detected) input to the reset terminal (R) as a trigger. Means. When the output voltage Vout is maintained in the vicinity of the target voltage value during light load or no load, the error voltage ERR is always below the lower limit value of the slope voltage SL as shown in FIG. Thus, the pulse signal PWM is automatically shifted from the continuous oscillation state to the intermittent oscillation state.

  The pre-driver 10 is means for increasing the driving capability of the pulse signal PWM to generate the gate signal SG and supplying the gate signal SG to the gate of the transistor 11. In this embodiment, the pre-driver 10 functions as the upper drive voltage VH (= An inverter that drives the gate signal SG in a pulse manner is used between the input voltage Vin) and the lower drive voltage VL. That is, the pulse signal PWM and the gate signal SG are signals that are logically inverted from each other.

  The transistor 11 is a switching element (power transistor) that is on / off controlled according to a gate signal SG (and thus a pulse signal PWM). The source of the transistor 11 is connected to the application terminal of the input voltage Vin via the sense resistor 12. The drain of the transistor 11 is connected to the cathode of the diode D1 and one end of the inductor L1. The anode of the diode D1 is connected to the ground terminal. The other end of the inductor L1 is connected to a load (not shown) as an output terminal of the output voltage Vout, and is also connected to the ground terminal through a path through the capacitor C1 and through the resistors R1 and R2. Yes.

  Note that the rectangular-wave-like switch voltage Vsw drawn from the source of the transistor 11 is rectified and smoothed by the diode D1, the inductor L1, and the capacitor C1, and is supplied as an output voltage Vout to a load (not shown). Further, the output voltage Vout is divided by a resistance dividing circuit including a resistor R1 and a resistor R2, and is output to the error amplifier 4 as the feedback voltage Vfb described above. By such feedback control, in the switching regulator of this embodiment, the input voltage Vin is stepped down to generate a desired output voltage Vout.

  The sense resistor 12 is means for detecting the current i flowing through the transistor 11 as a voltage signal, and is connected between the application terminal of the input voltage Vin and the source of the transistor 11.

  The non-inverting input terminal (+) of the comparator 13 is connected to the negative terminal of the DC voltage source 14. The positive terminal of the DC voltage source 14 is connected to the input terminal of the input voltage Vin (the high potential terminal of the sense resistor 12). The inverting input terminal (−) of the comparator 13 is connected to the source of the transistor 11 (the low potential terminal of the sense resistor 12). That is, the comparator 13 has a threshold voltage (= Vin−Vth1) applied to the non-inverting input terminal (+) and one end voltage (= Vin−i × R) of the sense resistor 12 applied to the inverting input terminal (−). ) To generate an overcurrent detection signal S1 and output it to the latch circuit 16 as an overcurrent detection means (a circuit element of an overcurrent protection circuit). Note that while the voltage drop (i × R) at the sense resistor 12 is smaller than the electromotive voltage Vth1 of the DC voltage source 14, the overcurrent detection signal S1 is maintained at a low level. When the drop (i × R) becomes larger than the electromotive voltage Vth1 of the DC voltage source 14, the overcurrent detection signal S1 is transited to a high level.

  The DC voltage source 14 is a means for setting an overcurrent detection threshold voltage (= Vin−Vth1), and is connected between the input terminal of the input voltage Vin and the non-inverting input terminal (+) of the comparator 13. Yes.

  The delay circuit 15 is a means for generating an enable signal EN for the comparator 13 by delaying the timing at which the pulse signal PWM is set to the low level. The operation of the delay circuit 15 will be described later.

  The latch circuit 16 uses the rising edge of the overcurrent detection signal S1 input from the comparator 13 as a trigger, sets the overcurrent protection signal S3 to high level, and triggers the rising edge of the timer signal S2 input from the timer circuit 17 The overcurrent protection signal S3 is reset to a low level. The operation of the latch circuit 16 will be described later.

  The timer circuit 17 starts counting the protection operation period Toff using the rising edge of the overcurrent detection signal S1 input from the comparator 13 as a trigger, and when the count operation ends, the timer circuit S2 is changed from low level to high level. A means to set a level. The operation of the timer circuit 17 will be described later.

  A constant current source 18, N-channel MOS field effect transistors 19 and 20, a diode array 21, a P-channel MOS field effect transistor 22, and a resistor 23 are connected to the gate-source voltage (input voltage Vin and gate signal) of the transistor 11. This is a withstand voltage protection circuit that draws the drive current of the pre-driver 10 while controlling the lower drive voltage VL in accordance with the input voltage Vin so that the voltage difference with SG is kept below a predetermined value. One end of the constant current source 18 is connected to the application end of the internal voltage Vreg. The other end (constant current output end) of the constant current source 18 is connected to the drain of the transistor 19. The source of the transistor 19 is connected to the ground terminal. The gate of the transistor 19 is connected to the gate of the transistor 20 and is also connected to the drain of the transistor 19. The source of the transistor 20 is connected to the ground terminal. The drain of the transistor 20 is connected to the anode end of the diode array 21 and the gate of the transistor 22. The cathode end of the diode array 21 is connected to the application end of the input voltage Vin. The drain of the transistor 22 is connected to the ground terminal via the resistor 23. The source of the transistor 22 is connected to the application end of the lower drive voltage VL. The number of diodes forming the diode array 21 may be an arbitrary integer of 1 or more. The operation of the withstand voltage protection circuit having the above configuration will be described in detail later.

  Based on the low voltage detection signal S4 input from the comparator 25, the low voltage driver 24 lowers the lower drive voltage VL of the predriver 10 than usual, and determines whether or not to draw the drive current of the predriver 10. It is a means to control. The circuit configuration and operation of the low voltage driver 24 will be described later.

  The comparator 25 compares the electromotive voltage (threshold voltage Vth2) of the DC voltage source 26 applied to the non-inverting input terminal (+) with the input voltage Vin applied to the inverting input terminal (−) to detect a low voltage detection signal. This is a low voltage detection circuit that generates S4 and outputs it to the low voltage driver 24. That is, when the input voltage Vin is higher than the threshold voltage Vth2, the low voltage detection signal S4 is maintained at a low level, but when the input voltage Vin becomes lower than the threshold voltage Vth2, the low voltage detection signal S4 transitions to a high level. Is done.

  The DC voltage source 26 is a means for setting a threshold voltage (= Vth2) for detecting a low voltage, and is connected between the non-inverting input terminal (+) of the comparator 25 and the ground terminal.

  Next, the current consumption reduction function of the overcurrent protection circuit will be described in detail with reference to FIGS. 3 to 5 are all timing charts for explaining the current consumption reduction function of the overcurrent protection circuit. From the top, the clock signal CLK (the set signal S of the RS flip-flop 9) and the comparison are respectively shown. The signal CMP (the reset signal R of the RS flip-flop 9), the pulse signal PWM (the output signal Q of the RS flip-flop 9), the enable signal EN, the gate signal SG, the switch voltage Vsw, and the current i are depicted. 3 shows a state when the pulse signal PWM is continuously oscillated, and FIG. 4 shows a state when the pulse signal PWM is intermittently oscillated. FIG. 5 shows a state in which a delay time d2 described later is set to be long.

  First, FIG. 3 and FIG. 4 will be described. As described above, the pulse signal PWM output from the output terminal (Q) of the RS flip-flop 9 is set to a high level at the rising edge of the clock signal CLK input to the set terminal (S), and the reset terminal (R ) Is reset to a low level at the rising edge of the comparison signal CMP.

  The delay circuit 15 delays the timing when the pulse signal PWM is set to the low level so as to use the pulse signal PWM as the enable signal EN of the overcurrent protection circuit, and generates the enable signal EN of the comparator 13. That is, the enable signal EN is set to the high level at the same timing as the rising edge of the pulse signal PWM, and is set to the low level at a timing delayed by the delay time d2 from the falling edge of the pulse signal PWM.

  On the other hand, the pre-driver 10 generates the gate signal SG by increasing the driving capability of the pulse signal PWM and inverting the logic. At this time, the timing at which the gate signal SG is at the low level is delayed by the delay time d1 from the timing at which the pulse signal PWM is at the high level, depending on the slew rate of the pre-driver 10 and the gate capacitance of the transistor 11. That is, the gate signal SG is set to the low level at a timing delayed by the delay time d1 from the rising edge of the pulse signal PWM, and is set to the high level at the same timing as the falling edge of the pulse signal PWM.

  Therefore, the period T2 in which the comparator 13 is in the operating state is longer than the period T1 in which the transistor 11 is turned on. In other words, the comparator 13 is activated before the transistor 11 is turned on, and is deactivated after the transistor 11 is turned off.

  As described above, the switching regulator IC 100 of the present embodiment includes an overcurrent protection circuit (including the comparator 13) that monitors the current i flowing through the transistor 11 and performs overcurrent protection, and overcurrent protection when the transistor 11 is on. An enable control circuit (in this embodiment, the delay circuit 15) is set to have the circuit in an operating state and the overcurrent protection circuit in a non-operating state when the transistor 11 is turned off.

  With this configuration, the overcurrent protection circuit is activated only when the current i should be monitored (that is, when the transistor 11 is turned on and the current path through the transistor 11 is conducted). In the other case, the overcurrent protection circuit can be deactivated, so that the current consumption of the overcurrent protection circuit can be reduced. In particular, as shown in FIG. 4, at the time of light load or no load when the pulse signal PWM is in an intermittent oscillation state, the ratio of the consumption current of the overcurrent protection circuit to the consumption current of the entire switching regulator increases. The effect of reducing current consumption according to the present invention is remarkable.

  In the switching regulator IC 100 of this embodiment, the enable control circuit (delay circuit 15) is configured to use the pulse signal PWM used for on / off control of the transistor 11 as the enable signal EN of the overcurrent protection circuit. Yes. With such a configuration, matching between the on / off control timing of the transistor 11 and the on / off control timing of the overcurrent protection circuit can be easily realized. However, the configuration of the present invention is not limited to this, and the enable signal EN of the overcurrent protection circuit may be generated by other means. For example, the enable signal EN may be generated from the gate signal SG of the transistor 11 or the enable signal EN may be generated by directly monitoring the on / off state of the transistor 11.

  Further, as described above, the switching regulator IC 100 of the present embodiment uses the delay circuit 15 that generates the enable signal EN by delaying the timing at which the pulse signal PWM is set to the low level, as the enable control circuit. Yes. With such a configuration, the period T2 in which the comparator 13 is in the operating state can be made longer than the period T1 in which the transistor 11 is turned on. Therefore, when the transistor 11 is turned on, the overcurrent protection circuit Can be activated reliably.

  Next, FIG. 5 will be described. In the example of FIG. 5, the delay time d2 given to the pulse signal PWM by the delay circuit 15 is set longer than the examples of FIGS. More specifically, in the delay circuit 15, when the pulse signal PWM is continuously oscillated, the overcurrent protection circuit is always maintained in an operating state, and only when the pulse signal PWM is intermittently oscillated. The delay time d2 is set so that the protection circuit is inoperative.

  Referring to the example of FIG. 5, when the pulse signal PWM is continuously oscillating, the next rising edge of the pulse signal PWM arrives before the delay time d2 elapses from the falling edge of the pulse signal PWM. Therefore, the enable signal EN is always at a high level, and the overcurrent protection circuit is always maintained in the operating state. On the other hand, when the pulse signal PWM is intermittently oscillated, even if the delay time d2 elapses from the falling edge of the pulse signal PWM, the next rising edge of the pulse signal PWM does not arrive. When the delay time d2 elapses, the level becomes low level, and the overcurrent protection circuit is deactivated.

  By adopting such a configuration, when the pulse signal PWM is continuously oscillated, the overcurrent protection circuit is always maintained in an operating state with priority given to improving safety, while the pulse signal PWM is intermittently oscillated. When it is, it is possible to put the overcurrent protection circuit into a non-operating state in preference to the reduction of current consumption.

  In the above embodiment, the configuration in which the present invention is applied to the switching regulator IC 100 has been described as an example. However, the application target of the present invention is not limited to this, and an overcurrent protection circuit is provided. The present invention can be widely applied to all switch drive devices (for example, a switch drive device that performs on / off control of a switching element that forms an output stage of a motor driver).

  Next, the self-recovery function of the overcurrent protection circuit will be described in detail with reference to FIG. 6 together with FIG. FIG. 6 is a timing chart for explaining the self-recovery function of the overcurrent protection circuit. The clock signal CLK, the overcurrent detection signal S1, the timer signal S2, and the overcurrent protection signal S3 are depicted in order from the top. Has been.

  As described above, the timer circuit 17 starts counting the protection operation period Toff using the rising edge of the overcurrent detection signal S1 as a trigger, and when the count operation ends, the timer signal S2 is changed from low level to high level. Set to level. The latch circuit 16 sets the overcurrent protection signal S3 to a high level using the rising edge of the overcurrent detection signal S1 as a trigger, and sets the overcurrent protection signal S3 to a low level using the rising edge of the timer signal S2 as a trigger. Reset. The overcurrent protection signal S3 generated in this way is applied to the second input terminal of the OR calculator 8 and is used for masking the comparison signal CMP. Specifically, when the overcurrent protection signal S3 is at a low level, the comparison signal CMP is passed through the OR calculator 8, and when the overcurrent protection signal S3 is at a high level, the comparison signal CMP is an OR calculator. 8 masked.

  As described above, in the switching regulator IC 100 of the present embodiment, the overcurrent protection circuit starts counting the predetermined protection operation period Toff when the overcurrent is detected, and the protection operation period after the overcurrent is detected. The driving of the transistor 11 is continuously stopped until Toff has elapsed, and then the driving of the transistor 11 is resumed.

  With such a configuration, unlike the conventional configuration in which the overcurrent protection circuit self-recovers every cycle of the pulse signal PWM (every pulse cycle of the clock signal CLK), an abnormal state in which the overcurrent continues to flow (output) Even in the event of a short circuit, the overcurrent protection circuit is not self-recovered every cycle of the pulse signal PWM, and an excessive current i does not continue to flow intermittently. Therefore, the switching regulator IC 100 and external components (coils) It is possible to suppress the heat generation of L1, Schottky diode D1).

  The timer circuit 17 may be an analog timer such as an RC time constant circuit or a digital timer that counts the number of pulses of the clock signal CLK. The protection operation period Toff is preferably set sufficiently longer than the pulse period T of the clock signal CLK. For example, when the pulse period T is several [μs], the protection operation period Toff is several tens [μs]. ] May be set.

  In FIG. 1, the latch circuit 16 and the timer circuit 17 are depicted as independent circuit blocks as the self-recovery function unit of the overcurrent protection circuit. However, the configuration of the present invention is not limited to this. As shown in FIG. 7, the circuit elements forming the latch circuit 16 and the timer circuit 17 include a capacitor CA, a constant current source IA that generates a charging current for the capacitor CA, and an overcurrent. A discharge unit that sometimes discharges the capacitor CA (in FIG. 7, an N-channel MOS field-effect transistor NA that is turned on when the overcurrent detection signal S1 is at a high level), and a charge voltage VC of the capacitor CA is a predetermined threshold voltage. A comparison unit (inverter INV in FIG. 7) that changes the output logic of the overcurrent protection signal S3 depending on whether it is higher or lower may be adopted.

  FIG. 8 is a timing chart for explaining the operation of the self-recovery function unit configured as described above. From the top, the overcurrent detection signal S1, the charging voltage VC of the capacitor CA, and the overcurrent protection signal S3 are depicted. Has been.

  As shown in FIG. 8, when the overcurrent detection signal S1 rises to a high level, the transistor NA is turned on, the capacitor CA is discharged, and the charging voltage VC becomes a zero value (low level). Therefore, the overcurrent protection signal S3 that is the output signal of the inverter INV rises to a high level, and the driving of the transistor 11 is continuously stopped. When the driving of the transistor 11 is stopped, the overcurrent detection signal S1 falls to the low level, and the transistor NA is turned off. As a result, charging of the capacitor CA is resumed and the charging voltage VC starts to rise. When the charging voltage VC reaches the logic inversion threshold value of the inverter INV (see the one-dot chain line in FIG. 8), the overcurrent protection signal S3 is changed from the high level to the low level, and the driving of the transistor 11 is resumed.

  As described above, the self-recovery function unit configured as described above can generate a desired overcurrent protection signal S3 with a simple analog circuit. Note that the length of the protection operation period Toff can be appropriately adjusted according to the amount of current generated by the constant current source IA.

  In the above embodiment, the configuration using the inverter INV as an example of the comparison unit that changes the output logic of the overcurrent protection signal S3 according to whether the charging voltage VC of the capacitor CA is higher or lower than a predetermined threshold voltage is taken as an example. Although described above, the configuration of the present invention is not limited to this, and a buffer or a comparator may be used.

  Next, the circuit configuration and operation of the internal voltage generator 1 will be described in detail. FIG. 9 is a circuit diagram illustrating a configuration example of the internal voltage generation unit 1. As shown in FIG. 9, the internal voltage generation unit 1 of this configuration example includes pnp bipolar transistors Qa, Qb, Qc, npn bipolar transistors Qd, Qe, resistors Ra, Rb, Rc, Rd, and a capacitor Ca. And an operational amplifier AMP and a DC voltage source Ea.

  The emitters of the transistors Qa, Qb, and Qc are all connected to the application terminal for the input voltage Vin. The bases of the transistors Qa, Qb, and Qc are all connected to the collector of the transistor Qa. The collector of the transistor Qa is connected to the input terminal of the input current Iin. The collector of the transistor Qb is connected to the power supply terminal of the operational amplifier AMP, and is also connected to the collector of the transistor Qd via the resistor Ra. The collector of the transistor Qc is connected to the ground terminal via the resistor Rb, and is also connected to the base of the transistor Qd. The emitter of the transistor Qd is connected to the ground terminal. The collector of the transistor Qe is connected to the application terminal for the input voltage Vin. The base of the transistor Qe is connected to the output terminal of the operational amplifier AMP. The emitter of the transistor Qe is connected to the ground terminal via the resistors Rc and Rd, and is also connected to the output terminal of the internal voltage Vreg. The non-inverting input terminal (+) of the operational amplifier AMP is connected to the application terminal of the first voltage V1 (the positive terminal of the DC voltage source Ea). An inverting input terminal (−) of the operational amplifier AMP is connected to an application terminal (a connection node between the resistor Rc and the resistor Rd) of the second voltage V2.

  The internal voltage generation unit 1 having the above-described configuration uses the operational amplifier AMP to control the open degree of the transistor Qe so that the first voltage V1 and the second voltage V2 coincide with each other, thereby obtaining a desired internal voltage from the input voltage Vin. It is a series regulator that generates a voltage Vreg.

  In the internal voltage generation unit 1 having the above configuration, the transistors Qa and Qb form a current mirror circuit that generates a desired output current Iout (= α × Iin) from the input current Iin and supplies this to the operational amplifier AMP. doing.

  This current mirror circuit includes a first current mirror stage including transistors Qa and Qb, and a peak current prevention circuit X (transistors Qc and Qd, resistor Ra for suppressing fluctuations in the output current Iout when the input voltage Vin suddenly changes. , Rb, and capacitor Ca).

  FIG. 10 is a waveform diagram for explaining the peak current prevention operation. In order from the top, the input voltage Vin, the base-emitter voltage Vbe of the transistor Qb, the first mirror current I1, the second mirror current I2, and the correction current are shown. I3 and output current Iout are shown.

  As shown in FIG. 10, when the input voltage Vin is kept constant, the base-emitter voltage Vbe of the transistor Qb is maintained at the forward drop voltage Vf between the base and emitter of the transistor Qb, and the first mirror The current I1 and the second mirror current I2 are maintained at α × Iin and β × Iin, respectively. Further, while the second mirror current I2 is maintained at the above current value, the transistor Qd is turned off, and the current path from the collector of the transistor Qb to the ground terminal via the resistor Ra and the transistor Qd is cut off. The correction current I3 flowing through this current path has a zero value. As a result, the output current Iout has the same current value (α × Iin) as the first mirror current I1. The second mirror constant β is desirably set to a value (for example, a few tenths) sufficiently smaller than the first mirror constant α from the viewpoint of reducing current consumption.

  On the other hand, when the input voltage Vin suddenly fluctuates, the base-emitter voltage Vbe of the transistor Qb increases, but the capacitor Ca is connected between the input voltage Vin and the base of the transistor Qb. The increase amount is very small compared to the conventional configuration (see FIGS. 12 and 13).

  In addition to the capacitor Ca, the peak current prevention circuit X is provided with a peak current absorption circuit Y (transistors Qc and Qd and resistors Ra and Rb) that absorbs the increased amount of the first mirror current I1. Thus, further suppression of the peak current generated when the input voltage Vin suddenly changes is achieved.

  The operation of the peak current absorption circuit Y will be described in detail with reference to FIGS. When a sudden change occurs in the input voltage Vin and a peak current occurs in the first mirror current I1, a peak current also occurs in the second mirror current I2 with the same behavior. At this time, when the second mirror current I2 reaches a predetermined value, the base potential of the transistor Qd (the one end voltage of the resistor Rb through which the second mirror current I2 flows) is raised to the on-threshold voltage of the transistor Qd, and the transistor Qd is turned on. Thus, the current path from the collector of the transistor Qb to the ground terminal via the resistor Ra and the transistor Qd is conducted. As a result, since the correction current I3 corresponding to the second mirror current I2 is drawn from the collector of the transistor Qb, the output current Iout is a current value obtained by subtracting the correction current I3 from the first mirror current I1 (first mirror current). The increase in I1 is the absorbed current value).

  As described above, the current mirror circuit according to the present invention includes the first current mirror stage (transistors Qa and Qb) that generates the first mirror current I1 by mirroring the input current Iin, and the first mirror that is generated when the power supply suddenly changes. A peak current absorption circuit Y (transistors Qc, Qd, resistors Ra, Rb) that generates a correction current I3 corresponding to the increase in the current I1 and draws it from the output terminal of the first current mirror stage. The differential current (= I1−I3) obtained by subtracting the correction current I3 from the first mirror current i1 is output as the output current Iout to the subsequent circuit (the operational amplifier AMP).

  More specifically, the peak current absorption circuit Y includes a second current mirror stage (transistors Qa and Qc) that mirrors the input current Iin to generate a second mirror current I2, and a second mirror current I2. Accordingly, a correction current generation circuit Z (transistor Qd, resistors Ra and Rb) for controlling the amount of correction current I3 to be drawn is configured.

  More specifically, the correction current generation circuit Z includes a resistor Rb that converts the second mirror current I2 into a voltage signal, and an output terminal (collector of the transistor Qb) of the first current mirror stage and a ground terminal. The transistor Qd is connected and the conductivity is controlled in accordance with the voltage signal.

  By adopting such a configuration, even if the input voltage Vin changes suddenly, a large peak current does not occur in the output current Iout of the current mirror circuit, so that it is possible to prevent malfunction of the subsequent circuit. This can contribute to improving the stability of the switching regulator. In particular, when the output voltage of the battery is directly applied as the input voltage Vin, since the input voltage Vin tends to fluctuate easily, the effect of reducing the peak current according to the present invention becomes significant.

  In the above-described embodiment, the configuration using the current mirror circuit according to the present invention has been described as an example of the drive current generation means of the operational amplifier AMP. However, the scope of application of the present invention is limited to this example. Instead, the present invention can be widely applied to all current mirror circuits that generate a desired output current by mirroring an input current.

  Next, the breakdown voltage protection function of the transistor 11 and the switching function to the low voltage mode will be described in detail with reference to FIG.

  As described above, the switching regulator IC 100 of this embodiment has the input voltage Vin so that the gate-source voltage of the transistor 11 (voltage difference between the input voltage Vin and the gate signal SG) is maintained below a predetermined value. Accordingly, a withstand voltage protection circuit that pulls in the drive current of the pre-driver 10 while controlling the lower drive voltage VL of the pre-driver 10 is provided.

  As shown in FIG. 1, the above-mentioned withstand voltage protection circuit includes a diode array 21 whose cathode terminal is connected to the application terminal of the input voltage Vin, and a constant current source (18 to 20) that supplies a constant current to the diode array 21. , A P-channel field effect transistor 22 having a source connected to the application terminal of the lower drive voltage VL and a gate connected to the anode terminal of the diode array 21.

  Certainly, in the withstand voltage protection circuit configured as described above, the lower drive voltage VL of the pre-driver 10 is Vin−VA + VthB (where VA is the forward voltage drop of the diode array 21 and VthB is the on-threshold voltage of the transistor 22). Therefore, the gate-source voltage of the transistor 11 can be opened only to a predetermined value (VA-VthB). Therefore, even when the transistor 11 is operated at a high input voltage Vin, the gate-source voltage of the transistor 11 does not exceed the breakdown voltage, and it is possible to prevent the device from being damaged or abnormally heated.

  However, when only the above-mentioned withstand voltage protection circuit is provided, as described in the section of the prior art, VthA + VthB + Vds or more (where VthA is the on-threshold voltage of the transistor 11, Vds) in order to operate the pre-driver 10 normally. Needs to supply the input voltage Vin of the drain-source drop voltage of the transistor 20. Further, when the input voltage Vin decreases, the voltage between the gate and source of the transistor 11 decreases, so that the on-resistance of the transistor 11 increases and the power efficiency decreases.

  Therefore, the switching regulator IC 100 of this embodiment includes a low voltage detection circuit (comparator 25) that detects whether or not the input voltage Vin is lower than the threshold voltage Vth2, and a low voltage state of the input voltage Vin in the low voltage detection circuit. Only when it is detected, it has a low-voltage driver 24 that lowers the lower drive voltage VL of the pre-driver 10 than usual and draws the drive current of the pre-driver 10.

  The low voltage driver 24 includes a resistor Rx and an N-channel field effect transistor Nx as shown in FIG. The drain of the transistor Nx is connected to the application terminal of the lower drive voltage VL via the resistor Rx. The source of the transistor Nx is connected to the ground terminal. The gate of the transistor Nx is connected to the application terminal of the low voltage detection signal S4.

  In the switching regulator IC 100 having the above-described configuration, when the input voltage Vin falls below the threshold voltage Vth2, the lower drive voltage VL of the pre-driver 10 is lowered than usual by the action of the low voltage driver 24, and the transistor 22 The drive current of the pre-driver 10 is drawn not only in the current path through the transistor Nx but also in the current path through the transistor Nx. That is, when the low voltage state of the input voltage Vin is detected, the drive mode of the pre-driver 10 is switched from the normal mode to the low voltage mode.

  With such a configuration, the switching regulator can be operated safely and stably even when the input voltage Vin is widely changed from the high voltage range to the low voltage range. Further, even when the input voltage Vin is in a low voltage state, the gate-source voltage of the transistor 11 can be ensured and the on-resistance of the transistor 11 can be kept small, leading to a reduction in power efficiency. Disappear.

  The configuration of the present invention can be variously modified in addition to the above-described embodiment without departing from the gist of the invention.

  The present invention is a technique that can be used for all devices and systems including electric circuits and electronic circuits, such as electrical appliances, automobiles, and power facilities.

These are the circuit block diagrams which show one Embodiment of the switching regulator which concerns on this invention. These are timing charts for explaining the generation operation of the pulse signal PWM used for on / off control of the transistor 11. These are the timing charts (when pulse signal PWM is oscillating continuously) for demonstrating the consumption current reduction function of an overcurrent protection circuit. These are timing charts (when pulse signal PWM is oscillating intermittently) for explaining the current consumption reduction function of the overcurrent protection circuit. These are timing charts (when delay time d2 is set long) for explaining the consumption current reduction function of the overcurrent protection circuit. These are timing charts for explaining the self-recovery function of the overcurrent protection circuit. These are the circuit diagrams which show the example of 1 structure of a self-recovery function part. These are timing charts for explaining the operation of the self-recovery function unit. FIG. 3 is a circuit diagram showing a configuration example of an internal voltage generation unit 1. These are waveform diagrams for explaining the peak current prevention operation. FIG. 3 is a circuit diagram showing a configuration example of a low voltage driver 24. These are the circuit block diagrams which show the prior art example of the switching regulator provided with the overcurrent protection circuit. These are waveform diagrams showing the behavior of the current i flowing through the switching element Q1.

Explanation of symbols

100 Switching regulator IC (switch drive device)
DESCRIPTION OF SYMBOLS 1 Internal voltage generation part 2 Reference voltage generation part 3 Soft start voltage generation part 4 Error amplifier 5 PWM comparator 6 Slope voltage generation part 7 Oscillator 8 OR operator 9 RS flip-flop 10 Predriver 11 P channel type MOS field effect transistor 12 Sense resistor 13 Comparator 14 DC voltage source 15 Delay circuit 16 Latch circuit 17 Timer circuit 18 Constant current source 19, 20 N channel type MOS field effect transistor 21 Diode array 22 P channel type MOS field effect transistor 23 Resistance 24 Low voltage driver 25 Comparator 26 DC voltage source D1 Diode (Schottky diode)
L1 Inductor C1, C2 Capacitor R1-R4 Resistance NA N-channel MOS field effect transistor CA Capacitor IA Constant current source INV Inverter Qa, Qb, Qc Pnp type bipolar transistor Qd, Qen npn type bipolar transistor Ra, Rb, Rc, Rd resistance Ca capacitor Ea DC voltage source AMP operational amplifier X peak current prevention circuit Y peak current absorption circuit Z correction voltage generation circuit Nx N channel type MOS field effect transistor Rx resistance

Claims (3)

A pre-driver that receives an input of a pulse signal that is a first logic when the switching element is turned on and a second logic that is the second logic when the switching element is turned off, and performs on / off control of the switching element ;
An overcurrent protection circuit that performs overcurrent protection by monitoring a current flowing through the switching element;
The overcurrent protection circuit is activated before the pre-driver turns on the switching element after the pulse signal is set to the first logic, and the pre-driver is switched to the switching state after the pulse signal is set to the second logic. A delay circuit for generating an enable signal for the overcurrent protection circuit by delaying a timing at which the pulse signal is set to the second logic so that the overcurrent protection circuit is inactivated after the element is turned off; ;
A switch driving device comprising: The delay circuit is configured such that when the pulse signal is continuously oscillated, the overcurrent protection circuit is always maintained in an operating state, and only when the pulse signal is intermittently oscillated, the overcurrent protection circuit is not operated. as a state, the switch driving device according to claim 1, characterized in that the delay time is set.   An automobile comprising the switch driving device according to claim 1.

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