JP5214219B2 - Charge pump circuit and control circuit thereof - Google Patents

Description

  The present invention relates to a charge pump circuit.

  Electronic devices such as cellular phones and PDAs (Personal Digital Assistants) in recent years are equipped with devices that require a driving voltage higher than the battery voltage, such as LEDs (Light Emitting Diodes) used for liquid crystal backlights. The For example, in these small information terminals, a Li-ion battery is often used, and its output voltage is normally about 3.5V, and even when fully charged, it is about 4.2V. Requires a higher voltage. Thus, when a voltage higher than the battery voltage is required, the battery voltage is boosted using a charge pump circuit or a switching regulator to obtain a voltage necessary for driving the LED.

The charge pump circuit generates an output voltage obtained by multiplying the input voltage by a predetermined boost rate. For example, when the battery voltage is 3V and the boost rate is double, the output voltage is fixed at 6V. Therefore, when the load circuit requires a driving voltage lower than 6V, a power transistor is inserted on the input side or output side of the charge pump circuit to constitute a regulator, and the output voltage is adjusted by adjusting the on-resistance. There was a need to do. For example, Patent Document 1 describes related technology.
JP 2000-262043 A

  As a result of studying a pulse modulation type charge pump circuit that stabilizes the output voltage by modulating the on-time of the switching element of the charge pump circuit, the present inventors have recognized the following problems.

  When the charge pump circuit is combined with a regulator using a power transistor whose on-resistance is adjusted as in the past, the charge pump circuit can be soft-started by gently changing the reference voltage of the regulator. .

  However, when the on-time of the switching element of the charge pump circuit is controlled by pulse modulation without using a regulator, when the switching element is turned on, even if the on-time is short, the flying capacitor or output capacitor with a small amount of charge is used. On the other hand, a large current (inrush current) flows. Such a problem can occur not only in pulse modulation but also in a charge pump circuit having a fixed duty.

  The present invention has been made in view of these problems, and an object thereof is to provide a charge pump circuit in which an inrush current is suppressed.

  One embodiment of the present invention relates to a control circuit for a charge pump circuit. The charge pump circuit has a flying capacitor and an output capacitor. The control circuit includes a first switch provided between the first input terminal to which the first input voltage is applied and one end of the flying capacitor, and a second switch provided between the other end of the flying capacitor and the fixed voltage terminal. A third switch provided between the second input terminal to which the second input voltage is applied and the other end of the flying capacitor; a fourth switch provided between one end of the flying capacitor and one end of the output capacitor; , A period corresponding to the high period of the pulse signal, a first pair of the first and second switches, or a second pair of the third and fourth switches, and a period corresponding to the low period, the other And a driver for turning on the pair. The driver turns on the first and fourth switches to charge the output capacitor during a predetermined precharge period from the start of activation of the charge pump circuit, and then alternately alternates the first and second pairs based on the pulse signal. Turn on and off.

“Duty ratio” refers to the ratio of the high period to the cycle time of the pulse signal.
When the first and fourth switches are turned on during the precharge period, the output capacitor is charged with the first input voltage. In a normal switching operation, there is a possibility that an inrush current may occur due to the sum of the first input voltage and the second input voltage being applied to the output capacitor. According to this aspect, the first input voltage is applied during the precharge period. Inrush current can be prevented because it is applied only during the period.

When the first input voltage Vin1 is higher than the second input voltage Vin2, the driver turns on the third switch in addition to the first and fourth switches and turns off the second switch during the precharge period. The capacitor may be charged with a difference voltage (Vin1-Vin2) between the first input voltage Vin1 and the second input voltage Vin2.
If the flying capacitor is charged with the first input voltage Vin1 during the precharge period, a large voltage of Vin1 + Vin2 is applied to the output capacitor immediately after the end of the precharge period and immediately after the normal switching operation is started. However, according to this aspect, since the voltage (Vin1−Vin2) + Vin2 = Vin1 is applied to the output capacitor immediately after starting the normal switching operation, the inrush current can be suitably prevented.

When the first input terminal and the second input terminal are commonly connected and the first input voltage and the second input voltage are equal, the driver may turn off the second switch during the precharge period.
In this case, the flying capacitor is not charged with the first input voltage during the precharge period, and the voltage Vin2 is applied to the output capacitor immediately after the start of the normal switching operation. Therefore, the inrush current can be suitably prevented.

The control circuit according to an aspect may further include a pulse modulator that generates a pulse signal whose duty ratio is adjusted so that a feedback voltage according to an output voltage of the charge pump circuit matches a predetermined reference voltage. After the precharge period, the pulse modulator may increase the reference voltage with time, and the driver may drive the first to fourth switches based on the pulse signal.
By raising the reference voltage as the soft start voltage, the output voltage can be gradually raised after the end of the precharge period.

The control circuit according to an aspect may further include an input switch provided on a path from the first input terminal to the output capacitor and capable of switching on-resistance. The driver may turn on the input switch with a high on-resistance during a predetermined soft start period from the start of activation of the charge pump circuit, and then switch the on-resistance of the input switch to a low state.
When the on-resistance of the first and fourth switches is very low, a large current may flow into the output capacitor even during the precharge period. In this case, the current flowing into the output capacitor can be suppressed by providing an input switch and increasing the on-resistance.

The input switch may be provided between the first switch and the first input terminal. The input switch may be provided between a connection point between the fourth switch and the flying capacitor and the first switch.
In this case, the charging current for the flying capacitor can be controlled after the charge pump circuit starts a normal switching operation.

The input switch may be provided between the fourth switch and the output capacitor. The input switch may be provided between a connection point between the first switch and the flying capacitor and the fourth switch.
In this case, the charging current for the output capacitor can be controlled after the charge pump circuit starts a normal switching operation.

  The input switch may include a plurality of MOSFETs connected in parallel, and the on-resistance may be switched by a combination of ON and OFF of the plurality of MOSFETs.

  The first and fourth switches may be MOSFETs, and the body diodes of each of the plurality of MOSFETs of the input switch may be provided in opposite directions to the body diodes of the first and fourth switches. In this case, the leakage current from the first input terminal to the output capacitor can be cut off.

  The pulse modulator may perform pulse width modulation in which the period is constant and the pulse width changes.

  Another aspect of the present invention is a charge pump circuit. The charge pump circuit includes a flying capacitor, an output capacitor, and any one of the above-described control circuits that controls charging and discharging states of the flying capacitor and the output capacitor.

  Yet another embodiment of the present invention relates to a method for controlling a charge pump circuit having a flying capacitor and an output capacitor. The method includes a precharge step and a switching step. In the precharge step, the output capacitor is charged using the first input voltage during a predetermined precharge period after the start of activation of the charge pump circuit. A switching step of charging the flying capacitor with a first input voltage; connecting one end of the flying capacitor to the output capacitor; applying a second input voltage to the other end of the flying capacitor; And a discharging step of charging the battery are alternately executed.

  When the first input voltage is higher than the second input voltage, the precharging step may charge the flying capacitor with a difference voltage between the first input voltage and the second input voltage.

  The switching step includes a step of generating an error voltage obtained by amplifying an error between the feedback voltage corresponding to the output voltage of the charge pump circuit and a predetermined reference voltage, and slicing the error voltage with a triangular wave signal having a predetermined period, and performing pulse width modulation. A step of generating a pulse signal generated, a step of limiting a pulse width of the pulse signal to a predetermined range, a time corresponding to a high period of the pulse signal, a charging or discharging step, and executing a step corresponding to the low period And the step of executing the other step.

  The switching step may increase the reference voltage with time after the precharge period.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, etc. are also effective as an aspect of the present invention.

  According to the present invention, the inrush current of the charge pump circuit can be suppressed.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are physically directly connected, or the member A and the member B are in an electrically connected state. Including the case of being indirectly connected through other members that do not affect the above.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.

  FIG. 1 is a circuit diagram showing a configuration of a charge pump circuit 120 according to an embodiment of the present invention. The charge pump circuit 120 adds the first input voltage Vin 1 input to the first input terminal 122 and the second input voltage Vin 2 input to the second input terminal 123, and outputs the output voltage Vout from the output terminal 124. As the input voltages Vin1 and Vin2, a battery voltage output from a battery (not shown) or a power supply voltage Vdd supplied from a power supply circuit is used. The present invention can be applied to a charge pump circuit having an arbitrary boosting rate. Hereinafter, an additive type (double boosting rate) charge pump circuit will be described for easy understanding.

  The charge pump circuit 120 includes a control circuit 100, a flying capacitor Cf1, an output capacitor Co1, and feedback resistors R1 and R2. The charge pump circuit of FIG. 1 has one flying capacitor Cf1 and one output capacitor Co1 because the boost rate is twice, but when the boost rate is different or when generating a plurality of output voltages, There may be a plurality of capacitors and output capacitors.

  The control circuit 100 includes a first switch group 10, a second switch group 12, a pulse modulator 20, and a driver 40, and is a functional circuit integrated on one semiconductor substrate. The first input voltage Vin1 is applied to the first input terminal 102, and the second input voltage Vin2 is applied to the second input terminal 103. A flying capacitor Cf1 is connected between the capacitor terminal 104 and the capacitor terminal 106, and an output capacitor Co1 is connected between the output terminal 108 and the ground. The ground terminal 110 is grounded, and a feedback voltage Vfb corresponding to the output voltage Vout is input to the feedback terminal 112. The feedback voltage Vfb is a voltage obtained by dividing the output voltage Vout by the feedback resistor R1 and the feedback resistor R2.

  Generally, the charge pump circuit generates a boosted voltage by repeating a charging period φ1 for charging the flying capacitor and a discharging period φ2 for charging the output capacitor using the charge stored in the flying capacitor. .

  The first switch group 10 includes at least one switch provided in a path for charging the flying capacitor Cf1 using the first input voltage Vin1. The first switch group 10 and the flying capacitor Cf1 form a series path between the first input terminal 122 and the ground. In the present embodiment, the first switch group 10 includes a first switch SW1 and a second switch SW2. Specifically, the first switch SW1 is provided between the first input terminal 102 and the capacitor terminal 104, and the second switch SW2 is provided between the capacitor terminal 106 and the ground terminal 110. The first switch SW1 is a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and the second switch SW2 is an N-channel MOSFET.

  The second switch group 12 includes at least one switch provided in a path for charging the output capacitor Co1 using the charge stored in the flying capacitor Cf1 during the charging period φ1. In the present embodiment, the second switch group 12 includes a third switch SW3 and a fourth switch SW4. Specifically, the third switch SW3 is provided between the first input terminal 102 and the capacitor terminal 106. The fourth switch SW4 is provided between the capacitor terminal 104 and the output terminal 108. Both the third switch SW3 and the fourth switch SW4 are P-channel MOSFETs.

  The driver 40 includes a level shift circuit, and controls on / off by switching gate voltages of the first switch SW1 to the fourth switch SW4.

  When both the first switch SW1 and the second switch SW2 are turned on during the charging period φ1, the first input voltage Vin1 is applied to one end of the flying capacitor Cf1, and the other end is grounded. As a result, the flying capacitor Cf1 is input to the first input. It is charged with the voltage Vin1. A potential difference between both ends of the flying capacitor Cf1 is ΔV.

  When both the third switch SW3 and the fourth switch SW4 are turned on during the discharge period φ2, the potential of the capacitor terminal 106 becomes equal to the second input voltage Vin2, and the potential of the capacitor terminal 104 becomes Vin2 + ΔV. The potential of the capacitor terminal 104 is applied to the output capacitor Co1 via the fourth switch SW4, whereby the output capacitor Co1 is charged.

  The driver 40 alternately repeats the charging period φ1 and the discharging period φ2 to boost the input voltage Vin. In the conventional charge pump circuit, the charging period φ1 and the discharging period φ2 are assigned to the high level and the low level of the clock signal having a duty ratio of 50%, so that the charging period φ1 and the discharging period φ2 are fixed. On the other hand, the charge pump circuit 120 according to the present embodiment is characterized in that the charging period φ1 and the discharging period φ2 are adjusted by feedback.

  The pulse modulator 20 generates a pulse signal Spwm3 and supplies it to the driver 40. The driver 40 assigns the high period TH of the pulse signal Spwm3 to either the charging period φ1 or the discharging period φ2, assigns the low period TL to the other, and turns on the first switch group 10 and the second switch group 12 alternately.

  A feedback voltage Vfb corresponding to the output voltage Vout of the charge pump circuit 120 is input to the pulse modulator 20. The voltage source 21 generates a reference voltage Vref. The pulse modulator 20 adjusts the duty ratio of the pulse signal Spwm3 so that the feedback voltage Vfb matches the predetermined reference voltage Vref. The duty ratio is a ratio of the cycle time Tp (= TH + TL) to the high period TH. In the present embodiment, the pulse modulator 20 performs pulse width modulation.

  The driver 40 provides a dead time so that the first switch group 10 and the second switch group 12 are not turned on at the same time, and the first switch group 10 and the second switch group in the vicinity of the positive edge and the negative edge of the pulse signal Spwm3. It is preferable to set a dead time during which both switch groups 12 are off. A known technique may be used as a dead time setting method.

  The pulse modulator 20 adjusts the duty ratio of the pulse signal Spwm1 by limiting it to a predetermined range. Hereinafter, the reason will be described.

  When the duty ratio of the pulse signal Spwm3 is 0%, the first switch group 10 is not turned on, so that the flying capacitor Cf1 is not charged by the first input voltage Vin1. Therefore, charge transfer to the output capacitor Co1 is not performed, and the current supply capability (driving capability) to a load (not shown) connected to the output terminal 124 is low (substantially 0).

  As the duty ratio of the pulse signal Spwm3 increases within a certain range, the charging period φ1 for the flying capacitor Cf1 becomes longer. Accordingly, the amount of charge stored in the flying capacitor Cf1 increases during the charging period φ1, and the potential difference ΔV of the flying capacitor Cf1 immediately after the charging period φ1 increases.

  As described above, the output capacitor Co1 is charged with a voltage of Vin2 + ΔV in the discharge period φ2. Therefore, when the potential difference ΔV of the flying capacitor Cf1 increases, the amount of charge supplied to the output capacitor Co1 during the discharge period φ2 increases. That is, as the duty ratio of the pulse signal Spwm3 increases, the current supply capability to the load increases.

  As the duty ratio of the pulse signal Spwm3 is increased, the charging period φ1 for the flying capacitor Cf1 becomes longer. However, the upper limit value of the potential difference ΔV immediately after the charging period φ1 is the first input voltage Vin1. Now, the duty ratio when the potential difference ΔV reaches the upper limit value is written as α%. When the duty ratio of the pulse signal Spwm3 increases beyond α%, the discharge period φ2 becomes shorter while the amount of charge supplied to the flying capacitor Cf1 is constant during the charge period φ1. As a result, as the duty ratio increases, the amount of charge supplied to the output capacitor Co1 during the discharge period φ2 decreases. That is, as the duty ratio of the pulse signal Spwm3 increases beyond α%, the current supply capability to the load decreases.

  When the duty ratio of the pulse signal Spwm3 becomes 100%, charge transfer from the flying capacitor Cf1 to the output capacitor Co1 is not performed, and the current supply capability to the load becomes substantially zero.

  That is, the current supply capability of the charge pump circuit 120 is minimum when the duty ratio is 0% and 100%, and is maximum when the duty ratio is a certain value α%. In other words, the duty ratio has a value that gives the maximum value to the current supply capability of the charge pump circuit.

  Therefore, the output voltage Vout is monitored, and when the output voltage Vout decreases, that is, when the load current increases, the current supply capability of the charge pump circuit 120 is increased, and conversely, when the output voltage Vout increases, That is, when the load current decreases, the output voltage Vout can be maintained at a constant value by performing feedback so as to decrease the current supply capability of the charge pump circuit 120.

  If the duty ratio of the pulse signal Spwm3 changes across α%, the output voltage Vout becomes unstable because feedback is applied in a direction away from the target value. Therefore, the charge pump circuit 120 according to the present embodiment limits the duty ratio of the pulse signal Spwm3 to a predetermined range.

  Thus, in the charge pump circuit 120 according to the present embodiment, the output voltage Vout is controlled by controlling the first switch group 10 and the second switch group 12 based on the pulse signal Spwm3 in which the range of the duty ratio is limited. Can be stabilized.

  When the first input voltage Vin1 = 10V and the second input voltage Vin2 = 3.5V, the conventional charge pump circuit can output only the output voltage Vout of 13.5V which is the sum. Therefore, when it is desired to obtain a desired voltage of 13.5 V or less, it is necessary to provide a linear regulator before or after the charge pump circuit, which increases the circuit area. On the other hand, according to the charge pump circuit 120 according to the present embodiment, since the output voltage Vout can be stabilized to a desired value without providing a regulator, the circuit area can be reduced.

  Further, when a regulator is provided as in the prior art, since the power transistor is inserted on the path from the input terminal to which the input voltage is supplied to the load, the efficiency is reduced due to the power loss of the power transistor. On the other hand, since the charge pump circuit 120 according to the present embodiment does not require a power transistor, the circuit efficiency can be improved.

  The value of α depends on the capacitance values of the flying capacitor Cf1 and the output capacitor Co1 and the frequency (period time Tp) of the pulse signal Spwm3, but is typically 50%. Hereinafter, a case where α = 50% will be described.

The predetermined range is
(1) 0% to βmax%
(2) γ min% to 100%
Can be set to either. Hereinafter, feedback control in each range will be described.

(1) First Control Method The pulse modulator 20 modulates the pulse signal Spwm3 so that the high period TH becomes longer as the feedback voltage Vfb is lower. At this time, the upper limit value βmax is set to the duty ratio of the pulse signal Spwm3, and modulation is performed so that the duty ratio of the pulse signal Spwm3 changes in the range of 0% to the upper limit value βmax%.

  It is desirable to set βmax ≦ α. In this case, since the change across the duty ratio α can be prevented, the output voltage Vout can be stabilized. However, βmax may be set to be larger than α when it is permissible to generate ripples in the output voltage Vout. In order to maximize the efficiency of the charge pump circuit, it is preferable to set βmax = α. When α = 50, βmax is set as large as possible between 0% and 50%.

  When βmax = 45%, the high period TH changes in a range of Tp × (0 to 0.45), and the low period TL changes in a range of Tp × (1 to 0.55). That is, the low period TL is limited to be longer than the high period TH. At this time, the driver 40 preferably turns on the first switch group 10 for a period corresponding to the high period TH of the pulse signal Spwm3 and turns on the second switch group 12 for a period corresponding to the low period TL. That is, it is preferable that the time for which the second switch group 12 is turned on is lengthened. The reason for this will be explained.

Now, the capacity desired from the output terminal 124 to the control circuit 100 side will be considered. In the charging period φ1, the fourth switch SW4 is turned off, so that the capacitor connected to the output terminal 124 is only the output capacitor Co1. In the discharge period φ2, the flying capacitor Cf1 is connected in addition to the output capacitor Co1. When the load current is constant, the fluctuation of the output voltage Vout becomes smaller as the capacitance connected to the output terminal 124 is larger.
Therefore, by assigning the time corresponding to the high period TH of the pulse signal Spwm3 to the charging period φ1, the discharging period φ2 becomes longer than the charging period φ1, and therefore the ripple of the output voltage Vout can be reduced.

  Although the longer discharge period φ2 has the advantage that the ripple of the output voltage Vout can be reduced, the high period TH may be assigned to the discharge period φ2 when the capacitance of the output capacitor Co1 is large or when the ripple is acceptable.

  The control circuit 100 in FIG. 1 shows a configuration for executing the first control method. The pulse modulator 20 includes an error amplifier 22, an oscillator 24, a PWM (Pulse Width Modulation) comparator 26, an AND gate 30, a minimum duty comparator 32, a PFM (Pulse Frequency Modulation) controller 34, and a maximum duty comparator 28.

  The error amplifier 22 receives the feedback voltage Vfb at the inverting input terminal and the reference voltage Vref at the non-inverting input terminal, and amplifies the error between the two voltages. The output of the error amplifier 22 is referred to as an error voltage Verr. The oscillator 24 outputs a triangular wave or a sawtooth wave periodic voltage Vosc. The PWM comparator 26 receives the error voltage Verr at the non-inverting input terminal and the periodic voltage Vosc at the inverting input terminal. The PWM comparator 26 slices the periodic voltage Vosc with the error voltage Verr and outputs a pulse signal Spwm1 whose level changes at the intersection. The pulse width of the pulse signal Spwm1 is modulated so that the output voltage Vout approaches the target value.

  Maximum duty comparator 28 receives periodic voltage Vosc and maximum voltage Vmax. The maximum duty comparator 28 slices the periodic voltage Vosc at the maximum voltage Vmax, and generates a maximum pulse signal Smax having a predetermined duty ratio. The value of the maximum voltage Vmax is set so that the duty ratio of the maximum pulse signal Smax matches the value of β described above.

  The AND gate 30 receives the pulse signal Spwm2 output from the PFM controller 34 and the maximum pulse signal Smax, and outputs a logical product of the two signals. The output of the AND gate 30, that is, the duty ratio of the pulse signal Spwm3 coincides with the duty ratio of the pulse signal Spwm1 when the duty ratio of the pulse signal Spwm1 is equal to or less than βmax%, and when the duty ratio of the pulse signal Spwm1 is equal to or greater than βmax%. , Βmax%. In order to limit the duty ratio of the pulse signal Spwm3, another circuit configuration may be used, and the format is not limited.

  The pulse modulator 20 compares the duty ratio of the pulse signal Spwm1 with a predetermined lower limit value βmin. When the duty ratio of the pulse signal Spwm1 is smaller than the lower limit value βmin, the level of the pulse signal Spwm1 is fixed, and the first switch group 10. Stop the switching of the second switch group 12. That is, no pulse is output from the pulse modulator 20. For this purpose, a minimum duty comparator 32 and a PFM controller 34 are provided.

  The pulse modulator 20 desirably fixes the level of the pulse signal Spwm3 so that the second switch group 12 is turned on when the duty ratio of the pulse signal Spwm3 is smaller than the lower limit value βmin. The reason will be described later.

  The minimum duty comparator 32 receives the periodic voltage Vosc and the minimum voltage Vmin. The minimum duty comparator 32 slices the periodic voltage Vosc with the minimum voltage Vmin, and generates a minimum pulse signal Smin having a predetermined duty ratio. The value of the minimum voltage Vmin is set so that the duty ratio of the minimum pulse signal Smin is about 20%.

  The PFM controller 34 receives the pulse signal Spwm1 and the minimum pulse signal Smin, and compares the duty ratios of the two signals. When the duty ratio of the pulse signal Spwm1 becomes smaller than the duty ratio of the minimum pulse signal Smin, the duty ratio of the pulse signal Spwm2 is fixed to a low level. When the duty ratio of the pulse signal Spwm1 is larger than the duty ratio of the minimum pulse signal Smin, the pulse signal Spwm2 becomes equal to the pulse signal Spwm1.

  Note that the order of the AND gate 30 and the PFM controller 34 may be reversed.

  The operation of the charge pump circuit 120 configured as described above will be described. FIG. 2 is a signal waveform diagram of the charge pump circuit 120 of FIG. In the waveform diagrams shown in this specification, the vertical axis and the horizontal axis are appropriately enlarged or reduced for the sake of brevity of explanation or easy understanding.

  As the load current increases, a large amount of charge is supplied from the output capacitor Co1 to the load, so that the output voltage Vout decreases and the error voltage Verr increases. The duty ratio of the pulse signal Spwm1 increases as the output voltage Vout decreases. However, the duty ratio of the pulse signal Spwm3 is limited to be equal to or less than the duty ratio βmax of the maximum pulse signal Smax. When the duty ratio of the pulse signal Spwm1 is smaller than the duty ratio βmin of the minimum pulse signal Smin, the pulse signal Spwm3 is fixed at a low level and the pulse is cut.

FIGS. 3A and 3B are operation waveform diagrams of the charge pump circuit 120 at normal load and light load, respectively.
As shown in FIG. 3A, when the load current is large and constant, the duty ratio of the pulse signal Spwm1 is adjusted by feedback. The first switch group 10 is turned on during the charging period φ1 when the pulse signal Spwm3 is high level, and the second switch group 12 is turned on during the discharge period φ2 when the pulse signal Spwm1 is low level. In the charging period φ1, since the load current flows out from the output capacitor Co1, the output voltage Vout decreases. In the discharge period φ2, since the output capacitor Co1 is charged using the flying capacitor Cf1, the output voltage Vout rises. By repeating the charging period φ1 and the discharging period φ2, the output voltage Vout is stabilized near the target value while slightly changing.

  FIG. 3B shows the operation at light load. In a light load state, the duty ratio of the pulse signal Spwm1 is smaller than the minimum duty ratio βmin. As a result, the switching of the first switch group 10 and the second switch group 12 stops, and the charging operation of the output capacitor Co1 stops. During this time, since the output capacitor Co1 is discharged by a small load current, the output voltage Vout gradually decreases. As the output voltage Vout decreases, the error voltage Verr increases, and when the duty ratio of the pulse signal Spwm1 exceeds the minimum duty ratio βmin at time t1, the pulse signal Spwm3 becomes high level and the charging period φ1 is reached. In the discharge period φ2 immediately after that, the output capacitor Co1 is charged, and the output voltage Vout rises. When the output voltage Vout increases, the error voltage Verr decreases again, the duty ratio becomes smaller than the minimum duty ratio βmin, and switching stops.

  As described above, in the charge pump circuit 120 according to the present embodiment, the duty ratio of the pulse signal Spwm3 is monitored, and a pulse smaller than the lower limit value βmin is cut to operate in the intermittent mode in a light load state. it can. In order to switch the first switch group 10 and the second switch group 12 on and off, a drive current for charging and discharging the gate capacitance of each transistor is required. Therefore, current consumption of the charge pump circuit 120 can be reduced.

Further, when the pulse signal Spwm3 is fixed at a low level at a light load, the circuit stops with the second switch group 12 turned on. Therefore, since the combined capacitance of the flying capacitor Cf1 and the output capacitor Co1 is connected to the output terminal 124, the ripple of the output voltage Vout can be reduced.
However, the present invention is not limited to this, and the pulse signal Spwm3 may be fixed at a high level during light load.

  Note that the ripple of the output voltage Vout shown in FIG. 3B is larger than that of FIG. 3A, but is actually the same or smaller. This is because the amount of discharge from the output capacitor Co1 is small and the amount of decrease in the output voltage Vout is small when the load current is small and the load is light.

The above is the operation of the charge pump circuit 120 according to the present embodiment. It should be noted that the pulse modulation technique of the charge pump circuit 120 has a different idea from the pulse modulation technique of the switching regulator. That is, when performing pulse width modulation in a step-up switching regulator, the duty ratio Dsr of the generated pulse signal is
Dsr = 1−Vin / Vout
Given in. That is, the duty ratio of the pulse signal is adjusted according to the input voltage Vin and the output voltage target value Vout.

  On the other hand, in the pulse modulation of the charge pump circuit 120 according to the present embodiment, the duty ratio of the pulse signal Spwm3 is different from the pulse modulation of the switching regulator in that it is determined according to the load current.

  In the switching regulator, feedback is applied in the direction in which the output voltage Vout increases as the duty ratio is increased. In the charge pump circuit, however, the feedback direction is reversed when the duty ratio crosses a certain boundary value. For this reason, in the charge pump circuit 120 according to the present embodiment, there is a limit on the range of the duty ratio of the pulse signal Spwm3.

(2) Second Control Method In the first control method, the pulse signal is modulated so that the high period TH becomes longer as the feedback voltage Vfb is lower. On the other hand, in the second control method, the pulse signal Spwm3 is modulated so that the low period TL becomes longer as the feedback voltage Vfb is lower. Further, a lower limit value γmin is set for the duty ratio of the pulse signal Spwm3, and modulation is performed so that the duty ratio of the pulse signal Spwm3 changes in a range from the lower limit value γmin% to 100%.

  At this time, it is desirable to set γmin ≧ α. In this case, since the change across α can be prevented, the output voltage Vout can be stabilized. However, γmin may be made smaller than α when ripples are allowed to occur in the output voltage Vout.

  In order to maximize the efficiency of the charge pump circuit, it is preferable to set γmin = α. When α = 50, γmin is set as small as possible between 50% and 100%.

  When γmin = 55%, the high period TH changes in a range of Tp × (0.55 to 1), and the low period TL changes in a range of Tp × (0.45 to 0). That is, the high period TH is limited to be longer than the low period TL. At this time, the driver 40 preferably turns on the first switch group 10 for a period corresponding to the low period TL of the pulse signal Spwm3 and turns on the second switch group 12 for a period corresponding to the high period TH. That is, it is preferable that the time for which the second switch group 12 is turned on is lengthened. Thereby, the ripple of the output voltage Vout can be reduced.

  In order to realize the second control method, the control circuit 100 of FIG. 1 may be modified. For example, the reference voltage Vref may be input to the inverting input terminal of the error amplifier 22 and the feedback voltage Vfb may be input to the non-inverting input terminal. In this case, the smaller the load current, that is, the larger the output voltage Vout, the larger the error voltage Verr, and the duty ratio of the pulse signal Spwm1 approaches 100%. As a result, the current supply capability to the load is reduced, and appropriate feedback can be applied. As the load current increases, the duty ratio approaches α and the current supply capability increases.

  In this case, the maximum duty comparator 28 may generate a pulse signal having a duty ratio of γmin, and the duty ratio of the pulse signal Spwm3 may be limited to be γmin or more.

  In order to realize the intermittent mode at a light load by the second control method, an upper limit value γmax is set for the duty ratio of the pulse signal Spwm3, and when the duty ratio of the pulse signal Spwm3 is larger than the upper limit value γmax, the pulse signal Spwm3 Fix the level. In this case, the minimum duty comparator 32 may generate a pulse signal having a duty ratio of γmax.

  In the second control method, the same effect as that of the first control method can be obtained.

  Next, a description will be given of a technique for preventing an inrush current flowing into the output capacitor at the start-up in the charge pump circuit having some or all of the features of the charge pump circuit 120 described above.

(First technology)
The driver 40 does not perform the switching operation of the charging period φ1 and the discharging period φ2 during a predetermined precharge period from the start of the activation of the charge pump circuit 120, and instead, the first switch SW1 and the fourth switch SW4 Is turned on to charge the output capacitor Co1.

  Thereafter, when the precharge period ends, the charging period φ1 and the discharging period φ2 are alternately switched, and the first pair (first switch SW1, second switch SW2) and the second pair (third switch SW3, fourth switch SW4). Are alternately turned on and off.

By providing the precharge period, the following effects can be obtained.
If the switching operation is started without providing the precharge period, the flying capacitor Cf1 is charged to ΔV during the charging period φ1, and then ΔV + Vin2 is applied to the output capacitor Co1. Immediately after startup, since the error between the output voltage Vout and the reference voltage Vref is large, the charging time of the flying capacitor Cf1 is the longest, so there is a possibility that ΔV≈Vin1. Then, in the subsequent discharge period φ2, a large voltage close to Vin1 + Vin2 is applied to the output capacitor Co1 in a state where the charge amount is 0, and there is a possibility that an inrush current flows in the output capacitor Co1. Immediately after the fourth switch SW4 is turned on, Vin1 + Vin2 is applied to one end (flying capacitor Cf1 side) of the fourth switch SW4 and 0 V is applied to the other end (output capacitor side), which may exceed the withstand voltage of the fourth switch SW4. There is also. Such a situation may affect the reliability of the circuit element.

  In contrast, by providing a precharge period and turning on the first switch SW1 and the fourth switch SW4, the first input voltage Vin1 is input to the output capacitor Co1 immediately after startup. Therefore, the occurrence of inrush current can be suppressed as compared with the situation where Vin1 + Vin2 is applied to the output capacitor Co1.

  In the precharge period, the first input voltage Vin1 is applied to both ends of the first switch SW1 and the fourth switch SW4. If the respective on-resistances are approximately the same, a voltage of Vin1 / 2 is applied to both ends of the fourth switch SW4. Therefore, the reliability of the element can be improved as compared with the situation where Vin1 + Vin2 is applied.

(Second technology)
In the precharge period, it is desirable that the second switch SW2 and the third switch SW3 are in the following states.

2-1. When the first input voltage Vin1 is higher than the second input voltage Vin2 In this case, during the precharge period, the driver 40 turns on the third switch SW3 in addition to the first switch SW1 and the fourth switch SW4, and the second switch SW2 is turned off. In this state, the flying capacitor Cf1 is charged with a differential voltage (Vin1-Vin2) between the first input voltage Vin1 and the second input voltage Vin2. That is, ΔV = (Vin1−Vin2).

When the precharge period ends and the switching operation is started and the third switch SW3 and the fourth switch SW4 are turned on in the discharge period φ2, the output capacitor Co1
Vin2 + ΔV = Vin2 + (Vin1-Vin2) = Vin1
Is applied. That is, it is possible to prevent a large voltage from being applied to the output capacitor Co1 when shifting from the precharge period to the switching operation.

If the third switch SW3 is turned off and the second switch SW2 is turned on during the precharge period to charge the flying capacitor Cf1 with the first input voltage Vin1, then ΔV = Vin1. Therefore, in the discharge period φ2 after the start of the switching operation, the output capacitor Co1 has
Vin2 + ΔV = Vin2 + Vin1
This is not preferable because a large voltage is applied.

2-2. When the first input voltage Vin1 is equal to the second input voltage Vin2 In this case, the driver 40 turns off the second switch SW2 during the precharge period. The third switch SW3 may be on or off. By turning off the second switch SW2, since the flying capacitor Cf1 is not charged with the first input voltage Vin1, it is possible to prevent a large voltage from being applied to the output capacitor Co1 immediately after the start of the switching operation.

(Third technology)
In combination with the first and second techniques, the pulse modulator 20 preferably performs a soft start to increase the reference voltage Vref with the eye time after the precharge period.

  The operation when the charge pump circuit 120 is activated by combining the first and second techniques will be described. FIG. 4 is a time chart showing an operation state at the start-up of the charge pump circuit 120 of FIG.

  At time t0, a sequence start signal (hereinafter, SEQ_IN signal) instructing start of activation of the charge pump circuit 120 becomes high level. When the SEQ_IN signal becomes high level, the driver 40 turns on the first switch SW1 and the fourth switch SW4 during the precharge period τpc and charges the output capacitor Co1 with the first input voltage Vin1. As a result, the output voltage Vout increases with time.

  At time t1 after the precharge period τpc has elapsed, the operation is switched to the soft start operation. During the soft start operation, the driver 40 alternately switches between the charging period φ1 and the discharging period φ2 based on the pulse signal Spwm3. During the soft start operation, the voltage source 21 gradually increases the reference voltage Vref with time. The output voltage Vout increases following the reference voltage Vref by feedback.

  Thereafter, when the reference voltage Vref reaches the target value at time t3, the output voltage Vout is stabilized.

  Thus, according to the charge pump circuit 120 of FIG. 1, the output voltage Vout can be increased while suppressing the inrush current.

(Fourth technology)
The fourth technique relates to a technique for effectively suppressing an inrush current by using in combination with at least one of the first to third techniques described above or by itself.
FIG. 5 is a circuit diagram showing a configuration of a charge pump circuit 120a according to a modification. The charge pump circuit 120a in FIG. 5 further includes an input switch 14 in addition to the charge pump circuit 120 in FIG. The driver 40 controls the state of the input switch 14 in addition to the first switch SW1 to the fourth switch SW4.

  The input switch 14 is provided on a path from the first input terminal 102 through the output terminal 108 to the output capacitor Co1, and is configured to be able to switch on-resistance. In FIG. 5, the input switch 14 is provided between the first switch SW <b> 1 and the first input terminal 102.

  The driver 40 turns on the input switch 14 in a state where the on-resistance is high during a predetermined soft start period τss from the start of activation of the charge pump circuit 120a, and then switches the on-resistance of the input switch 14 to a low state. The soft start period τss may coincide with the precharge period τpc, or may be longer or shorter. In the following, description will be made assuming that τss> τpc.

  The input switch 14 includes a P-channel MOSFET fifth switch SW5 and a P-channel MOSFET sixth switch SW6 connected in parallel. The on-resistance of the fifth switch SW5 is designed to be high, and the on-resistance of the sixth switch SW6 is designed to be sufficiently small so as not to cause a loss during normal switching operation.

  The driver 40 turns on only the fifth switch SW5 during the soft start period τss. Then, after the elapse of the soft start period τss, the sixth switch SW6 is turned on in addition to or instead of the fifth switch SW5.

By providing the input switch 14, the following effects can be obtained.
In the control circuit 100 of FIG. 1, the first switch SW1 and the fourth switch SW4 are turned on during the precharge period τss. Therefore, if the ON resistances of the first switch SW1 and the fourth switch SW4 are very small, or if the first input voltage Vin1 is very high, an inrush current may flow into the output capacitor Co1. Therefore, in such a case, the inrush current can be suitably prevented by providing the input switch 14 and setting the resistance value of the path from the first input terminal 102 to the output terminal 108 high in the precharge period τpc. Can do.

  When τss> τpc, the on-resistance of the input switch 14 is set high even after the soft start operation is started. Therefore, even if the switching operation starts with the output voltage Vout being low, it is possible to suitably prevent the inrush current from flowing. Thereafter, after the soft start period τss elapses, the ON resistance of the input switch 14 is set low, and the switching operation is performed with low loss.

  FIG. 6 is a circuit diagram showing a configuration example of the control circuit 100a of FIG. The control circuit 100a of FIG. 6 shows only the configuration of the voltage source 21 and the driver 40 in detail. The voltage source 21 includes a counter 21a and a voltage source 21b. The counter 21a receives the SEQ_IN signal and the clock CK. When the SEQ_IN signal becomes a high level, the counter 21a starts a count operation using the clock CK and measures the precharge period τpc and the soft start period τss.

  The counter 21a switches the charge signal (hereinafter, CHG signal) from the high level to the low level after the precharge period τpc has elapsed from the start of activation. Further, the soft start end signal (hereinafter referred to as SSEND signal) is switched from the high level to the low level at a time after the start of the soft start period τss.

The driver 40 includes a control unit 42, a first driver DRV1 to a fourth driver DRV4.
The control unit 42 turns on the fifth switch SW5 and turns off the sixth switch SW6 during a period when the SSEND signal is at a high level (soft start period τss). Further, both the fifth switch SW5 and the sixth switch SW6 are turned on while the SSEND signal is at a low level.

  The first driver DRV1 to the fourth driver DRV4 receive the pulse signal Spwm3 and the CHG signal and drive the first switch SW1 to the fourth switch SW4, respectively. Specifically, the first driver DRV1, the third driver DRV3, and the fourth driver DRV4 turn on the first switch SW1, the third switch SW3, and the fourth switch SW4, respectively, when the CHG signal is at a high level. The second driver DRV2 turns off the second switch SW2 when the CHG signal is at a high level.

  The first driver DRV1 to the fourth driver DRV4 switch the first switch SW1 to the fourth switch SW4 based on the pulse signal Spwm3 when the CHG signal is at a low level. That is, the first driver DRV1 and the second driver DRV2 turn on the first switch SW1 and the second switch SW2, respectively, when the pulse signal Spwm3 is at a low level, and turn off when the pulse signal Spwm3 is at a high level. Conversely, the third driver DRV3 and the fourth driver DRV4 turn on the third switch SW3 and the fourth switch SW4, respectively, when the pulse signal Spwm3 is at a high level, and turn off when the pulse signal Spwm3 is at a low level.

  The body diodes D1 and D4 of the first switch SW1 and the fourth switch SW4 are connected so that the cathode is on the output terminal 108 side and the anode is on the first input terminal 102 side. Therefore, in the circuit of FIG. 1, a current path exists from the first input terminal 102 to the output terminal 108 even when the first switch SW1 and the fourth switch SW4 are off. That is, when the first input voltage Vin1 cannot be cut off, a leakage current is generated, resulting in power loss. In FIG. 6, the fifth switch SW5 and the sixth switch SW6 are both P-channel MOSFETs, and the body diodes D5 and D6 are opposite to the body diodes D1 and D4. Therefore, the current path from the first input terminal 102 to the output terminal 108 can be completely cut off by turning off the switches SW1, SW4, SW5, and SW6.

  FIG. 7 is a time chart showing an operation state of the control circuit 100a of FIG. When the SEQ_IN signal becomes high level at time t0, start-up of the charge pump circuit 120 is instructed. During the precharge period τpc from time t0, the CHG signal is at a high level, and the first switch SW1, the third switch SW3, and the fourth switch SW4 are turned on. Further, the fifth switch SW5 is turned on and the sixth switch SW6 is turned off. As a result, the first input voltage Vin1 is applied to the output capacitor Co1 via the fifth switch SW5, the first switch SW1, and the fourth switch SW4, and the output voltage Vout increases.

  When the CHG signal becomes low level at time t1, the first switch SW1 to the fourth switch SW4 start the switching operation. After time t1, the reference voltage Vref gradually increases and a soft start operation is performed. At this time, only the fifth switch SW5 is on and the sixth switch SW6 is off. That is, during the period from the time t1 to the time t2, the soft start operation for gradually increasing the reference voltage Vref is performed, and the ON resistance of the input switch 14 is set to be high, so that the charging capability of the flying capacitor Cf1 from the first input terminal 102 By limiting, the output voltage Vout is gradually raised.

  When the SSEND signal becomes low level at time t2, the sixth switch SW6 is turned on, the current supply capability from the first input terminal 102 is maximized, and the load can be driven. Thereafter, when the SEQ_IN signal becomes low level at time t3, at least the first switch SW1 and the fourth switch SW4 are turned off.

  As described above, according to the control circuit 100a of FIGS. 5 and 6, on-resistance is provided on the path from the first input terminal 102 to the output capacitor Co1 via the output terminal 108, separately from the switching elements (SW1 to SW4). By providing an adjustable switch and switching on-resistance in accordance with the start-up sequence, the charging capacity for the output capacitor Co1 and the flying capacitor Cf1 can be limited, and an inrush current can be prevented.

  Specifically, according to the fourth technique in which the input switch 14 is provided, the following effects can be obtained.

(Effect 1) When the fourth technique is combined with the first technique When the first switch SW1 and the fourth switch SW4 are turned on during the precharge period τpc immediately after the start of the activation of the charge pump circuit 120a, the input switch 14 Is set to a high value, the impedance of the charging path from the first input terminal 102 to the output capacitor Co1 via the input switch 14, the first switch SW1, and the fourth switch SW4 can be increased. It is possible to prevent an inrush current from flowing through the capacitor Co1.

(Effect 2) When the fourth technique is combined with the first technique, or when used alone. Also, the precharge is not performed or the precharge is not performed to turn on the first switch SW1 and the fourth switch SW4. When the first switch SW1 to the fourth switch SW4 are switched after being performed, by setting the ON resistance of the input switch 14 to be high, the input switch 14 and the first switch SW1 are connected from the first input terminal 102. Thus, the impedance of the charging path leading to the flying capacitor Cf1 can be increased, and the charging current for the flying capacitor Cf1 can be limited. As a result, during the charging period φ1, the amount of charge stored in the flying capacitor Cf1 can be limited, so that the output voltage Vout can be gradually raised.

(Effect 3) When the fourth technology is combined with the third technology and the on-resistance of the input switch 14 is controlled, and the soft start for gradually increasing the reference voltage Vref is executed in the pulse modulator 20, the output voltage This is effective in increasing Vout gently.

  The charge pump circuit 120 according to the embodiment has been described above. Those skilled in the art will understand that the above-described embodiment is an exemplification, and that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. is there. Hereinafter, such modifications will be described.

5 and 6, the case where the input switch 14 is provided between the first switch SW1 and the first input terminal 102 has been described, but the present invention is not limited to this.
Since the input switch 14 has only to be provided on the path from the first input terminal 102 to the output terminal 108, the following modifications are possible.
Modification 1 The input switch 14 may be provided between the connection point N1 between the fourth switch SW4 and the flying capacitor Cf1 and the first switch SW1.
Modification 2 The input switch 14 may be provided between the fourth switch SW4 and the output capacitor Co1.
Modification 3 The input switch 14 may be provided between the connection point N1 between the first switch SW1 and the flying capacitor Cf1 and the fourth switch SW4.

  In the case of the first modification, the charging current for the flying capacitor Cf1 can be controlled after the charge pump circuit 120a starts the normal switching operation, as in the case of FIGS.

  In the second and third modifications, the charge current to the output capacitor Co1 can be controlled after the charge pump circuit 120a starts the normal switching operation.

  The configuration of the charge pump circuit is not limited to the topologies of FIGS. For example, a diode may be used instead of the transistor switch. In the embodiment, the addition type charge pump circuit that adds two input voltages has been described. However, a charge pump circuit having a double boosting rate may be used. The first input terminal 102 and the second input terminal 103 may be connected in common.

  Further, the boost rate may be 1.5 times or 4 times, and another charge pump circuit may be used, or a charge pump circuit in which a plurality of boost rates can be switched may be used. Furthermore, the present invention can be applied to a voltage inversion type charge pump circuit for generating a negative voltage.

  In the embodiment, the case where the first switch SW1 to the fourth switch SW4 and the input switch 14 are built in the control circuit 100 has been described. However, a discrete element may be used and provided outside the control circuit 100.

  In the embodiment, the case where the pulse modulator 20 performs pulse width modulation in which a pulse signal is generated by slicing a triangular wave or a sawtooth wave has been described, but the modulation method is not limited to this. For example, pulse frequency modulation or pulse density modulation may be performed. That is, the duty ratio of the pulse signal may be adjusted so that the output voltage Vout approaches the target voltage, and the duty ratio may be limited to a predetermined range.

  The logic level of each signal is not limited to that in the embodiment, and can be reversed as appropriate.

  Although the present invention has been described using specific words and phrases based on the embodiments, the embodiments are merely illustrative of the principles and applications of the present invention, and the embodiments are defined in the claims. Many modifications and arrangements can be made without departing from the spirit of the present invention.

It is a circuit diagram which shows the structure of the charge pump circuit which concerns on embodiment of this invention. FIG. 2 is a signal waveform diagram of the charge pump circuit of FIG. 1. 3A and 3B are operation waveform diagrams of the charge pump circuit of FIG. 1 at normal load and light load, respectively. 2 is a time chart showing an operation state at the time of starting the charge pump circuit of FIG. 1. It is a circuit diagram which shows the structure of the charge pump circuit which concerns on a modification. FIG. 6 is a circuit diagram illustrating a configuration example of a control circuit in FIG. 5. It is a time chart which shows the operation state of the control circuit of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Control circuit, 102 ... 1st input terminal, 103 ... 2nd input terminal, 104 ... Capacitor terminal, 106 ... Capacitor terminal, 108 ... Output terminal, 110 ... Grounding terminal, 112 ... Feedback terminal, 120 ... Charge pump circuit, 122: First input terminal, 123: Second input terminal, 124: Output terminal, Cf1: Flying capacitor, Co1: Output capacitor, R1: Feedback resistor, R2: Feedback resistor, 10: First switch group, 12: Second Switch group, 14 ... input switch, SW1 ... first switch, SW2 ... second switch, SW3 ... third switch, SW4 ... fourth switch, SW5 ... fifth switch, SW6 ... sixth switch, 20 ... pulse modulator, 21 ... Voltage source, 21a ... Counter, 21b ... Voltage source, 22 ... Error amplifier, 24 ... Oscillator, 26 ... PWM comparator, 8 ... maximum duty comparator, 30 ... the AND gate, 32 ... minimum duty comparator, 34 ... PFM controller, 40 ... driver, Vin1 ... first input voltage, Vin2 ... second input voltage, Vout ... output voltage.

Claims (10)

A charge pump circuit control circuit having a flying capacitor and an output capacitor,
A first switch provided between a first input terminal to which a first input voltage is applied and one end of the flying capacitor;
A second switch provided between the other end of the flying capacitor and a fixed voltage terminal;
A third switch provided between a second input terminal to which a second input voltage is applied and the other end of the flying capacitor;
A fourth switch provided between the one end of the flying capacitor and one end of the output capacitor;
A period corresponding to a high period of a pulse signal, turning on one of the first pair of the first and second switches, or the second pair of the third and fourth switches, and a period corresponding to the low period; A driver to turn on the other pair;
With
The driver turns on the first and fourth switches to charge the output capacitor during a predetermined precharge period from the start of activation of the charge pump circuit, and then charges the output capacitor based on the pulse signal. A control circuit that turns on and off the second pair alternately. When the first input voltage is higher than the second input voltage;
The driver turns on the third switch in addition to the first and fourth switches and turns off the second switch during the precharge period, thereby connecting the flying capacitor to the first input voltage and the first switch. The control circuit according to claim 1, wherein charging is performed with a differential voltage of the second input voltage. When the first input terminal and the second input terminal are connected in common, and the first input voltage and the second input voltage are equal,
The control circuit according to claim 1, wherein the driver turns off the second switch during the precharge period. A pulse modulator that generates a pulse signal in which a duty ratio is adjusted so that a feedback voltage corresponding to an output voltage of the charge pump circuit matches a predetermined reference voltage;
The pulse modulator increases the reference voltage with time after the precharge period ends, and the driver drives the first switch to the fourth switch based on the pulse signal. Item 4. The control circuit according to any one of Items 1 to 3. An input switch provided on a path from the first input terminal to the output capacitor and capable of switching on-resistance;
The driver turns on the input switch in a high on-resistance state for a predetermined soft start period from the start of activation of the charge pump circuit, and then switches the on-resistance of the input switch to a low state. The control circuit according to claim 1.   The control circuit according to claim 5, wherein the input switch is provided between the first switch and the first input terminal.   The control circuit according to claim 5, wherein the input switch includes a plurality of MOSFETs connected in parallel, and the on-resistance is switched by a combination of ON and OFF of the plurality of MOSFETs.   8. The first and fourth switches are MOSFETs, and the body diodes of the plurality of MOSFETs of the input switch are provided in opposite directions to the body diodes of the first and fourth switches, respectively. Control circuit according to.   The control circuit according to claim 4, wherein the pulse modulator performs pulse width modulation in which a period is constant and a pulse width is changed. A flying capacitor,
An output capacitor;
The control circuit according to any one of claims 1 to 3, which controls charge / discharge states of the flying capacitor and the output capacitor;
A charge pump circuit comprising:

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