JP5209106B2 - Semiconductor device manufacturing method - Google Patents

Description

  The present invention relates to a semiconductor device manufacturing method, and more particularly to a semiconductor device manufacturing method including a metal conductor film forming step of forming a metal conductor film on a barrier metal film by a CVD method.

In a semiconductor device manufacturing process such as a wafer process, a metal conductor film (pattern) is formed on a substrate made of a Si wafer, a glass plate, or the like. At this time, in order to prevent the metal ions or atoms of the metal conductor film from diffusing into the insulator film (insulator film) and deteriorating the insulation characteristics, a barrier metal film is provided between the metal conductor film and the insulator film. To be formed. As this barrier metal film, for example, tungsten nitride (WN) is formed by a metal CVD (Chemical Vapor Deposition) method or a metal PVD (Physical Vapor Deposition) method using tungsten hexafluoride (WF ₆ ) and ammonia (NH ₃ ) as raw materials. A thin film is formed. As for the metal conductor film, as in the case of the barrier metal film, a metal conductor film as a wiring (pattern) is formed by a metal CVD method, a metal PVD method, or an electroplating method.

  By the way, in recent years, as the density of large-scale integrated circuits (hereinafter referred to as LSIs) is increased and the number of terminals is increased, the fineness of the wiring made of the metal conductor film on the substrate connecting the LSIs and the number of wirings are increased. An increase is required. In this case, a method of forming a metal conductor film such as copper (Cu) by the CVD method is preferable because fine wiring can be formed. There is a problem that peeling occurs due to a decrease in adhesion. In addition, the decrease in adhesion between the metal conductor film and the barrier metal film may cause a disconnection or a short circuit when the semiconductor device is used. On the other hand, the method of forming the metal conductor film by the PVD method is not necessarily a sufficient method in terms of forming the wiring finely, although the problem of adhesion does not become obvious.

  As described above, the difference in the adhesion between the metal conductor film and the barrier metal film due to the difference in the formation method of the metal conductor film is caused by the content of impurities in the formed metal conductor film in the PVD method. In contrast to the trace amount, the CVD method may be left as an impurity in the metal conductor film in which carbon (C), fluorine (F), etc. in the organic raw material are formed.

  On the other hand, vias (conductor parts for connection) are formed to electrically connect the wiring between insulating layers in a multilayer thin film wiring board or the like having multiple insulating layers, or are electrically connected to a semiconductor diffusion layer In order to do so, a contact is formed. Usually, aluminum (Al) or copper (Cu) is suitably used as the metal conductor film used for these vias and contacts. However, in order to increase the density of LSI, it is necessary to reduce the diameter of the via hole for forming the via and the contact hole for forming the contact and to increase the depth of the hole. Aspect ratio (depth / hole diameter) tends to increase. In such a case, as a method of forming the metal conductor film and the barrier metal film with a uniform film thickness on the bottom part and the side wall part of the via hole or the like, the above-described CVD method is suitably employed, and as the CVD material The aforementioned Cu and WN or tantalum nitride (TaN) are preferably used.

  However, in this case as well, the problem that the adhesion between the barrier metal film for covering the via and the metal conductor film is lowered cannot be avoided as in the case of forming the wiring (pattern) described above.

JP-A-9-232313 JP 2000-068232 A Japanese Patent Laid-Open No. 11-074354 JP 11-186261 A Japanese Patent Laid-Open No. 11-087353 JP-A-8-288242 Japanese Patent Laid-Open No. 10-189734

  The present invention has been made in view of the above problems, and provides a method for manufacturing a semiconductor device having excellent adhesion between a barrier metal film and a copper film that is a metal conductor film formed by a CVD method. For the purpose.

According to one aspect of the invention ,
In a semiconductor device manufacturing method including a step of forming a barrier metal film directly on a substrate or via an insulator film, and a step of forming a copper film on the barrier metal film by a CVD method.
Between the step of forming the barrier metal film and the step of forming the copper film, a step of exposing to a first reducing gas containing at least one of ammonia, hydrogen, or silane under heating conditions When,
After the step of forming the copper film, exposing to a second reducing gas under heating conditions;
After the step of exposing to the second reducing gas, a step of forming a metal conductor portion made of copper on the copper film by electroplating and completely closing the via hole or contact hole and the wiring groove ; ,
A method of manufacturing a semiconductor device is provided .

  Here, a Si wafer, a glass plate, etc. can be used for a board | substrate, and it does not specifically limit. The barrier metal film is a metal thin film for preventing the copper film from reacting with the insulator film or the substrate in the process of heating or electrical stress to deteriorate the function of the insulator film or the substrate. Further, the copper film may be a wiring pattern, or may be a conductor layer such as a via or a contact deposited in a contact hole or a via hole. These also apply to the following inventions.

  With the configuration of the above invention, the adhesion between the barrier metal film and the copper film formed by the CVD method can be improved.

  In this case, the second reducing gas is at least one of ammonia and hydrogen, and is exposed to the first reducing gas and the second reducing gas. When the process is performed at a temperature of 250 to 500 ° C., the effects of the present invention can be more suitably achieved.

  Here, each temperature refers to the atmospheric temperature in the chamber in which processing is performed, and this atmospheric temperature is substantially the same as the temperature of the formed barrier metal film or copper film.

  In this case, when the barrier metal film is formed of tungsten nitride (WN) or tantalum nitride (TaN), the effects of the present invention can be suitably achieved.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the semiconductor device excellent in the adhesiveness between the barrier metal film and the copper film which is a metal conductor film formed by CVD method is provided.

It is a flowchart which shows the procedure of the manufacturing method of the semiconductor device which concerns on the 1st example of this Embodiment. FIG. 5 is a partial cross-sectional view of a semiconductor device in a via hole and wiring groove forming step for explaining a method for manufacturing a semiconductor device according to a first example of the present embodiment; FIG. 8 is a partial cross-sectional view of a semiconductor device in a via hole and wiring groove cleaning step for explaining a method for manufacturing a semiconductor device according to a first example of the present embodiment; It is for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st example of this Embodiment, and is a fragmentary sectional view of the semiconductor device in a barrier metal film formation process. It is for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st example of this Embodiment, and is a fragmentary sectional view of the semiconductor device in a 1st reduction process process. It is for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st example of this Embodiment, and is a fragmentary sectional view of the semiconductor device in a metal conductor film formation process. It is for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st example of this Embodiment, and is a fragmentary sectional view of the semiconductor device in a metal conductor part deposition process. It is for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st example of this Embodiment, and is a fragmentary sectional view of the semiconductor device in a 2nd reduction process process. It is for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st example of this Embodiment, and is a fragmentary sectional view of the semiconductor device in a grinding | polishing process. It is a flowchart which shows the procedure of the manufacturing method of the semiconductor device which concerns on the 2nd example of this Embodiment. It is for demonstrating the manufacturing method of the semiconductor device which concerns on the 2nd example of this Embodiment, and is a fragmentary sectional view of the semiconductor device in a via hole and a wiring groove | channel formation process. FIG. 10 is a partial cross-sectional view of a semiconductor device in a via hole and wiring groove cleaning step for explaining a method for manufacturing a semiconductor device according to a second example of the present embodiment; It is for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st example of this Embodiment, and is a fragmentary sectional view of the semiconductor device in a barrier metal film formation process. It is for demonstrating the manufacturing method of the semiconductor device which concerns on the 2nd example of this Embodiment, and is a fragmentary sectional view of the semiconductor device in a plasma processing process. It is for demonstrating the manufacturing method of the semiconductor device which concerns on the 2nd example of this Embodiment, and is a fragmentary sectional view of the semiconductor device in a metal conductor film formation process. It is for demonstrating the manufacturing method of the semiconductor device which concerns on the 2nd example of this Embodiment, and is a fragmentary sectional view of the semiconductor device in a heat treatment process. It is for demonstrating the manufacturing method of the semiconductor device which concerns on the 2nd example of this Embodiment, and is a fragmentary sectional view of the semiconductor device in a metal conductor part deposition process. It is for demonstrating the manufacturing method of the semiconductor device which concerns on the 2nd example of this Embodiment, and is a fragmentary sectional view of the semiconductor device in a grinding | polishing process. It is a figure which shows an example of arrangement | positioning of the semiconductor manufacturing apparatus applied to the manufacturing method of the semiconductor device which concerns on this Embodiment. It is a figure which shows another example of arrangement | positioning of the semiconductor manufacturing apparatus applied to the manufacturing method of the semiconductor device which concerns on the example of this Embodiment. It is a figure which shows another example of arrangement | positioning of the semiconductor manufacturing apparatus applied to the manufacturing method of the semiconductor device which concerns on the example of this Embodiment. It is a figure which shows another example of arrangement | positioning of the semiconductor manufacturing apparatus applied to the manufacturing method of the semiconductor device which concerns on the example of this Embodiment. It is a figure which shows another example of arrangement | positioning of the semiconductor manufacturing apparatus applied to the manufacturing method of the semiconductor device which concerns on the example of this Embodiment. It is a figure which shows another example of arrangement | positioning of the semiconductor manufacturing apparatus applied to the manufacturing method of the semiconductor device which concerns on the example of this Embodiment.

  A preferred embodiment of a semiconductor device manufacturing method according to the present invention will be described below with reference to the drawings, taking as an example the case of forming a via by depositing a metal conductor film in a via hole.

  The semiconductor device manufacturing method according to the first example of the present embodiment will be described below with reference to the process flow diagram of FIG. 1 and the partial cross-sectional views of the semiconductor devices of FIGS.

  First, for example, after laminating a plurality of insulating layers (insulator films) 12a to 12c on a substrate 10 made of a Si wafer (in each figure, a plurality of layers are collectively displayed in a single pattern for convenience. Hereinafter, simply referred to as the insulating layer 12), via holes 14 a and wiring grooves 14 b are formed in the insulating layer 12 by steps (S 1, FIG. 2). In this case, a metal conductor layer 16 as a wiring pattern is formed on the first insulating layer 12 a formed immediately above the substrate 10. The metal conductor layer 16 is formed by, for example, CVD using Cu. In addition, between the metal conductor layer 16, and the board | substrate 10 and the insulating layer 12a, the barrier metal layer 18 formed by PVD method, for example using TaN is provided. In FIG. 3 and subsequent figures, the substrate 10 is not shown.

  Next, impurities such as polymer (denoted by reference numeral 20 in FIG. 2) generated during the etching existing in the via hole 14a and the wiring groove 14b are removed (cleaned) by wet cleaning or the like (S2, FIG. 3). ).

Next, a barrier metal film 22 is formed on the side walls of the via holes 14a and the wiring grooves 14b and the bottom of the via holes 14 (upper end surface of the metal conductor layer 16) (barrier metal film forming step: S3, FIG. 4). The barrier metal film 22 is formed by PVD such as vacuum deposition at a temperature of room temperature to about 200 ° C. under a reduced pressure of about 1 to 30 Pa (absolute pressure) using tantalum (Ta) or W as a raw material. In this case, the raw material Ta or W is nitrided by ammonia (NH ₃ ) or nitrogen (N ₂ ) gas, and changes to TaN or WN in the barrier metal film 22 after film formation.

Next, heat treatment is performed in a reducing gas atmosphere (first reduction treatment step: S4, FIG. 5). That is, as the reducing gas (first reducing gas), silicon hydride (Si _n H _{2n + 2} ), preferably monosilane (SiH ₄ ), or ammonia (NH ₃ ), hydrogen (H ₂ ), nitrogen ( N ₂ ) or the like, and in any of these reducing gas atmospheres, for example, under a vacuum of about 40 Pa, for example, at a temperature of 250 to 500 ° C., for example, at a temperature of 450 ° C., for example, for about 3 minutes. To process. At this time, for example, in the case of NH ₃ , the maximum is about 200 cm ³ (standard state) / min (min), in the case of SiH ₄ , the maximum is about 5 cm ³ (standard state) / min, and in the case of H ₂ , the maximum is about 500 cm ^3. (Standard state) / minute, one kind of each reducing gas is used alone or two or more kinds are mixed and circulated.

Next, a metal conductor film 24 is formed on the barrier metal film 22 by a CVD method (metal conductor film forming step: S5, FIG. 6). Here, as a raw material, for example, an organic metal in which a monovalent ion of Cu is contained in an organic solution is used. The organic solution is, for example, trimethylvinylsilane, allyltrimethylsilane, 2-methyl-1-hexene-3-ene, 3-hexyne-2, as a ligand for binding to Cu atoms to hexafluoroacetylacetonate. A material containing any of 5-dimethoxy, hexafluoropropyne, triethoxyvinylsilane and the like is used. Then, under a vacuum of about 10 to 10 ⁴ Pa, preferably about 27 to 133 Pa, at a temperature of about 140 to 240 ° C., preferably about 150 to 210 ° C., the source gas generated by heating is H as a carrier gas. ₂ , He, N ₂ , Ar and the like are deposited. The flow rate of the carrier gas at this time is about 500 cm ³ (standard state) / min at the maximum.

  Next, Cu is deposited on the metal conductor film 24 by electroplating to completely close the via hole 14a and the wiring groove 14b, and further form the metal conductor portion 26 so as to cover the upper surface of the insulating layer 12 (see FIG. S6, FIG. 7).

Next, heat treatment is performed in a reducing gas atmosphere (second reduction treatment step: S7, FIG. 8). That is, any one of NH ₃ , He, H ₂ , N ₂ , and Ar is used as the reducing gas (second reducing gas), and at least 10 Pa or more, for example, about 670 Pa, under a vacuum of 250 to 500 ° C. For example, at a temperature of 350 ° C. for at least about 0.5 minutes or more, for example, 5 minutes. Note that the processing time depends on the processing temperature. The flow rate of the reducing gas at this time is, for example, about 400 cm ³ (standard state) / min in the case of H ₂ .

  Here, instead of the above procedure, step 6 (S6) and step 7 (S7) may be performed in the reverse order.

  Finally, the metal conductor 26 is polished and planarized by CMP (Chemical Mechanical Polish) (S8, FIG. 9). That is, the metal conductor portion 26 is precisely polished with a polishing pad affixed to a surface plate while pouring a polishing liquid containing silica particles or the like to expose the insulating layer 12, and the upper end surface of the insulating layer 12 and the metal conductor portion 26 are The via 28 and the wiring layer 29 are formed by smoothing so that the upper end surfaces constitute the same plane.

  In addition to the above-described steps, the first reduction treatment that is exposed to the first reducing gas under heating conditions between the barrier metal film forming step and the metal conductor film forming step is performed by appropriately performing other steps. A semiconductor device manufactured by the manufacturing method according to the first example of the present embodiment is subjected to a second reduction treatment step of exposing to a second reducing gas under heating conditions after the step and the metal conductor film forming step. Complete.

  Next, a semiconductor device manufacturing method according to a second example of the present embodiment will be described below with reference to the process flow diagram of FIG. 10 and the partial cross-sectional views of the semiconductor devices of FIGS. In the semiconductor device manufacturing method according to the second example of the present embodiment, the same method as the semiconductor device manufacturing method according to the first example of the present embodiment and the same components formed by the method The description is omitted, and the same constituent elements are denoted by the same reference numerals as in the first example.

  First, step-like via holes 14a and wiring grooves 14b are formed in the insulating layer 12 by the same method as in the first example (S11, FIG. 11).

  Next, the via hole 14a and the wiring groove 14b are cleaned by the same method as in the first example (S12, FIG. 12).

Next, a barrier metal film 30 is formed on the side walls of the via holes 14a and the wiring grooves 14b and the bottom of the via holes 14 (upper end surface of the metal conductor layer 16) (barrier metal film forming step: S13, FIG. 13). The barrier metal film 30 is formed by a CVD method at a temperature of about 300 to 500 ° C. under a reduced pressure of about 10 to 500 Pa, using WF ₆ or the like as a raw material and accompanied by NH ₃ or the like. In this case, the barrier metal film 30 is nitrided by a gas containing nitrogen such as NH ₃ , and the barrier metal film 30 after film formation is changed to WN.

Then, exposure treatment is performed under a heating condition with a plasma of a reducing gas (plasma treatment step: S14, FIG. 14). That is, as the reducing gas, a _{H 2,} the _{H 2,} for example, at a temperature of 100 to 450 ° C., the hydrogen flow rate 1~500cm ³ (STP) / min or so, under pressure conditions of about 1~500Pa A high frequency of 400 KHz to 13.65 MHz is applied to form a plasma.

  Next, a metal conductor film 32 is formed on the barrier metal film 30 by CVD in the same manner as in the first example (metal conductor film formation: S15, FIG. 15).

Next, heat treatment is performed in a reducing gas atmosphere before the via hole 14a and the wiring groove 14b are completely closed to form the metal conductor portion (heat treatment step: S16, FIG. 16). That is, heat treatment is performed at a temperature of 300 to 350 ° C., for example, for 5 minutes under a vacuum of at least 10 Pa or more, for example, about 670 Pa, using H ₂ or N ₂ as the reducing gas. Note that the processing time depends on the processing temperature. The flow rate of the reducing gas at this time is, for example, about 400 cm ³ (standard state) / min.

  Next, Cu is deposited on the metal conductor film 32 by the same method as in the first example to completely close the via hole 14a and the wiring groove 14b, and further cover the upper surface of the insulating layer 12 so that the metal conductor is covered. The part 34 is formed (S17, FIG. 17).

  Finally, by the same method as in the first example, the metal conductor portion 34 is polished and planarized by the CMP method, and the via 36 and the wiring layer 37 are formed (S18, FIG. 18).

  In addition to each of the above-described steps, a plasma treatment step of exposing to a reducing gas plasma under heating conditions between the barrier metal film forming step and the metal conductor film forming step, After the conductor film formation step, a semiconductor device by the manufacturing method according to the second example of the present embodiment is completed through a heat treatment step of exposing to a reducing gas under heating conditions.

  Table 1 shows the adhesion evaluation results of the semiconductor devices obtained by the semiconductor device manufacturing method according to the first and second examples of the present embodiment described above.

ここで、バリア金属膜等を形成するベースとなる基板１０はいずれもＳｉウェハであり、金属導体膜は特に断らない限りすべてＣＶＤ法により形成したＣｕ膜である。実施例１〜４は前記本実施の形態の第１の例に対応するものであり、表１中記載のない条件は前記本実施の形態の第１の例の説明で示したとおりである。実施例５は前記本実施の形態の第２の例に対応するものであり、表１中記載のない条件は前記本実施の形態の第２の例の説明で示したとおりである。

Here, the substrate 10 serving as a base for forming the barrier metal film or the like is an Si wafer, and the metal conductor films are all Cu films formed by the CVD method unless otherwise specified. Examples 1 to 4 correspond to the first example of the present embodiment, and conditions not described in Table 1 are as described in the description of the first example of the present embodiment. Example 5 corresponds to the second example of the present embodiment, and conditions not described in Table 1 are as described in the description of the second example of the present embodiment.

  Moreover, the comparative example 1-5 showed the example which abbreviate | omitted at least 1 process of the 1st reduction process and the 2nd reduction process as a comparative example with respect to Examples 1-4. Also, a TaN film is formed as a barrier metal film by the PVD method, a Cu film is formed as an intermediate film on the TaN film by the PVD method, and then a Cu film is formed as a metal conductor film on the Cu film by the PVD method by the CVD method. And the first reduction treatment of the present invention is not performed as a reference example. The processing conditions not described in these comparative examples and reference examples conform to the conditions of the first or second example of the present embodiment.

  The evaluation of adhesion was performed by a tape test and a strength test. In the tape test, a predetermined tape is attached to the surface of the metal conductor film on the substrate, and whether the metal conductor film is peeled off from the substrate when the tape is rapidly pulled upward is visually evaluated. The tensile test method using a Sebastian measuring instrument was performed. The evaluation results for the tape test are indicated by ○ for the case where the metal conductor film does not peel and good adhesion, and x for the case where the metal conductor film peels off and the adhesion is not good. About the strength test, it evaluated by the tensile strength of the perpendicular direction when the adhesion location of a metal conductor film and a barrier metal film peels.

  When the results of Table 1 are summarized, Examples 1 to 5 have good adhesion as in the reference example. On the other hand, all of Comparative Examples 1 to 5 that omit the treatment such as the reduction treatment of the present invention have poor adhesion. In addition, although the thing of a reference example is ensuring adhesiveness similarly to an Example, since the intermediate | middle Cu layer is formed by PVD method, there exists a malfunction that it is not enough at the point which aims at the densification of wiring. .

In addition, among Examples 1 to 3 using a TaN film formed by the PVD method as the barrier metal film, the measured value of the strength test is that of Example 2 using SiH ₄ as the reducing gas in the first reduction treatment step. It was found that the largest was 74 MPa, and therefore the adhesion was the best.

Further, although not specifically described, Example 5 corresponding to the second example of the present embodiment is one in which exposure to the atmosphere is once performed for 24 hours or more before moving to the plasma treatment after forming the barrier metal film. However, good adhesion is obtained even under such conditions. On the other hand, it has been found that the adhesiveness is unfavorable when the heat treatment is performed only in a reducing gas atmosphere such as H ₂ instead of the plasma treatment.

  The following can be considered for the effects of the present invention.

First, as for the first example of the present embodiment, for example, as a result of XPS measurement of the barrier metal film of Example 2, it is known that several layers of Si are grown in the vicinity of the TaN surface layer. This Si is considered to be generated as a result of the SiH ₄ treatment in the first reduction treatment step. In view of the presence of Si, it is considered that Si and TaN react to form TaSiN on the surface layer, and the presence of TaSiN contributes to improving the adhesion between the metal conductor film and the barrier metal film. In addition, impurities such as C and F at the interface may be reduced by such a reduction treatment step. In Examples 1 and 3 using other reducing gases, the reduction of F may be performed in the same manner. The formation of an adhesive layer at the interface is assumed.

  Next, in the second example of the present embodiment, the removal of carbon, oxygen or fluorine existing on the surface of the barrier metal film by plasma treatment improves the adhesion between the metal conductor film and the barrier metal film. It is thought that it contributed.

  With respect to the semiconductor device manufacturing apparatus used in the semiconductor device manufacturing method according to the present invention described above, examples of arrangement of the apparatus (cluster tool) are shown in FIGS.

  In FIG. 19, for example, a pre-processing chamber (first processing chamber) 42, a metal conductor film forming chamber (second processing chamber) 44, and a post-processing in three directions across a central space (transfer chamber) 40 in which the transfer arm 41 is disposed. A chamber (third processing chamber) 46 is arranged. Reference numeral 43 indicates a load lock chamber. Here, the pretreatment chamber includes a barrier metal film forming means for performing the barrier metal film forming process of the first or second embodiment of the present invention and the first reduction process of the first embodiment of the present embodiment. The first reduction processing means for performing the plasma processing or the plasma processing means for performing the plasma processing of the second embodiment, and the post-treatment chamber is the second processing chamber of the first embodiment. The load lock chamber 43 is a chamber provided with a second reduction processing means for performing a reduction process or a heat treatment means for performing the heat treatment of the second embodiment. The load lock chamber 43 is a wafer without opening each processing chamber to the atmosphere. It is a vacuum chamber for taking in and taking out. The space 40, the pretreatment chamber 42, the metal conductor film formation chamber 44 and the post-treatment chamber 46 may all be provided in a confidential state as shown in FIG. 19, and only the space 40 is opened to the atmosphere. The pre-processing chamber 42, the metal conductor film forming chamber 44, and the post-processing chamber 46 may each be a confidential chamber, and a semiconductor device may be transferred into and out of the space 40 through a door. In this case, when it is necessary to provide a larger number of chambers in parallel, the chambers may be arranged in a circle around the space 40.

  20 is different from FIG. 19 in that the post-processing chamber 46 is independently disposed apart from the other chambers 42 and 44 and the space 40.

  In FIG. 21, the chamber is reduced by one from that of FIG. 19, and the pretreatment and the posttreatment are performed in one chamber 48.

  In FIG. 22, the chamber is reduced by one from that of FIG. 19 so that the pretreatment and the metal conductor film formation are performed in one chamber 50, and the post-treatment chamber 46 is independently provided in the chamber 50 and The space 40 is spaced apart.

  In FIG. 23, as a modification of FIG. 21 or FIG. 22, a pretreatment chamber 42 and a chamber 52 for performing posttreatment and metal conductor film formation are arranged to face each other with a space 40 interposed therebetween.

  In FIG. 24, only one chamber 54 for performing all the pretreatment, metal conductor film formation, and posttreatment is disposed in contact with the space 40.

  Each of the above-described device arrangements is characterized by the following points.

  First, in the case where each processing chamber and the central space are integrally connected, the integrated processing can be performed without being exposed to the atmosphere in the course of processing (FIGS. 14, 21, and 23). , FIG. 24).

  On the other hand, a chamber provided separately from each processing chamber and the central space is suitable for a case where it is preferable to perform post-processing after processing rather than consistent processing for various reasons. (FIG. 20, FIG. 22). For example, a case where electroplating is performed before post-processing is applicable. In addition, when the throughput of each process is different, it is possible to adjust the production amount such as preparing raw materials (intermediate products) for a process with a high throughput in advance to avoid a decrease in the throughput of the process. Is preferred. Furthermore, due to different processing conditions in a plurality of steps, a chamber that performs the processing may be easily damaged by performing processing under severe conditions in a specific step. By providing them independently, it is preferable that only the damaged specific room be repaired or replaced.

  Moreover, what performs a some process in one chamber is preferable from the viewpoint of the expense for providing a chamber. On the other hand, in this case, in order to perform different processing in one chamber, it takes a predetermined time to change processing conditions such as temperature, resulting in a decrease in throughput, and for this purpose, precise temperature adjustment is performed. It should be taken into account that this is not always easy.

  Considering the above characteristics of the respective device arrangements comprehensively, the device arrangements shown in FIGS. 20, 19 and 21 are considered to be more preferable in this order.

10 Substrate 12, 12a to 12c Insulating layer 14a Via hole 14b Wiring groove 22, 30 Barrier metal film 24, 32 Metal conductor film 26, 34 Metal conductor part 28, 36 Via 29, 37 Wiring layer 40 Space 41 Transport arm 42 Pre-processing Chamber 43 Load lock chamber 44 Metal conductor film formation chamber 46 Post-processing chamber 48, 50, 52, 54 chamber

Claims (5)

In a semiconductor device manufacturing method including a step of forming a barrier metal film directly on a substrate or via an insulator film, and a step of forming a copper film on the barrier metal film by a CVD method.
Between the step of forming the barrier metal film and the step of forming the copper film, a step of exposing to a first reducing gas containing at least one of ammonia, hydrogen, or silane under heating conditions When,
After the step of forming the copper film, exposing to a second reducing gas under heating conditions;
After the step of exposing to the second reducing gas, a step of forming a metal conductor portion made of copper on the copper film by electroplating and completely closing the via hole or contact hole and the wiring groove ; ,
A method for producing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein the second reducing gas is at least one of ammonia and hydrogen.   3. The method of manufacturing a semiconductor device according to claim 1, wherein the barrier metal film is formed of tungsten nitride or tantalum nitride.   The semiconductor device manufacturing method according to claim 1, wherein the step of exposing to the first reducing gas is performed at a temperature of 250 to 500 ° C. 5. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the step of exposing to the second reducing gas is performed at a temperature of 250 to 500 ° C. 6.

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