JP5142703B2 - Imaging apparatus and processing method thereof - Google Patents

Description

  The present invention relates to an imaging apparatus such as a CMOS image sensor and a processing method thereof.

  Conventionally, as an imaging device that captures, records, and reproduces still images and moving images, a memory card having a solid-state memory element is used as a recording medium, and still images and moving images captured by a solid-state imaging element such as a CCD or CMOS are recorded and reproduced. An imaging device such as an electronic camera is already known. CCD is Charge Coupled Devices, and CMOS is Complementary Metal Oxide Semiconductor.

  Also, when imaging using an image sensor, the dark pixel signal read after charge accumulation is performed in the same manner as in the main shooting without exposing the image sensor, and after charge accumulation is performed with the image sensor exposed. An arithmetic process is performed using the read main photographing pixel signal. Thereby, it is possible to perform dark noise correction processing. As a result, high-quality images can be obtained by correcting the captured pixel signals against image quality degradation such as dark current noise generated in the image sensor, fixed pattern noise caused by the readout circuit, and pixel defects due to minute flaws inherent to the image sensor. Can be obtained.

  On the other hand, the correction method using the dark pixel signal requires a large-capacity memory for one frame for storing the dark pixel signal, which increases the cost of the imaging apparatus. In addition, since it is necessary to acquire a dark pixel signal for one frame in advance before the actual shooting, the shutter release time lag is increased, which hinders comfortable shooting. In addition, since the dark pixel signal includes a random component called random noise, the fixed pattern noise can be completely suppressed only by subtracting the dark pixel signal from the main photographing pixel signal. Can not.

  As a method for solving this problem, there has been proposed a method of dividing the effective pixel region into the ineffective pixel region, averaging the pixel signals in the ineffective pixel region, and subtracting the pixel signals in the effective pixel region. . The effective pixel region outputs a signal obtained by accumulating charges generated in response to incident light in the pixel region of the image sensor. The ineffective pixel region is a pixel region in which, for example, the pixel surface having the same circuit configuration as the effective pixel region is covered with a light shielding film such as aluminum, and outputs a signal that does not depend on incident light. In this method, the averaging signal is increased by averaging the pixel signals in the ineffective pixel region, and the random noise included in the correction signal is reduced.

  Patent Document 1 aims to provide a solid-state imaging device that generates a correction signal based on pixel signals in a plurality of rows of ineffective pixel regions, increases the reliability of the correction signal, and suppresses fixed pattern noise. . In order to achieve the above object, there has been proposed a solid-state imaging device characterized by generating a correction signal for one row from a plurality of rows of light-shielded pixels and correcting a pixel signal of an effective pixel.

  Patent Document 2 is characterized in that pixel signals obtained from pixel signals in an ineffective pixel region are summed over a plurality of frames, an average value is obtained from the sum value, a correction signal is generated, and solid pattern noise is suppressed. Solid-state imaging devices have been proposed.

  In Patent Document 3, each photoelectric conversion element is read a plurality of times within one field period, and the charge of the vertical black reference detection element is read each time the reading is performed a plurality of times within one field period. An imaging apparatus has been proposed.

JP 2002-16841 A JP 2004-15712 A JP 2000-138864 A

  However, the fixed pattern noise suppression method according to the background art as described above has the following problems.

  In the solid-state imaging device proposed in Patent Document 1, there is a problem that the chip area increases when a large number of rows of ineffective pixel regions are provided in order to increase the reliability of the correction signal. That is, the influence of random noise included in the correction signal is reduced by increasing the number of rows of the ineffective pixel region used for averaging.

  In the solid-state imaging device proposed in Patent Document 2, since a pixel signal of an ineffective pixel region over a plurality of frames is necessary for generating a correction signal, a shooting mode of only one frame such as single shooting with a digital still camera is required. There was a problem that could not be used. That is, the influence of random noise included in the correction signal is reduced by increasing the number of frames of the pixel signal in the ineffective pixel region used for averaging.

  In the solid-state imaging device proposed in Patent Document 2, the influence of random noise included in the correction signal is reduced by increasing the number of pixel signals in the ineffective pixel region used for averaging. In other words, the generation of the correction signal requires a pixel signal of an ineffective pixel region over a plurality of frames, and thus there is a problem that the correction signal cannot be used in a shooting mode of only one frame such as single shooting with a digital still camera. In addition, even when the pixel signal of the ineffective pixel area can be acquired over a plurality of frames as in moving image shooting, if the number of ineffective pixel areas is small, a large number of frames are required, so the response leading to the start of shooting deteriorates. There is a problem to do. Further, there is a problem that the chip area increases if the number of frames to be integrated is reduced by increasing the ineffective pixel region.

  In order to solve the above-described problems, the present invention provides an imaging apparatus and a processing method thereof in which the influence of random noise included in the correction signal is reduced from the pixel signal of the ineffective pixel region of only one frame without increasing the chip area. It is intended to provide.

An image pickup apparatus according to the present invention includes a pixel unit including an effective pixel region of a plurality of pixels that accumulates charges generated according to incident light and outputs a signal, and a non-effective pixel region of a plurality of pixels that outputs a signal independent of incident light A plurality of vertical signal lines provided for each column of pixels in the pixel portion, and scanning the pixels in the pixel portion in units of rows to select signals of the pixels in the selected same row A vertical scanning circuit for outputting to a vertical signal line; and a horizontal scanning circuit for outputting a signal of the selected vertical signal line by scanning and selecting a signal of the plurality of vertical signal lines, the vertical scanning The circuit selects pixels in the same row in the effective pixel region once per row during one frame, and selects pixels in the same row in the non-effective pixel region multiple times per row during one frame , Further, the plurality of selected and previous A correction circuit that corrects a pixel signal of the effective pixel region using a pixel signal output by a horizontal scanning circuit, wherein the non-effective pixel region includes a first non-effective pixel region in a different row; A second ineffective pixel region, and the vertical scanning circuit selects pixels in the same row in the second ineffective pixel region a plurality of times during one frame, and the correction circuit A first correction circuit that corrects a signal of the pixel in the effective pixel region by averaging signals of the pixels selected first in the first and second ineffective pixel regions; and A second correction circuit that corrects the signal of the pixel in the effective pixel region by averaging the signal of the pixel selected after the second time, and the first correction circuit includes the first and second non-correction circuits. Averaging the pixels in the effective pixel area for each of multiple areas divided in the horizontal direction. The second correction circuit includes a feature to averaging the signals of the pixels of the second non-effective pixel region for each of the plurality of regions divided in the horizontal direction in number divided into than the first correction circuit To do.

In addition, the processing method of the imaging apparatus according to the present invention includes an effective pixel region of a plurality of pixels that accumulates charges generated according to incident light and outputs a signal, and a plurality of non-effective pixels that outputs a signal independent of incident light. A pixel portion including a region, a plurality of vertical signal lines provided for each pixel column of the pixel portion, and scanning the pixels in the pixel portion in units of rows to select the pixels in the selected same row A vertical scanning circuit for outputting a signal to the plurality of vertical signal lines; and a horizontal scanning circuit for outputting a signal of the selected vertical signal line by scanning and selecting the signals of the plurality of vertical signal lines. In the processing method of the imaging apparatus, the vertical scanning circuit selects pixels in the same row of the effective pixel region once in one frame during one frame, and the same in the non-effective pixel region during one frame. Multiple rows of pixels Selecting times, correction circuit, and a correction step of correcting the signals of the pixels of the effective pixel region by using the signals of pixels which are output by said plurality of times selected and the horizontal scanning circuit, the non The effective pixel region has a first non-effective pixel region and a second non-effective pixel region in different rows, and the vertical scanning circuit is identical to the second non-effective pixel region during one frame. Selecting a pixel in a row a plurality of times in units of rows, wherein the correcting step averages a signal of a pixel selected first in the first and second non-effective pixel regions, A first correction step for correcting the signal of the pixel, and a second correction for correcting the signal of the pixel in the effective pixel region by averaging the signal of the pixel selected after the second time of the second ineffective pixel region And having the step In the correction step, the pixels in the first and second ineffective pixel regions are averaged for each of a plurality of regions divided in the horizontal direction, and in the second correction step, the pixels in the second ineffective pixel region are averaged. The signal is averaged for each of a plurality of regions divided in the horizontal direction with a larger number of divisions than the first correction circuit .

  Even when the ineffective pixel region is narrow, the signal of the pixel can be output in a plurality of rows by selecting a plurality of times. By correcting based on the pixel signals output in a plurality of rows, the influence of random noise can be reduced. Since the ineffective pixel region can be narrowed, the chip area can be reduced. In addition, since it is not necessary to perform correction based on the signal of the pixels in the ineffective pixel region over a plurality of frames, for example, even in a single frame shooting mode such as single shooting with a digital still camera, fixed pattern noise can be suppressed with high accuracy. Can do.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a plan view of a pixel portion of the solid-state imaging device according to the first embodiment of the present invention. The solid-state imaging device according to the present embodiment includes a plurality of effective pixel regions 101 that accumulate charges generated according to incident light and output signals, and a plurality of non-effective pixel regions that output signals that do not depend on incident light. The pixel portion 100 including the pixel 102 is included. The ineffective pixel region 102 is arranged in units of rows at the top in the vertical direction of the pixel unit 100. For example, a semiconductor impurity region for storing charges is formed in the pixels of the effective pixel region 101, and a semiconductor impurity region for storing charges is not formed in the pixels of the non-effective pixel region 102.

  FIG. 2 is a circuit diagram of the pixel, readout circuit, and common output circuit of the CMOS type solid-state imaging device. The pixel 200 is configured as shown below. The photodiode 201 converts the received light into electric charges. In this example, the photodiode 201 generating the optical signal charge is grounded on the anode side. The cathode side of the photodiode 201 is connected to the gate of the amplification MOS transistor 203 via the transfer MOS transistor 202. The gate of the amplification MOS transistor 203 is connected to the source of a reset MOS transistor 204 for resetting the same, and the drain of the reset MOS transistor 204 is connected to the power supply voltage Vcc. Further, the drain of the amplification MOS transistor 203 is connected to the power supply voltage Vcc, and the source is connected to the drain of the selection MOS transistor 205.

  FIG. 3 is a block diagram illustrating a configuration example of a CMOS solid-state imaging device. The pixel unit 300 includes 3 × 3 pixels in which unit pixels 301 are arranged in three rows in the row direction and three pixels in the column direction. A CMOS type solid-state imaging device includes a vertical scanning circuit 302 that selects a readout row, a horizontal scanning circuit 303 that selects a readout column, and a readout circuit 304 that amplifies pixel signals and removes noise. The unit pixel 301 corresponds to the pixel 200 in FIG. The operation for reading out the pixel signal will be described below. A plurality of vertical signal lines 206 in FIG. 2 are provided for each column of the pixels 301 of the pixel unit 100. The vertical scanning circuit 302 outputs the signals of the selected pixels in the same row to the plurality of vertical signal lines 206 by scanning and selecting the pixels 301 of the pixel unit 100 in units of rows. The horizontal scanning circuit 303 outputs a signal of the selected vertical signal line 206 by scanning and selecting the signals of the plurality of vertical signal lines 206.

  The gate of the transfer MOS transistor 202 of the pixel 11 is connected to a first row selection line (vertical scanning line) Ptx1 that extends in the horizontal direction. The gates of similar transfer MOS transistors 202 of the pixels 12 and 13 arranged in the same row are also commonly connected to the first row selection line Ptx1. The gate of the reset MOS transistor 204 of the pixel 11 is connected to a second row selection line (vertical scanning line) Pres1 that extends in the horizontal direction. The gates of similar reset MOS transistors 204 of the pixels 12 and 13 arranged in the same row are also commonly connected to the second row selection line Pres1. The gate of the selection MOS transistor 205 of the pixel 11 is connected to a third row selection line (vertical scanning line) Psel1 that extends in the horizontal direction. The gates of similar selection MOS transistors 205 of the pixels 12 and 13 arranged in the same row are also commonly connected to the third row selection line Psel1. These first to third row selection lines Ptx1, Pres1, and Psel1 are connected to the vertical scanning circuit 302 and supplied with a signal voltage. In the remaining rows shown in FIG. 3, pixels having the same configuration and row selection lines are provided. The row selection signals Ptx1, Pres1, Psel1, Ptx2, Pres2, Psel2, and Ptx3, Pres3, Psel3 formed by the vertical scanning circuit 302 are supplied to these row selection lines. The sources of the selection MOS transistors 205 are connected to a vertical signal line 206 that extends in the vertical direction. The sources of similar selection MOS transistors 205 of pixels arranged in the same column are also connected to the vertical signal line 206. A portion surrounded by a broken line in FIG. 2 is a circuit example for one column of the reading circuit 304 shown in FIG. A pixel output Vout is connected to each vertical signal line 206. The constant current source 207 is connected to the vertical signal line 206. The feedback capacitor 210 is connected between the input and output of the amplifier 211.

  FIG. 4A is a timing chart showing a processing method of the CMOS type solid-state imaging device shown in FIGS. Prior to reading of the optical signal charge from the photodiode 201, the gate Pres1 of the reset MOS transistor 204 is set to the high level. As a result, the gate of the amplification MOS transistor 203 is reset to the reset power supply voltage. After the gate Pres1 of the reset MOS transistor 204 returns to the low level and the gate Pc0r of the clamp switch 209 becomes the high level, the gate Psel1 of the selection MOS transistor 205 becomes the high level. As a result, the reset signal (noise signal) on which the reset noise is superimposed is read to the vertical signal line 206 and clamped to the clamp capacitor 208 (C0) of each column. Next, after the gate Pc0r of the clamp switch 209 returns to the low level, the gate Pctn of the N-side transfer switch 213 becomes the high level, and the reset signal is held in the noise holding capacitor 215 (Ctn) provided in each column. . Next, the gate Pcts of the S-side transfer switch 212 becomes high level. Next, the gate Ptx1 of the transfer MOS transistor 202 becomes high level, and the optical signal charge of the photodiode 201 is transferred to the gate of the amplification MOS transistor 203, and at the same time, the optical signal is read to the vertical signal line 206. Next, after the gate Ptx1 of the transfer MOS transistor 202 returns to the low level, the gate Pcts of the S-side transfer switch 212 goes to the low level. As a result, the amount of change (optical signal) from the reset signal is read out to the signal holding capacitors 214 (Cts) provided in each column. With the operations so far, the pixel signals connected to the first row are held in the signal holding capacitors 214 and 215 (Ctn and Cts) connected to the respective columns. After the pixel signal is held in the signal holding capacitors 214 and 215, the gate Pres1 of the reset MOS transistor 204 and the gate Ptx1 of the transfer MOS transistor 202 become high level, thereby resetting the photodiode 201 to the reset power supply voltage.

  After the pixel signals are held in the signal holding capacitors 214 and 215, the gates of the horizontal transfer switches 216 and 217 in each column are sequentially set to the high level by the signal Ph (Ph1) supplied from the horizontal scanning circuit 303. The voltages held in the signal holding capacitors 214 and 215 (Cts and Ctn) are sequentially read out to the horizontal output line capacitors 218 and 219 (Chs and Chn), subjected to differential processing by the output amplifier 222, and sequentially output to the output terminal OUT. Is output. That is, the output amplifier 222 subtracts the signal of the horizontal output line capacitor 219 from the signal of the horizontal output line capacitor 218 to remove the noise component. The horizontal output line capacitors 218 and 219 (Chs and Chn) are reset to the reset voltages Vchrs and Vchrn by the reset switches 220 and 221 between the signal readings of the columns. Thus, reading of the pixels connected to the first row is completed.

  FIG. 5 is a diagram showing an example of the vertical scanning circuit 302 shown in FIG. The vertical scanning start signal is composed of a shift register circuit that sequentially transfers signals to the subsequent flip-flop 500 in synchronization with the rising edge of the vertical scanning signal PV shown in FIG. Row selection signals Ptx, Pres, Psel, output signals Pv1 to Pv5 of the flip-flop 500, and the like are connected to inputs of the AND gate 501 provided for each column. In this way, independent row selection signals are generated for each row by the vertical scanning signal PV.

  FIG. 6 is a timing chart showing the operation of the solid-state imaging device according to the present embodiment. In the present embodiment, the ineffective pixel region 102 shown in FIG. 1 is arranged for one row at the top in the vertical direction of the pixel unit 100. In the present embodiment, a row selection signal Pv1 for selecting the first row is output for four horizontal scanning periods in order to output the pixel signals of the ineffective pixel region for one row arranged at the top of the pixel portion for four horizontal scanning periods. It is a thing. In order to generate the row selection signal Pv1, as shown in FIG. 4B, the vertical scanning signal PV is set to the low level for 2 to 4 horizontal scanning periods, and the shift operation of the shift register circuit shown in FIG. Has stopped. In this way, the pixel signals in the first row are repeatedly output over four horizontal scanning periods.

  Here, in this specification, one horizontal scanning period is a period obtained by adding a period (horizontal blank period) in which an optical signal is subjected to voltage conversion and transferred to an internal capacitor, and a period in which a pixel signal is scanned and read (horizontal transfer period). This represents the length to read out the pixel signals for a row. In FIG. 4, a period in which the horizontal selection signals ph1, ph2,... Are input is a “horizontal transfer period”, and a period before that is a “horizontal blank period”. One horizontal scanning period is an interval of horizontal synchronizing signals.

  Thereafter, by repeating the timing chart shown in FIG. 4A again, the pixel signals connected to the second and subsequent rows are sequentially read out by signals from the vertical scanning circuit 302, and all pixels are read out. Complete. In the second and subsequent rows, the pixel signals of the effective pixel region 101 in each row are output for each horizontal scanning period (once).

  Thus, a period from the start of the pixel signal readout operation of the first row constituting the pixel unit 100 to the end of readout of the pixel signal of the last row is defined as one frame period.

  FIG. 7 is a conceptual diagram describing signal levels of pixel signals read by the solid-state imaging device according to the present embodiment. In the present embodiment, the pixels in the ineffective pixel region are constituted by NULL pixels that do not form a semiconductor impurity region for accumulating charges. The number of rows in the ineffective pixel area is one. Since the pixel signal 702 in the ineffective pixel region 700 is a NULL pixel signal, the signal level is a reference for the black level of the captured image. By reading out the pixel signal of the ineffective pixel region 700 having only one row at the timing shown in FIG. After reading out the NULL pixel signals 702 for four rows, the row selection signal starts to be output again, and the effective pixel signal 703 of the effective pixel region 701 that outputs a signal in which charges generated according to incident light are output is output for each row. Output to.

  FIG. 8 is a block diagram including a pixel signal correction circuit of the solid-state imaging device according to the present embodiment. Reference numeral 800 denotes a pixel portion, reference numeral 801 denotes an ineffective pixel area, reference numeral 802 denotes an effective pixel area, reference numeral 803 denotes a vertical scanning circuit, reference numeral 804 denotes a readout circuit, and reference numeral 805 denotes a horizontal scanning circuit. The analog pixel signal output from the readout circuit 804 by the above operation is digitized by the AD converter 806. The average value for each column of the pixel signals in the ineffective pixel region 801 increased to four rows is calculated by the averaging circuit 807. The calculated average value for each column is stored in the memory 808. By subtracting the stored average value for each column by the subtractor 809 from the pixel signal in the effective pixel region 802, the fixed pattern noise generated for each column can be accurately suppressed.

  The vertical scanning circuit 302 selects pixels in the same row of the pixel unit 100 a plurality of times in units of rows during one frame. Specifically, the vertical scanning circuit 302 selects pixels in the same row in the effective pixel region 101 once in a frame, and selects pixels in the same row in the ineffective pixel region 102 in one frame. Select multiple times per line. For example, the first row of pixels is selected four times. The correction circuit includes the averaging circuit 807, the memory 808, and the subtractor 809 shown in FIG. 8, and the pixels of the effective pixel region 101 are selected using the pixel signals selected a plurality of times and output from the horizontal scanning circuit 303. Correct the signal. Specifically, the correction circuit averages the signals of the pixels selected a plurality of times and corrects the signals of the pixels in the effective pixel region 101.

  In the present embodiment, the pixels in the ineffective pixel region are constituted by NULL pixels that do not form a semiconductor impurity region for accumulating charges. However, if the charge accumulation period is short or the dark current of the photodiode itself is small, the pixels in the ineffective pixel area are shielded from light by covering the surface of the pixel having the same circuit configuration as the effective pixel area with a light shielding film such as aluminum. Even if it is composed of pixels, the effect of this embodiment does not change.

  In this embodiment, line memory for the number of horizontal pixels is required to store the average value for each column in the memory, but the number of memories for storing the number of horizontal pixels divided into several areas is reduced. Even so, the effect of this embodiment does not change.

  In this embodiment, the number of pixels of the ineffective pixel area to be averaged is one row, but the effect of this embodiment does not change even if the number of rows is increased so as not to reduce the chip area. A more accurate average value can be calculated by increasing the number of parameters for reading out multiple rows of ineffective pixel regions a plurality of times.

(Second Embodiment)
The second embodiment of the present invention is an embodiment similar to the first embodiment, but there is a method for suppressing fixed pattern noise using a timing chart showing the operation of the solid-state imaging device and a pixel signal in an ineffective pixel region. Different. Hereinafter, the present embodiment will be described in detail with reference to the drawings.

  FIG. 9 is a timing chart illustrating an operation example of the solid-state imaging device according to the second embodiment of the present invention. In the present embodiment, the ineffective pixel region 102 shown in FIG. 1 is arranged for two rows at the top in the vertical direction of the pixel unit 100. The row selection signal Pv2 for selecting the second row is output for five rows in order to output the pixel signals of the second row in the two invalid rows of ineffective pixel regions arranged at the top of the pixel portion. is there. In order to generate this row selection signal Pv2, as shown in FIG. 4B, the vertical scanning signal PV is set to the low level for 3 to 6 horizontal scanning periods, and the shift operation of the shift register circuit shown in FIG. Has stopped. In this way, the pixel signals in the second row are repeatedly output over five rows.

  After that, by repeating the timing chart shown in FIG. 4A again, the pixel signals connected in the third and subsequent rows are sequentially read out by the signal from the vertical scanning circuit, and the reading of all the pixels is completed. To do. Rows other than the second row are output one horizontal scanning period (once).

  Thus, a period from the start of the pixel signal readout operation of the first row constituting the pixel portion to the end of readout of the pixel signal of the last row is defined as one frame period.

  FIG. 10 is a conceptual diagram describing signal levels of pixel signals read by the solid-state imaging device according to the present embodiment. In the present embodiment, the pixels in the ineffective pixel region are configured by light-shielding pixels in which the pixel surface having the same circuit configuration as that of the effective pixel region is covered with a light-shielding film such as aluminum. The number of rows of the ineffective pixel area is two. The first row is the first ineffective pixel area 1000 and the second row is the second ineffective pixel area 1001. Since the pixel signal 1003 of the first ineffective pixel region 1000 is a light-shielded pixel signal, a pixel signal level affected by a dark current depending on temperature and accumulation time is output. Subsequently, the pixel signal 1004 of the second ineffective pixel region 1001 to be read out has a pixel signal level that is affected by the dark current in the same manner as the pixel signal 1003 of the first ineffective pixel region 1000. By reading out pixel signals at the timing shown in FIG. 9, the pixel signals in the second ineffective pixel region 1001 having only one row can be read out by increasing the number to five rows. As shown in FIG. 4B, the pixel signal read out for the second time and thereafter is reset in the photodiode and the signal holding capacitor in the immediately preceding horizontal scanning period. The pixel signal 1005 is affected. The length of one general horizontal scanning period is about several tens of microseconds, and the influence of dark current can be almost ignored in such an accumulation period. After reading out the pixel signals of these ineffective pixel regions, the row selection signal is output again, and the effective pixel signal 1006 of the effective pixel region 1002 that outputs a signal in which charges generated according to incident light are output is output. . In the non-effective pixel regions 1000 and 1001 having only two rows at the timing of FIG. 9, the data 1003 and 1004 for two rows of pixel signals affected by the dark current and the pixel signals for four rows that are hardly affected by the dark current. Data 1005 can be acquired during one frame.

  FIG. 11 is a conceptual diagram illustrating a correspondence between an average value of pixel signals read by the solid-state imaging device according to the present embodiment and an average value calculation region. Reference numeral 1100 denotes a first ineffective pixel area, reference numeral 1101 denotes a second ineffective pixel area, and reference numeral 1102 denotes an effective pixel area.

FIG. 12 is a block diagram including a pixel signal correction circuit of the solid-state imaging device according to the present embodiment. Reference numeral 1200 denotes a pixel portion, 1201 denotes a first ineffective pixel area, 1202 denotes a second ineffective pixel area, 1203 denotes an effective pixel area, 1204 denotes a vertical scanning circuit, 1205 denotes a readout circuit, and 1206 denotes a horizontal scanning circuit. The analog pixel signal output from the readout circuit 1205 by the above-described operation is digitized by the AD converter 1207.
Pixel signal of the first ineffective pixel area 1201 (pixel signal of the first row = pixel signal of the first row) and pixel signal of the second ineffective pixel area 1202 (first pixel signal of the second row) = The pixel signal of the second row) is averaged by the first averaging circuit 1208. In the first averaging circuit 1208, as shown in FIG. 11, the average value for each region divided into three in the horizontal direction is calculated and stored in the first memory 1209. Unlike the averaging method for each column, the average value can be increased by calculating the average value for each area composed of a plurality of pixels. The value can be obtained. Next, the pixel signal of the second ineffective pixel region 1202 (second pixel signal of the second row to fifth pixel signal = pixel signal of the third row to sixth row) is subjected to the second averaging. An average value is calculated by the circuit 1210. In the second averaging circuit 1210, as shown in FIG. 11, the average value for each column is calculated and stored in the second memory 1211. Since averaging is performed for each column, four rows of pixel signals are used in this embodiment in order to increase the number of parameters to be averaged. The two average values calculated in this way are subtracted by the subtracting circuits 1212 and 1213 from the pixel signal of the effective pixel region 1203. As shown in FIG. 12, for the purpose of canceling the effect of subtracting the two average values, the adder circuit 1215 may add an offset 1214 for black level adjustment to the output signal of the subtractor circuit 1213. By using this embodiment by the above method, the influence of the dark current of the solid-state imaging device and the fixed pattern noise generated for each column can be accurately suppressed.

  The non-effective pixel area includes a first non-effective pixel area 1201 and a second non-effective pixel area 1202 in different rows. The vertical scanning circuit 1204 selects pixels in the same row in the second ineffective pixel region 1202 a plurality of times in units of rows during one frame. The correction circuit includes a first correction circuit and a second correction circuit. Specifically, the correction circuit includes averaging circuits 1208 and 1210, memories 1209 and 1211, subtracters 1212 and 1213, and an adder 1215. The first correction circuit includes an averaging circuit 1208, a memory 1209, and a subtractor 1212, and averages the signals of the pixels selected first in the first ineffective pixel region 1201 and the second ineffective pixel region 1202. To correct the signal of the pixel in the effective pixel region 1203. The second correction circuit includes an averaging circuit 1210, a memory 1211, and a subtractor 1213, and averages the signals of the pixels selected after the second time in the second ineffective pixel region 1202, so that the pixels in the effective pixel region 1203 Correct the signal. The first correction circuit averages the pixels of the first ineffective pixel region 1201 and the second ineffective pixel region 1202 for each of a plurality of regions (for example, three regions) divided in the horizontal direction. The second correction circuit averages the signals of the pixels in the second non-effective pixel area 1202 for each of a plurality of areas divided in the horizontal direction by a larger number of divisions than the first correction circuit.

  In this embodiment, the number of pixels of the non-effective pixel area to be averaged is two rows, but the effect of this embodiment does not change even if the number of rows is increased so as not to reduce the chip area. A more accurate average value can be calculated by increasing the number of parameters for reading out multiple rows of ineffective pixel regions a plurality of times.

  In this embodiment, the non-effective pixel area is configured by a light-shielding pixel in which the pixel surface having the same circuit configuration as that of the effective pixel area is covered with a light-shielding film such as aluminum. However, the pixels in the second ineffective pixel region are pixels that are hardly affected by the dark current because one pixel signal affected by the dark current is a NULL pixel that does not form a semiconductor impurity region for accumulating charges. Even if the average value is calculated with five rows of signals, the effect of this embodiment does not change.

(Third embodiment)
The third embodiment of the present invention is an embodiment similar to the first embodiment, but the timing chart showing the operation of the solid-state imaging device in the ineffective pixel area that is repeatedly read is different. Hereinafter, the present embodiment will be described in detail with reference to the drawings.

  FIG. 9 is a timing chart showing the operation of the solid-state imaging device according to the third embodiment of the present invention. In the present embodiment, the ineffective pixel region 102 shown in FIG. 1 is arranged for two rows at the top in the vertical direction of the pixel unit 100. The row selection signal Pv2 for selecting the second row is output for five horizontal scanning periods in order to output the pixel signal of the second row in the two invalid pixel regions arranged at the head of the pixel portion for five horizontal scanning periods. Is. In order to generate the row selection signal Pv2, as shown in FIG. 13, the vertical scanning signal PV is set to the low level for 3 to 6 horizontal scanning periods, and the shift operation of the shift register circuit shown in FIG. 5 is stopped. ing. In this way, the pixel signals in the second row are repeatedly output over five horizontal scanning periods. The operation of the second row that is repeatedly read is different only in that the optical signal charge is not transferred to the amplification MOS transistor 203 by the selection signal Ptx1. The pixel signal read at the timing shown in FIG. 13 becomes a black level output that does not depend on the dark current generated by the photodiode.

  After that, by repeating the timing chart shown in FIG. 4A again, the pixel signals connected in the third and subsequent rows are sequentially read out by the signal from the vertical scanning circuit, and the reading of all the pixels is completed. To do.

  Thus, a period from the start of the pixel signal readout operation of the first row constituting the pixel portion to the end of readout of the pixel signal of the last row is defined as one frame period.

  The method for suppressing the fixed pattern noise in the effective pixel region using the pixel signal in the non-effective pixel region is the same as in the first embodiment, and thus the description thereof is omitted.

  In this embodiment, the pixels in the ineffective pixel area are light-shielded pixels in which the surface of the pixel having the same circuit configuration as that of the effective pixel area is covered with a light-shielding film such as aluminum, even if a NULL pixel does not form a semiconductor impurity region for accumulating charges. However, it may be composed of pixels having the same circuit configuration as the effective pixel region.

(Fourth embodiment)
The fourth embodiment of the present invention is an embodiment similar to the first embodiment, but the timing chart showing the operation of the solid-state imaging device in the ineffective pixel region that is repeatedly read is different. Hereinafter, the present embodiment will be described in detail with reference to the drawings.

  FIG. 14 is a circuit diagram of a pixel, a readout circuit, and a common output circuit of a solid-state imaging device according to the fourth embodiment of the present invention. The difference between this embodiment and the first to third embodiments is that a MOS transistor switch 1423 for resetting the voltage level of the vertical signal line 1406 to the reference voltage Voutr is arranged. The MOS transistor switch 1423 is provided for each vertical signal line 1406 and is a switch for connecting the vertical signal line 1406 to the reference voltage Voutr. FIG. 15 shows the operation timing of the row of the ineffective pixel area that is repeatedly read.

  Since it is not necessary to read out the electric charge generated in the photodiode 1401, the gate Pres1 of the reset MOS transistor 1404 is held at a high level. As a result, the gate of the amplification MOS transistor 1403 is continuously reset to the reset power supply voltage. The vertical signal line 1406 is reset to the reset voltage Voutr by setting the gate Pvoutr1 of the MOS transistor switch 1423 to the high level. At this time, after the gate Pc0r of the clamp switch 1409 becomes high level, the gate Psel1 of the selection MOS transistor 1405 becomes high level, whereby the reset signal Voutr is clamped to the clamp capacitor 1408 (C0) of each column. . Next, after the gate Pc0r of the clamp switch 1409 returns to the low level, the gate Pctn of the N-side transfer switch 1413 becomes the high level, and the reset signal is held in the noise holding capacitor 1415 (Ctn) provided in each column. . Next, the gate Pctn of the N-side transfer switch 1413 becomes low level, and the gate Pcts of the S-side transfer switch 1412 becomes high level. Next, the gate Pcts of the S-side transfer switch 1412 becomes low level. As a result, the reset signal is read again to the signal holding capacitors 1414 (Cts) provided in each column. By the operation so far, the reset signal connected to the first row is held in the signal holding capacitors 1414 and 1415 (Ctn, Cts) connected to the respective columns. The constant current source 1407 is connected to the vertical signal line 1406. The feedback capacitor 1410 is connected between the input and output of the amplifier 1411.

  After the pixel signals are held in the signal holding capacitors 1414 and 1415, the gates of the horizontal transfer switches 1416 and 1417 in each column are sequentially set to the high level by the signal Ph1 supplied from the horizontal scanning circuit. The voltages held in the signal holding capacitors 1414 and 1415 (Cts and Ctn) are sequentially read out to the horizontal output line capacitors 1418 and 1419 (Chs and Chn), subjected to differential processing by the output amplifier 1422, and sequentially output to the output terminal OUT. Is output. The horizontal output lines 1418 and 1419 (Chs and Chn) are reset to the reset voltages Vchrs and Vchrn by the reset switches 1420 and 1421 between the signal readings of the columns. Thus, reading of the pixels connected to the first row is completed.

  In this embodiment, since the same charge according to the reset voltage Voutr of the vertical signal line 1406 is held in the two signal holding capacitors 1414 and 1415, the output terminal OUT subjected to differential processing by the output amplifier 1422 has A black level signal is output.

  After that, by repeating the timing chart shown in FIG. 4A again, the pixel signals connected in the third and subsequent rows are sequentially read out by the signal from the vertical scanning circuit, and the reading of all the pixels is completed. To do.

  Thus, a period from the start of the pixel signal readout operation of the first row constituting the pixel portion to the end of readout of the pixel signal of the last row is defined as one frame period.

  The method for suppressing the fixed pattern noise in the effective pixel region using the pixel signal in the non-effective pixel region is the same as in the first embodiment, and thus the description thereof is omitted.

(Fifth embodiment)
The fifth embodiment of the present invention is an embodiment similar to the first embodiment, but there is a method for suppressing fixed pattern noise using a timing chart showing the operation of a solid-state imaging device and pixel signals in an ineffective pixel region. Different. Hereinafter, the present embodiment will be described in detail with reference to the drawings.

  FIG. 16 is a timing chart showing the operation of the solid-state imaging device according to the fifth embodiment of the present invention. In the present embodiment, the ineffective pixel region 102 shown in FIG. 1 is arranged for two rows at the top in the vertical direction of the pixel unit 100. In order to output two invalid rows of ineffective pixel regions arranged at the top of the pixel portion, two rows of row selection signal Pv1 for selecting the first row and row selection signal Pv2 for selecting the second row It is the output. In this embodiment, the row selection signal is returned to the first row by inputting again the vertical search start signal PVST which is the start signal of the vertical scanning circuit shown in FIG. 5 after outputting the row selection signal of the second row. .

  FIG. 17 is a conceptual diagram describing signal levels of pixel signals read by the solid-state imaging device according to the present embodiment. In the present embodiment, the pixels in the ineffective pixel region 1700 are composed of NULL pixels that do not form a semiconductor impurity region for accumulating charges. The ineffective pixel region 1700 has two rows. Since the pixel signal 1702 of the ineffective pixel region 1700 is a NULL pixel signal, the signal level is a reference for the black level of the captured image. By reading out the pixel signals in the ineffective pixel region which originally has only two rows at the timing shown in FIG. 16, the number of pixels can be read out by increasing to four rows. After reading out the NULL pixel signals 1702 for four rows, the row selection signal starts to be output again, and the effective pixel signal 1703 of the effective pixel region 1701 that outputs a signal in which charges generated according to incident light are output is output. .

  After that, by repeating the timing chart shown in FIG. 4A again, the pixel signals connected to the second and subsequent rows are sequentially read by signals from the vertical scanning circuit, and the reading of all pixels is completed. To do.

  Thus, a period from the start of the pixel signal readout operation of the first row constituting the pixel portion to the end of readout of the pixel signal of the last row is defined as one frame period.

  The method for suppressing the fixed pattern noise in the effective pixel region 1701 using the pixel signal in the ineffective pixel region 1700 is the same as that in the first embodiment, and thus the description thereof is omitted.

(Sixth embodiment)
Hereinafter, a sixth embodiment of the present invention will be described in detail with reference to the drawings.
FIG. 18 is a plan view of a pixel portion of a solid-state imaging device according to the sixth embodiment of the present invention, and a conceptual diagram describing signal levels of read pixel signals. The solid-state imaging device according to the present embodiment includes a plurality of effective pixel regions 1801 for accumulating charges generated according to incident light and outputting signals, and a plurality of non-effective pixel regions for outputting signals independent of incident light. A pixel portion 1800 including 1802 is provided. In this embodiment, the pixel signal of the ineffective pixel region 1802 arranged in one column at the top in the horizontal direction of the pixel portion 1800 is read out four times during one horizontal scanning period.

  Since the circuit configuration and block diagram of the solid-state imaging device according to this embodiment are the same as those of the first embodiment, detailed description thereof is omitted.

  FIG. 19 is a timing chart for one horizontal scanning period of the solid-state imaging device according to the present embodiment. By selecting the horizontal selection signal Ph1 for selecting the first column repeatedly four times, and selecting the horizontal selection signals Ph2 to Ph5 etc. sequentially for the second column and thereafter, only the pixel signals of the first column can be read four times. . At this time, while the first column is selected, the reset signal Pchres of the signal holding capacitor is fixed to a low level, so that the pixel signal of the first column can be read out a plurality of times while being held in the signal holding capacitor. .

  FIG. 8 is a block diagram including a pixel signal correction circuit of the solid-state imaging device according to this embodiment except for the pixel unit 800. A pixel portion 1800 in FIG. 18 is provided instead of the pixel portion 800. The analog pixel signal output from the readout circuit 804 by the above operation is digitized by the AD converter 806. An average circuit 807 calculates the row average value of the pixel signals of the ineffective pixels increased to four columns. The calculated row average value is stored in the memory 808. The stored row average value is subtracted by the subtractor 809 from the pixel signal in the effective pixel region 802. Similarly, by performing the above-described row average value calculation operation and subtraction processing sequentially in units of rows, it is possible to accurately suppress horizontal stripe-like fixed pattern noise that occurs for each row.

  As described above, according to the present embodiment, the horizontal scanning circuit 805 selects the same pixel of the pixel unit 1800 a plurality of times during one horizontal scanning period. Specifically, the horizontal scanning circuit 805 selects the same pixel in the ineffective pixel region 1802 a plurality of times during one horizontal scanning period. For example, select four times. A semiconductor impurity region for accumulating charges is formed in the pixels of the effective pixel region 1801, and a semiconductor impurity region for accumulating charges is not formed in the pixels of the non-effective pixel region 1802. The correction circuit includes an averaging circuit 807, a memory 808, and a subtractor 809, and uses the pixel signal selected by the plurality of times and output by the horizontal scanning circuit 805 to output the pixel signal of the effective pixel region 1801. to correct. Specifically, the correction circuit averages the signals of the pixels selected a plurality of times and corrects the signals of the pixels in the effective pixel region 1801.

  In this embodiment, even if the pixels in the ineffective pixel region are configured by light-shielding pixels in which the surface of the pixel having the same circuit configuration as that of the effective pixel region is covered with a light-shielding film such as aluminum, the semiconductor impurity region for accumulating charges is formed. You may comprise the NULL pixel which is not formed.

  In this embodiment, the number of pixels of the ineffective pixel area to be averaged is one column. However, the effect of this embodiment is not changed even if the number of columns is increased so as not to reduce the chip area. A more accurate average value can be calculated by increasing the number of parameters of reading and averaging a plurality of columns of ineffective pixel regions.

(Seventh embodiment)
FIG. 20 is a plan view of a pixel portion of a solid-state imaging device according to the seventh embodiment of the present invention, and a conceptual diagram describing signal levels of read pixel signals. The solid-state imaging device according to this embodiment includes an effective pixel region 2002 that outputs a signal in which charges generated according to incident light are accumulated, a first ineffective pixel region 2000, and a second ineffective pixel region 2001. It consists of two pixel areas. The first non-effective pixel region 2000 is configured by a light-shielded pixel in which the pixel surface having the same circuit configuration as that of the effective pixel region 2002 is covered with a light-shielding film such as aluminum. The second ineffective pixel region 2001 is configured by a NULL pixel that does not form an impurity region for accumulating charges.

  Since the pixel signals in the first ineffective pixel region 2000 in the two rows are light-shielded pixel signals, a pixel signal level 2003 that is affected by dark current depending on temperature and accumulation time is output. Since the pixel signals in the second ineffective pixel region 2001 in the two rows are NULL pixel signals, a signal level 2005 serving as a reference for the black level of the captured image is output. Reference numeral 2004 denotes a pixel signal level of the effective pixel region 2002.

  FIG. 21 is a conceptual diagram showing a driving method of the solid-state imaging device according to this embodiment, and performs a so-called focal plane shutter operation. The time for one frame is 1/60 seconds, for example. In FIG. 21, the accumulation time of the first ineffective pixel area 2000 and the effective pixel area 2002 is 1 frame (1/60 seconds), but the readout scan and the reset scan are performed separately, so that the accumulation time is 1 frame or less. Even if the accumulation time is realized, the effect of this embodiment does not change. In this embodiment, pixel signals are read in the order of the first ineffective pixel area 2000 -the effective pixel area 2002 -the second ineffective pixel area 2001. When the period of one frame is fixed as in moving image shooting, many NULL pixel signals are acquired by repeatedly reading the second ineffective pixel area 2001 a plurality of times in the surplus time after reading the effective pixel area 2002. can do. In FIG. 21, for example, the NULL pixel signal for 12 rows is acquired by repeatedly scanning the second ineffective pixel region 2001 having only 2 rows 6 times during one frame.

  In the present embodiment, since the second non-effective pixel area 2001 is repeatedly read a plurality of times in the surplus time after the effective pixel area 2002 is read, the parameter of the NULL pixel signal to be averaged while maintaining the frame rate. The correction data with high accuracy can be acquired by increasing

  Furthermore, even if the acquired NULL pixel signal is averaged over a plurality of frames to increase the parameter of the NULL pixel signal to be further averaged to acquire highly accurate correction data, the effect of this embodiment does not change.

  FIG. 22 is a conceptual diagram illustrating a correspondence between an average value of pixel signals read by the solid-state imaging device according to the present embodiment and an average value calculation region. For simplification of description, the first ineffective pixel region 2200 has two rows, the effective pixel region 2202 has 98 rows, and the second ineffective pixel region 2201 has two rows. In the first ineffective pixel region 2200, an average value is calculated for each region obtained by dividing a row into three in the horizontal direction. The second non-effective pixel area 2201 calculates an average value for each column.

  FIG. 23 is a block diagram including a pixel signal correction circuit of the solid-state imaging device according to the present embodiment. 12, 2300 is a pixel portion, 2301 is a first ineffective pixel region, 2302 is a second ineffective pixel region, 2303 is an effective pixel region, 2304 is a vertical scanning circuit, 2305 is a readout circuit, and 2306 is This is a horizontal scanning circuit.

  As described above, the vertical scanning circuit 2304 selects the first row of the second non-effective pixel region 2302 again after selecting the last row of the second non-effective pixel region 2302 to select the second non-effective pixel region 2302. Are sequentially scanned. Thereby, the second ineffective pixel region 2302 is repeatedly scanned. As shown in FIG. 21, the vertical scanning circuit 2304 repeats the second ineffective pixel area 2302 in a period from the completion of scanning of the effective pixel area 2303 of the Nth frame to the start of scanning of the effective pixel area 2303 of the (N + 1) th frame. Scan.

  The pixel signal output from the readout circuit 2305 by the above operation is digitized by the AD converter 2307. The digitized pixel signal is stored in the frame memory 2316, and is read out by the first averaging circuit 2308, the second averaging circuit 2310, and the subtraction circuit 2312 when appropriate.

  Pixel signal of the first ineffective pixel area 2301 read from the frame memory 2316 (pixel signal of the first row to second row = pixel signal written to the first row to second row of the frame memory) ) Is calculated by the first averaging circuit 2308. In the first averaging circuit 2308, as shown in FIG. 22, the average value for each region divided into three in the horizontal direction is calculated and stored in the first memory 2309. Unlike the averaging method for each column, the average value can be increased by calculating the average value for each area composed of multiple pixels. The value can be obtained.

  Pixel signals of the second ineffective pixel area 2302 read from the frame memory 2316 (pixel signals of the 100th to 101st rows × 6 times = written to the 100th to 111th rows of the frame memory) The average value of the pixel signal) is calculated by the second averaging circuit 2310. In the second averaging circuit 2310, the average value for each column is calculated and stored in the second memory 2311 as shown in FIG. Since averaging is performed for each column, pixel signals for 12 rows are used in this embodiment in order to increase the number of parameters to be averaged.

  Next, calculation is performed for the pixel signal of the effective pixel area 2303 from the frame memory 2316 (pixel signals in the third to 99th rows = pixel signals written in the third to 99th rows of the frame memory). The two average values are subtracted by the subtracting circuits 2312 and 2313, respectively. As shown in FIG. 23, for the purpose of canceling the effect of subtracting the two average values, the adder circuit 2315 may add an offset 2314 for black level adjustment to the output signal of the subtractor circuit 2313.

  The non-effective pixel area includes a first non-effective pixel area 2301 and a second non-effective pixel area 2302 in different rows. The pixels in the first ineffective pixel region 2301 are light-shielding pixels in which the surface of a pixel in which a semiconductor impurity region for accumulating charges is formed is covered with a light-shielding film. A pixel in the second ineffective pixel region 2302 is a pixel in which a semiconductor impurity region for accumulating charges is not formed. The vertical scanning circuit 2304 selects pixels in the same row in the effective pixel region 2303 once in a unit of frame during one frame, and selects pixels in the same row of the second ineffective pixel region 2302 in a unit of row during one frame. Select multiple times with. The correction circuit has a first correction circuit and a second correction circuit. The first correction circuit includes a first averaging circuit 2308 and a subtraction circuit 2312, and corrects the pixel signals in the effective pixel area 2303 by averaging the pixel signals in the first ineffective pixel area 2301. The second correction circuit includes a second averaging circuit 2310 and a subtraction circuit 2313, and corrects the pixel signals in the effective pixel region 2302 by averaging the pixel signals in the second ineffective pixel region 2302.

  By the above method, the influence of the dark current of the solid-state imaging device and the fixed pattern noise generated for each column can be accurately suppressed.

  In the present embodiment, the pixel signal of the effective pixel region 2303 is subtracted using the pixel signal of the first ineffective pixel region 2301 digitized by the AD converter 2307, thereby affecting the influence of the dark current of the solid-state imaging device. Was suppressed. Instead, the dark current component included in the pixel signal after AD conversion is suppressed by the AD converter 2307 by using the pixel signal of the first ineffective pixel region 2301 for black level adjustment of the AD converter 2307. good.

  In this embodiment, the pixel signal digitized by the AD converter 2307 is temporarily stored in the frame memory 2316. However, the frame memory 2316 may be eliminated. For example, in the focal plane readout as shown in FIG. 21, the pixel signal of the second ineffective pixel area 2302 of the Nth frame is averaged by the second averaging circuit 2310 and stored in the first memory 2309. Then, the pixel signal of the first ineffective pixel region 2301 of the (N + 1) th frame is averaged by the first averaging circuit 2308 and stored in the second memory 2311. The frame memory 2316 can be omitted by subtracting the obtained two average values from the pixel signal of the effective pixel area 2303 of the (N + 1) th frame.

  As described above, according to the first to fifth embodiments, even when the number of non-effective pixel regions to be averaged is small, by selecting a plurality of row periods with a vertical selection signal during one frame. The pixel signal can be output in a plurality of rows. By calculating the correction signal by averaging pixel signals output over a plurality of row periods, it is possible to reduce the influence of random noise included in the correction signal. The same applies to the sixth and seventh embodiments. Further, since it is not necessary to have a large number of rows of ineffective pixel regions as in the background art, the chip area can be reduced.

  In addition, unlike the background art, it is not necessary to average the pixel signals of the ineffective pixel areas over a plurality of frames, so that the fixed pattern noise can be suppressed with high accuracy even in a single frame shooting mode such as single shooting with a digital still camera. can do.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

It is a pixel part top view of the solid-state imaging device concerning the 1st Embodiment of this invention. It is a circuit diagram of a pixel, a readout circuit, and a common output circuit of a CMOS type solid-state imaging device. It is a block diagram which shows the structural example of a CMOS type solid-state imaging device. It is a timing chart of the solid-state imaging device concerning the 1st Embodiment of this invention. It is a circuit diagram of the vertical scanning circuit of a CMOS type solid-state imaging device. It is a timing chart of the solid-state imaging device concerning the 1st Embodiment of this invention. It is the conceptual diagram which described the signal level of the pixel signal of the solid-state imaging device in connection with the 1st Embodiment of this invention. It is a block diagram including the pixel signal correction circuit of the solid-state imaging device according to the first embodiment of the present invention. It is a timing chart of the solid-state imaging device concerning the 2nd Embodiment of this invention. It is the conceptual diagram which described the signal level of the pixel signal of the solid-state imaging device concerning the 2nd Embodiment of this invention. It is the conceptual diagram which showed the response | compatibility with the average value of the pixel signal of the solid-state imaging device in connection with the 2nd Embodiment of this invention, and an inch calculation area | region. It is a block diagram including the pixel signal correction circuit of the solid-state imaging device concerning the 2nd Embodiment of this invention. It is a timing chart of the solid-state imaging device concerning the 3rd Embodiment of this invention. It is a circuit diagram of a pixel, a readout circuit, and a common output circuit of a solid-state imaging device according to a fourth embodiment of the present invention. It is a timing chart of the solid-state imaging device concerning the 4th Embodiment of this invention. It is a timing chart of the solid-state imaging device concerning the 5th Embodiment of this invention. It is the conceptual diagram which described the signal level of the pixel signal of the solid-state imaging device in connection with the 5th Embodiment of this invention. It is the top view of the solid-state imaging device concerning the 6th Embodiment of this invention, and the conceptual diagram which described the signal level of the read-out pixel signal. It is a timing chart of the solid-state imaging device concerning the 6th Embodiment of this invention. It is the conceptual diagram which described the signal level of the pixel signal of the solid-state imaging device of the solid-state imaging device in connection with the 7th Embodiment of this invention. It is a conceptual diagram showing the reading method of the pixel signal of the solid-state imaging device concerning the 7th Embodiment of this invention. It is the conceptual diagram which showed the relationship between the average value of the signal read in the solid-state imaging device concerning the 7th Embodiment of this invention, and an average value calculation area | region. It is the figure which showed the block diagram of the imaging system using the solid-state imaging device concerning the 7th Embodiment of this invention.

Explanation of symbols

100, 300, 800, 1200, 1800 Pixel portion 101, 700, 801, 1700, 1802 Ineffective pixel area 102, 701, 802, 1002, 1101, 1701, 1801, 2002, 2202, 2303 Effective pixel area 200, 301, 1400 Pixel 201, 1401 Photodiode 202, 1402 Transfer MOS transistor 203, 1403 Amplification MOS transistor 204, 1404 Reset MOS transistor 205, 1405 Selection MOS transistor 206, 1406 Vertical signal line 207, 1407 Constant current source 208, 1408 Clamp capacitance 209, 1409 Clamp switch 210, 1410 Feedback capacitor 211, 222, 1411, 1422 Amplifier 212, 1412 S side transfer switch 213, 1413 N side transfer Switches 214, 1414 S-side signal holding capacitors 215, 1415 N-side signal holding capacitors 216, 1416 S-side horizontal transfer switches 217, 1417 N-side horizontal transfer switches 218, 1418 S-side horizontal output lines 219, 1419 N-side horizontal output lines 220, 1420 S-side horizontal output line reset switch 221, 1421 N-side horizontal output line reset switch 302, 803, 1204, 2304 Vertical scanning circuit 303, 805, 1206, 2306 Horizontal scanning circuit 304, 804, 1205, 2305 Reading circuit 500 D flip-flop 501 AND gates 702 and 1702 Ineffective pixel area pixel signal level (NULL pixel)
703, 1006, 1703, 2004 Pixel signal level 806, 1207, 2307 in the effective pixel area AD converter 807, 1208, 1210, 2308, 2310 Averaging circuit 808, 1209, 1211, 2309, 2311 Memory 809, 1212, 1213, 2312, 2313 Subtracters 1000, 1201, 2000, 2200, 2301 First ineffective pixel regions 1001, 1202, 2001, 2201, 2302 Second ineffective pixel regions 1003, 2003 Pixel signals of the first ineffective pixel region Level (including dark current component)
1004 Pixel signal level of second non-effective pixel area (including dark current component)
1005 Pixel signal level of second non-effective pixel area (dark current component is almost negligible)
1100 Average value calculation area 1101 of the first ineffective pixel area 1101 Average value calculation areas 1214 and 2314 of the second ineffective pixel area Black level adjustment offset values 1215 and 2315 Adder 1423 Vertical signal line reset switch 2005 Second Ineffective pixel area pixel signal level (NULL pixel)
2316 frame memory

Claims (9)

A pixel unit including an effective pixel region of a plurality of pixels that accumulates charges generated according to incident light and outputs a signal, and an ineffective pixel region of a plurality of pixels that outputs a signal independent of incident light;
A plurality of vertical signal lines provided for each column of pixels of the pixel portion;
A vertical scanning circuit that outputs signals of the selected pixels in the same row to the plurality of vertical signal lines by scanning and selecting pixels of the pixel unit in units of rows;
A horizontal scanning circuit for outputting a signal of the selected vertical signal line by scanning and selecting a signal of the plurality of vertical signal lines;
The vertical scanning circuit selects pixels in the same row in the effective pixel area once in a frame during one frame, and selects pixels in the same row in the ineffective pixel area a plurality of times in one frame during one frame. selected,
And a correction circuit that corrects a signal of the pixel in the effective pixel region using a signal of the pixel selected a plurality of times and output by the horizontal scanning circuit,
The non-effective pixel region has a first non-effective pixel region and a second non-effective pixel region in different rows,
The vertical scanning circuit selects pixels in the same row of the second ineffective pixel region a plurality of times in units of one frame during one frame,
The correction circuit averages the signals of the pixels selected for the first time in the first and second ineffective pixel regions, and corrects the signals of the pixels in the effective pixel region, and the second correction circuit. And a second correction circuit that corrects the signal of the pixel in the effective pixel region by averaging the signal of the pixel selected after the second time of the non-effective pixel region,
The first correction circuit averages the pixels of the first and second ineffective pixel regions for each of a plurality of regions divided in the horizontal direction,
The second correction circuit averages the signals of the pixels in the second ineffective pixel area for each of a plurality of areas divided in the horizontal direction by a larger number of divisions than the first correction circuit. An imaging device.   The vertical scanning circuit selects the first row of the non-effective pixel region again after selecting the last row of the non-effective pixel region, and sequentially scans the rows of the non-effective pixel region to thereby detect the non-effective pixel region. The imaging apparatus according to claim 1, wherein scanning is repeated.   3. The vertical scanning circuit repeatedly scans the ineffective pixel area during a period from the completion of scanning of the effective pixel area of the Nth frame to the start of scanning of the effective pixel area of the (N + 1) th frame. Imaging device.   The imaging apparatus according to claim 1, further comprising a switch that is provided for each of the vertical signal lines and connects the vertical signal line to a reference voltage.   The semiconductor impurity region for accumulating charges is formed in the pixels of the effective pixel region, and the semiconductor impurity region for accumulating charges is not formed in the pixels of the ineffective pixel region. Item 5. The imaging device according to any one of Items 1 to 4. The imaging device according to claim 1, wherein the correction circuit averages the signals of the pixels selected a plurality of times and corrects the signals of the pixels in the effective pixel region. The imaging apparatus according to claim 1, wherein the second correction circuit averages the signal of the pixel for each column. The imaging apparatus according to claim 1, further comprising an addition circuit that adds an offset to a pixel signal corrected by the correction circuit. A pixel unit including an effective pixel region of a plurality of pixels that accumulates charges generated according to incident light and outputs a signal, and an ineffective pixel region of a plurality of pixels that outputs a signal independent of incident light;
A plurality of vertical signal lines provided for each column of pixels of the pixel portion;
A vertical scanning circuit that outputs signals of the selected pixels in the same row to the plurality of vertical signal lines by scanning and selecting pixels of the pixel unit in units of rows;
A processing method of an imaging apparatus having a horizontal scanning circuit that outputs a signal of the selected vertical signal line by scanning and selecting signals of the plurality of vertical signal lines,
The vertical scanning circuit selects pixels in the same row in the effective pixel area once in a frame during one frame, and selects pixels in the same row in the ineffective pixel area a plurality of times in one frame during one frame. A step to choose ;
A correction circuit, a correction step of correcting the pixel signal of the effective pixel region using the pixel signal selected a plurality of times and output by the horizontal scanning circuit,
The non-effective pixel region has a first non-effective pixel region and a second non-effective pixel region in different rows,
The vertical scanning circuit includes a step of selecting pixels in the same row of the second ineffective pixel region a plurality of times in units of one frame during one frame,
The correction step includes a first correction step of correcting the signal of the pixel in the effective pixel region by averaging the signal of the pixel selected first in the first and second ineffective pixel regions, and the second correction step. And a second correction step of correcting the signal of the pixel in the effective pixel region by averaging the signal of the pixel selected after the second time of the non-effective pixel region,
In the first correction step, the pixels of the first and second ineffective pixel regions are averaged for each of a plurality of regions divided in the horizontal direction,
In the second correction step, the pixel signal of the second ineffective pixel region is averaged for each of a plurality of regions divided in the horizontal direction by a larger number of divisions than the first correction circuit. Processing method for imaging apparatus.

Images