JP5136317B2 - Power supply - Google Patents

Description

  The present invention relates to a power supply device that rectifies an alternating current and generates a stable DC voltage, and more particularly to a power supply device having a PFC control circuit.

  A power supply device having a PFC (Power Factor Correction) control IC can suppress the generation of harmonics by improving the power factor. As such a power supply device, a power supply device described in Patent Document 1 below is known.

Japanese Patent Laid-Open No. 11-164548

  The power supply device described in Patent Document 1 has an excessive current flowing in the capacitor when the input voltage suddenly rises at the time of start-up or recovery after a momentary power interruption (instantaneous AC power supply stop), The object is to prevent the switching element from being destroyed by an excessive current. In Patent Document 1, a current is passed through a detection resistor, and a detected voltage is compared with a reference value. When an excessive current is detected, output of a drive pulse to a switching element is stopped.

  Further, Patent Document 2 below describes increasing the switching frequency of a switching element for the purpose of dispersing noise components as a PFC control circuit.

US Pat. No. 7,1969,17

  Two types of PFC control methods are known: a critical mode and a continuous current mode (hereinafter referred to as continuous mode). An example of a power supply device having a conventional critical mode PFC control circuit will be described with reference to FIG. As shown in FIG. 1, the bridge rectifier circuit BD rectifies the AC voltage of the AC power supply (commercial power supply) Vac and supplies the full-wave rectified voltage to the smoothing capacitor Ci. An input (DC) voltage Vin is output across the smoothing capacitor Ci.

  One output terminal (non-grounded side) of the bridge rectifier circuit BD is connected to one end of the choke coil L1, and the other end of the choke coil L1 is connected to one output terminal via the diode D1. A drain of a FET (Field Effect Transistor) Q1 as a switching element is connected between the other end of the choke coil L1 and the diode D1 and the other output terminal. The FET Q1 is, for example, an N channel type FET. The source of the FET Q1 is grounded.

  The detection winding L2 is connected as a secondary winding of the choke coil L1. The detection winding L2 is provided to detect that the current flowing through the choke coil L1 becomes zero. An output signal from the detection winding L2 is supplied to the PFC control circuit 1A. A drive pulse OUT formed by the PFC control circuit 1A is supplied to the gate of the FET Q1.

  The drain of the FET Q1 is connected to one end of the capacitor Co via the diode D1 in the forward direction. The other end of the capacitor Co is grounded. An output voltage Vout is generated across the capacitor Co. An output voltage Vout is applied to a load (not shown).

  A boost converter is configured, and an output voltage Vout higher than the input voltage Vin is formed. The FET Q1 is turned on when the logical value of the drive pulse OUT is low level (hereinafter referred to as L), and turned off when the logical value is high level (hereinafter referred to as H).

  During the period when the FET Q1 is ON, a current flows through the choke coil L1 and the FET Q1. Next, when the FET Q1 is turned off, a current flows through the choke coil L1, the diode D1, and the capacitor Co. The detection winding L2 detects that the current flowing through the choke coil L1 becomes zero, and immediately after this detection, the PFC control circuit 1A outputs a drive pulse OUT that turns on the FET Q1.

  FIG. 2 shows a current waveform flowing through the choke coil L1 in the critical mode. The peak value of the current is a value proportional to the length of the ON period of the FET Q1 and the input voltage Vin, and is a value inversely proportional to the inductance component of the choke coil L1. When the load becomes heavier than the current waveform shown in FIG. 2A, the current waveform shown in FIG. 2B is obtained. That is, as the load increases, the peak value of the current increases and the frequency decreases. In the case of the critical mode, as described above, when the load becomes heavy, the peak value of the current flowing through the choke coil L1 becomes large, and there is a disadvantage that is unsuitable for high power applications.

  Next, the continuous mode will be described with reference to FIG. The PFC control circuit 1B in the continuous mode has a fixed frequency oscillator and generates a fixed frequency drive pulse OUT. A drive pulse OUT is supplied to the gate of the FET Q1. Similar to the critical mode, the current peak value is proportional to the length of the ON period of the FET Q1 and the input voltage Vin, and inversely proportional to the inductance component of the choke coil L1. In the continuous mode, the length of the ON period is a fixed value determined by the output frequency of the oscillator.

  In the continuous mode, the FET Q1 performs a switching operation with a drive pulse OUT having a fixed frequency, so that the current flowing through the choke coil L1 does not become zero as shown in FIG. FIG. 4B shows a current waveform when the load becomes heavy with respect to the current waveform of FIG. 4A. When the load becomes heavy, the peak value of the current waveform does not change, and the average value (DC component) increases. Such a continuous mode is suitable for high power applications as compared to the critical mode.

  Unlike the critical mode, the continuous mode has a problem that loss and switching noise occur because the FET Q1 performs a switching operation in a state where a current flows. The loss will be described with reference to FIGS.

The drain-source voltage of the FET Q1 is denoted as V _DS, and the drain current flowing from the drain to the source of the FET Q1 is denoted as I _D. FIG. 5A shows waveforms of voltage V _DS and current _ID . FIG. 5B shows an enlarged waveform of a portion surrounded by a broken line where the FET Q1 is turned ON, and FIG. 5C shows an enlarged waveform of a portion surrounded by a broken line where the FET Q1 is turned OFF.

In the state where the voltage V _DS is applied to the FET Q1, switching loss occurs in the section where the current I _D flows. In FIG. 5B, a switching loss (ON time) occurs when the hatched ON (transition interval from OFF to ON) occurs, and in FIG. 5C, the switching loss occurs when the hatched OFF (transition interval from ON to OFF). Will occur. When transitioning from OFF to ON, a whisker-like current is generated due to the parasitic capacitance of the choke coil L1.

  In the continuous mode, the current for each pulse can be reduced by increasing the switching frequency, the demand for the DC superimposition characteristics of the choke coil becomes gradual, and the choke coil L1 can be downsized. However, when the frequency is increased, the switching loss increases and the burden on the FET Q1 of the switching element increases.

Regarding the loss in the continuous mode, the change when the frequency of the drive pulse OUT changes will be described with reference to FIG. 6A, 6B, and 6C show waveforms of the voltage V _DS and the current _ID when the frequency of the drive pulse OUT is, for example, 100 kHz. 6D and 6
E and FIG. 6F show waveforms of the voltage V _DS and the current _ID when the frequency of the drive pulse OUT is, for example, 130 kHz.

Increasing the frequency of the drive pulse OUT can reduce the current _ID as can be seen by comparing the waveform diagrams of FIGS. 6B and 6E. As a result, the loss at the time of OFF can be further reduced. However, as can be seen by comparing the waveform diagrams of FIG. 6C and FIG. 6F, when the frequency is increased, the current I _D at the ON time increases and the loss at the ON time increases.

  Comparing the decrease in loss at OFF and the increase in loss at ON, the decrease in loss at OFF is more. Therefore, the switching loss can be reduced in the section of one ON time and OFF time. However, if the frequency of the drive pulse OUT is high, the number of times of switching increases within the same time width. As a result, there is a problem that the total loss increases. Therefore, as described in Patent Document 2, for example, there is a problem that switching loss increases when the frequency of the drive pulse OUT is increased in the continuous mode.

  Thus, increasing the frequency can reduce the size of the choke coil, but increases the loss. On the other hand, if the frequency is low, a choke coil having good DC superposition characteristics, that is, a large coil is required.

  Accordingly, an object of the present invention is to provide a power supply apparatus that can solve the above problems, use a small choke coil, and reduce loss.

In order to solve the above-described problem, the present invention includes first and second input terminals to which an input voltage is supplied,
First and second output terminals from which output voltages are derived;
A choke coil having one end connected to the first input terminal and the other end connected to the first output terminal via a diode;
A switching element connected between the other end of the choke coil and the connection point of the diode and the second output terminal;
A capacitor connected between the connection point of the diode and the first output terminal and the second output terminal;
A comparator that compares the current that flows when the switching element is turned on with a preset threshold value;
In order to stabilize the output voltage of the oscillator, the pulse width modulation circuit for controlling the duty ratio of the pulse signal formed from the output signal of the oscillator, and the output signal from the pulse width modulation circuit are supplied, A frequency switching circuit for switching the frequency of the output signal by the comparison signal, and a PFC control circuit for outputting a pulse signal for turning on / off the switching element from the frequency switching circuit,
The frequency switching circuit is a power supply device that switches the frequency of the pulse signal to a higher frequency when the current that flows when the switching element is turned on is greater than or greater than the threshold.

Preferably, the switching element is a FET,
The comparison unit converts the drain current of the FET into a detection voltage using a resistor, compares the detection voltage with a threshold voltage, and outputs a comparison signal.

Preferably, the oscillation frequency of the oscillator is fixed,
One of the output signal of the oscillator and the divided output obtained by dividing the output signal of the oscillator is selected by the selection circuit,
The divided output is selected by the selection circuit except when the current flowing when the switching element is turned on is larger than the threshold value or more than the threshold value.

Preferably, the pulse width modulation circuit forms an output signal that is pulse width modulated in accordance with a signal corresponding to the output voltage .

  Further, the input voltage is compared with a preset threshold value, and when the input voltage is lower than the threshold value or lower than the threshold value, the frequency of the pulse signal is switched to a higher frequency.

  According to the present invention, since the switching frequency is increased only when the load is heavy, it is possible to prevent the choke coil from becoming large and to prevent the switching loss from increasing.

  An embodiment of the present invention will be described below with reference to the drawings. This embodiment is applied to a power supply apparatus having a continuous mode PFC control circuit shown in FIG.

  As shown in FIG. 7, the bridge rectifier circuit BD and the smoothing capacitor Ci rectify the AC voltage of the AC power supply (commercial power supply) Vac and supply the full-wave rectified voltage to the smoothing capacitor Ci. An input (DC) voltage Vin is output to both ends (first and second input terminals) of the smoothing capacitor Ci.

  One output terminal (non-grounded first input terminal) of the bridge rectifier circuit BD is connected to one end of the choke coil L1, and the other end of the choke coil L1 is connected to the first output terminal via the diode D1. The The drain of the FET Q1 as a switching element is connected between the other end of the choke coil L1 and the diode D1 and the second output terminal. The FET Q1 is, for example, an N channel FET. The source of the FET Q1 is grounded. A parasitic diode (not shown) exists between the drain and source of the FET Q1. A drive pulse OUT formed by the PFC control circuit 1C is supplied to the gate of the FET Q1.

  The drain of the FET Q1 is connected to one end of the capacitor Co via the diode D1 in the forward direction. The other end of the capacitor Co is grounded. An output voltage Vout is generated at both ends (first and second output terminals) of the capacitor Co. An output voltage Vout is applied to a load (not shown).

  A boost converter is configured, and an output voltage Vout higher than the input voltage Vin is formed. The drive pulse OUT is supplied to the FET Q1 as the switching element from the drive circuit 13 of the PFC control circuit 1C. The FET Q1 is turned ON when the logical value of the drive pulse OUT is L and turned OFF when the logical value is H.

  During the period when the FET Q1 is ON, a current flows through the choke coil L1 and the FET Q1. The peak value of the current flowing during the period when the FET Q1 is ON is a value proportional to the length of the ON period of the FET Q1 and the input voltage Vin, and is a value inversely proportional to the inductance component of the choke coil L1. Next, when the FET Q1 is turned off, a current flows through the choke coil L1, the diode D1, and the capacitor Co.

  The PFC control circuit 1 </ b> C includes an oscillator 11, a pulse width modulation (PWM) circuit 12, and a drive circuit 13. Although a protection circuit against overcurrent is provided in the PFC control circuit 1C, it is omitted for simplicity.

  The oscillator 11 generates an output signal of a sawtooth wave or a triangular wave (hereinafter referred to as a sawtooth wave unless otherwise distinguished), and the output signal of the oscillator 11 and the control signal FB are supplied to the PWM modulation circuit 12. The control signal FB is a signal having a voltage value corresponding to, for example, output voltage fluctuation. The PWM modulation circuit 12 modulates the pulse width of the output signal according to the control signal FB. The output pulse of the PWM modulation circuit 12 is supplied to the gate of the FET Q1 through the drive circuit 13. The PFC control circuit 1C stabilizes the output voltage Vout by changing the duty ratio of the drive pulse.

  As shown in FIG. 8, the oscillator 11 is configured to alternately perform the operation of charging the capacitor 21 with the constant current source 22a and the operation of discharging with the constant current source 22b by turning on / off the switching element 23. . The terminal voltage of the capacitor 21 is supplied to the output signal of the oscillator 11 and the PWM modulation circuit 12. A control signal FB is supplied to the PWM modulation circuit 12, and an output pulse whose duty ratio is controlled according to the control signal FB is generated.

  As shown in FIG. 9, in the oscillator 11, the charging constant current source 22 a is configured by a current mirror circuit including FETs 24 a and 24 b and a resistor 25. A portion surrounded by a broken line is an IC (Integrated Circuit) configuration, and a capacitor 21 and a resistor 25 are formed outside the IC.

  As shown in FIG. 10A, the sawtooth wave output from the oscillator 11 is compared with the control signal FB. In a section where the value of the sawtooth wave from the control signal FB is large, it becomes H as shown in FIG. 10B, and in a section where the value of the sawtooth wave from the control signal FB is small, it becomes L as shown in FIG. 10B. A PWM signal is formed. When the load increases, the control signal FB value decreases, the duty of the PWM signal increases, and control is performed such that the ON period of the FET Q1 is longer.

  An embodiment of the present invention will be described with reference to FIG. A sawtooth wave from the oscillator 11 is supplied to one input terminal of the voltage comparator 31. A control signal FB represented as a variable voltage source is supplied to the other input terminal of the voltage comparator 31. The control signal FB is, for example, a signal obtained by dividing the output voltage with a resistor. As described above, a PWM-modulated pulse signal is output to the output of the voltage comparator 31. The voltage comparator 31 constitutes the PWM modulation circuit 12.

  The PWM signal from the voltage comparator 31 is supplied to the counter 32 and the input terminal b of the switch circuit SW. The counter 32 divides the frequency of the PWM signal. The output signal of the counter 32 is supplied to the input terminal a of the switch circuit SW. The pulse signal extracted to the output terminal c of the switch circuit SW is input to the flip-flop 33. The output signal of the flip-flop 33 is supplied to the gate of the FET Q1 through the inverter 34.

The switch circuit SW is a frequency switching circuit and is controlled by a switching signal Pd obtained at the output of the voltage comparator 35. A current that flows when the FET Q1 as the switching element is turned on is detected. For example, a detection resistor Rs is inserted between the source of the FET Q1 and the ground. A detection voltage Vs is taken out from a connection point between the source and the detection resistor Rs. The detection voltage Vs has a value proportional to the current _ID that flows when the FET Q1 is ON. It is also possible to use the control signal FB as a detection voltage. Furthermore, the load current may be converted into a detection voltage by a resistor.

  The detection voltage Vs is supplied to one input terminal of the voltage comparator 35. A threshold voltage Vth is supplied to the other input terminal of the voltage comparator 35. When the detection voltage Vs is greater than or equal to the threshold voltage Vth (hereinafter referred to simply as “large” if no distinction is required), an H switching signal Pd that is one of the logical values is output. Is done. When the detection voltage Vs is equal to or lower than the threshold voltage Vth (hereinafter, when it is not particularly necessary to distinguish, it is simply described as follows), the L switching signal Pd that is the other logical value is output. The The voltage comparator 35 constitutes a comparator that compares the current that flows when the FET Q1 is turned on with a preset threshold value.

The switch circuit SW selects the input terminal a while the detection signal Pd is L, and outputs the output signal of the counter 32 to the output terminal c. While the detection signal Pd is H, the input terminal b is selected, and a pulse signal that does not pass through the counter 32 (output signal of the voltage comparator 31) is output to the output terminal c. The detection signal Pd becomes H only when the current _ID flowing through the FET Q1 is larger than the current corresponding to the threshold voltage Vth.

  The PWM signal shown in FIG. 12C is formed from the output signal of the oscillator 11 shown in FIG. 12A and the control signal FB. When the input terminal b of the switch circuit SW is selected, the pulse signal shown in FIG. 12C is supplied to the flip-flop 33.

  The counter 32 generates one output at the timing of counting two inputs indicated by T2 and T4 in FIG. 12A, and the flip-flop 33 is set or reset by the output of the counter 32. For example, the flip-flop 33 is set at the timing T2, and the flip-flop 33 is reset at the timing T4.

The pulse signal in FIG. 12B has a frequency that is three times the frequency of the pulse signal in FIG. 12C. Therefore, when the drain current _{ID of the} FET Q1 becomes larger than a preset threshold value, the frequency of the drive pulse is tripled. When the drain current _{ID of the} FET Q1 is not more than a preset threshold value, a lower frequency drive pulse (FIG. 12B) is formed.

  In the example described above, the counter 32 generates one output as a result of the count operation twice. The counter 32 may generate two outputs as a result of three count operations. In this case, the frequency of the drive pulse is 1.67 times. Further, when the counter 32 performs 1/2 frequency division, the frequency of the drive pulse can be doubled. Furthermore, the frequency dividing ratio of the counter 32 may be variably set by a user adjustment operation without being fixed.

In the embodiment of the present invention described above, when the load is light, current _ID does not exceed threshold current Ith as shown in FIG. 13A. The threshold current Ith is a current corresponding to the threshold voltage Vth. As shown in FIG. 13B showing the waveform of the current I _{D in} an enlarged manner, the period is tx corresponding to the oscillation frequency of the oscillator 11.

On the other hand, when the load is heavy, as shown in FIG. 14A, a period in which the current _ID exceeds the threshold current Ith occurs. In a period in which the current I _D does not exceed the threshold current Ith, as shown in FIG. 14B, a current I _D whose peak value is Ipp1 flows between the drain and source of the FET Q1 in the period tx. In the period in which the current _ID is equal to or higher than the threshold current Ith, the frequency of the drive pulse is increased as described above. That is, as shown in FIG. 14C, the current I _D for its peak value at a period ty (<tx) is Ipp2 (<Ipp1) flows between the drain and source of the FET Q1.

Thus, since the peak value of the current _ID when the load is heavy can be lowered, the demand for the DC superimposition characteristics of the choke coil can be moderated, and a small choke coil can be used. Furthermore, it is possible to reduce the loss at the OFF time when the choke coil FETQ1 transitions from the ON state to the OFF state. The loss at the ON time when the FET Q1 changes from the OFF state to the ON state increases. However, since the amount of decrease in loss at OFF is larger than the amount of increase in loss at ON, the increase in loss can be suppressed in total. In one embodiment of the present invention, the switching frequency is increased only during a part of the period when the current _ID is equal to or higher than the set value. Therefore, unlike the case where the switching frequency is always increased, the total switching loss is increased. Can be prevented.

  As mentioned above, although embodiment of this invention was described concretely, this invention is not limited to the above-mentioned embodiment, The various deformation | transformation based on the technical idea of this invention is possible. For example, in the above description, the switching frequency is increased when the load becomes heavy. Further, when the input voltage decreases, the switching frequency may be increased. In this case, the input voltage is compared with a preset threshold value, and when the input voltage becomes smaller than the threshold value, the switching frequency is switched to a higher one.

  Not only the frequency of the drive pulse OUT is changed by the counter, but the oscillator is configured as a variable frequency oscillator, and the oscillation frequency is increased when it is detected that the current flowing through the switching element exceeds the threshold value. You may do it.

It is a connection diagram showing an example of a conventional critical mode PFC control circuit. It is a wave form diagram for demonstrating operation | movement of the PFC control circuit of a critical mode. It is a connection diagram showing an example of a conventional continuous mode PFC control circuit. It is a wave form diagram for demonstrating operation | movement of the PFC control circuit of a continuous mode. FIG. 4 is a waveform diagram in which a part of FIG. 3 is enlarged. It is a wave form diagram for demonstrating the switching loss of the conventional PFC control circuit. It is a wave form chart for explaining switching loss at the time of making frequency high. It is a connection diagram of a power supply device having a PFC control circuit to which the present invention can be applied. It is a connection diagram which shows the structure of an example of an oscillator. It is a connection diagram which shows the more concrete structure of an oscillator. It is a wave form diagram used for description of PWM modulation. It is a connection diagram of a PFC control circuit according to an embodiment of the present invention. It is a wave form diagram for description of operation | movement of one Embodiment of this invention. It is a wave form diagram for description of operation | movement of one Embodiment of this invention. It is a wave form diagram for description of operation | movement of one Embodiment of this invention.

Explanation of symbols

Q1 ... FET
BD: Bridge rectifier circuit L1 ... Choke coil Rs ... Current detection resistor SW ... Switch circuit 1C, 1B, 1C ... PFC control circuit 11 ... Oscillator 12 ... PWM modulation circuit 31 35 ... Voltage comparator 32 ... Counter

Claims (5)

First and second input terminals to which an input voltage is supplied;
First and second output terminals from which output voltages are derived;
A choke coil having one end connected to the first input terminal and the other end connected to the first output terminal via a diode;
A switching element connected between the other end of the choke coil and the connection point of the diode and the second output terminal;
A capacitor connected between a connection point of the diode and the first output terminal and the second output terminal;
A comparator that compares the current that flows when the switching element is turned on with a preset threshold;
In order to stabilize the output voltage of the oscillator, a pulse width modulation circuit for controlling a duty ratio of a pulse signal formed from the output signal of the oscillator, and an output signal from the pulse width modulation circuit are supplied, and the comparison A frequency switching circuit for switching the frequency of the output signal by a comparison signal from the unit, and a PFC control circuit for outputting a pulse signal for turning on / off the switching element from the frequency switching circuit,
The frequency switching circuit is a power supply device that switches the frequency of the pulse signal to a higher frequency when a current that flows when the switching element is turned on is greater than or greater than the threshold value. The switching element is an FET;
2. The power supply device according to claim 1, wherein the comparison unit converts a drain current of the FET into a detection voltage by a resistor, compares the detection voltage with a threshold voltage, and outputs the comparison signal. The oscillation frequency of the oscillator is fixed,
One of the output signal of the oscillator and the divided output obtained by dividing the output signal of the oscillator is selected by a selection circuit,
2. The power supply device according to claim 1, wherein the divided output is selected by the selection circuit except when a current flowing when the switching element is turned on is larger than the threshold value or more than the threshold value. 2. The power supply apparatus according to claim 1, wherein the pulse width modulation circuit forms an output signal that is pulse width modulated in accordance with a signal corresponding to the output voltage.   Furthermore, the input voltage is compared with a preset threshold value, and the frequency of the pulse signal is switched to a higher frequency when the input voltage is lower than the threshold value or lower than the threshold value. The power supply device according to 1.

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