JP4637123B2 - Data processing method and data processing unit, method for dynamic reconfiguration of configurable elements, system and process - Google Patents

Abstract

The dynamic reconfiguration method uses one or more switching tables. These comprise one or more controls and one or more configuration memories and exist on or are connected to the module. Configuration words are transmitted from a switching table to a configurable element or several configurable elements of the modules, which set a desired configuration. The positioning logic or the configurable elements can write data into the configuration memory of the switching table(s). The table controls identify individual inputs as commands and can carry out these commands. The controls recognise different events and can differentiate between them and carry out a specified action. In response to an event or combination of events the controls move a position indicator. When the data is configuration data and not a control command the data is sent to the configurable elements. The control can transmit one or more messages to the logic which recognises and analyses the signals. The logic transmits data to the configuration memory of the switching table(s).

Description

  The present invention relates to a data processing method and data processing unit for a configurable element, a dynamic reconfiguration method, a system and a process for a configurable element.

  The present invention relates to a data processing method and a data processing unit.

[Conventional technology]
The programmable modules used today (DFP = Datenflussprozessoren, FPGA = Field Programmable Gate Arrays) can be programmed in two different forms:
1. Only once, ie after programming, the configuration can no longer be changed. Thus, all configured elements of the module perform the same function throughout the time interval being used.
2. In operation, that is, the configuration can be changed at the start of use by loading the configuration file after module installation. Most modules (especially FPGA modules) are not reconfigured any further during operation. For reconfigurable modules, subsequent processing of data during the reconfiguration period is usually not possible and the time required is significantly too large.

  Programmable modules are loaded with module configuration data by a hardware interface. This process is slow and often requires hundreds of milliseconds based on the limited bandwidth for the external memory where the configuration data is filed. The programmable module will then be used in the desired / programmed function as described in the configuration file. Configuration occurs by entering a unique bit pattern of arbitrary length into the configurable element of the module. The configurable elements can be, for example, all kinds of RAM cells, multiplexers, elements for the network or ALU (= Arithmetic Logic Unit). Since the configuration word is stored in such an element, the element maintains its configuration adjusted by the configuration word for the duration of operation.

There are a series of problems with existing methods and techniques. These are as follows:
1. Module to program the entire configuration file even if only a very small part of the configuration should be changed when trying to change the configuration in DFT (see German Patent Application Publication No. 4416881) or FPGA It is always necessary to transmit to.
2. During the loading of the new configuration, the module is still unable to process the data or, if possible, very limited.
3. As the number of configurable elements per module grows (especially in FPGA modules), the configuration files for these modules grow as well (during this time, hundreds of kilobytes of data) . Therefore, configuring a large module takes a very long time and for this reason reconfiguration during runtime is often not possible or hinders the operation of the module.
4). Whenever a module is partially configured at run time, a central logic entity is used. All reconfigurations are managed through this entity. This results in very high communication and synchronization costs.

  With the present invention, reconfigurable programmable modules can be made significantly faster. The present invention allows for a flexible use at run time of a wide variety of configurations of programmable modules, in which case the operational capabilities of the programmable modules are not disturbed or stopped. Absent. Module configuration changes are performed simultaneously, and in some circumstances can therefore be performed very quickly without the need to transmit separate configuration data. This method is intended for all types of configurable elements of configurable modules, as well as for all types of configuration data, for what purpose they are defined within the module. Can be used regardless of The present invention can eliminate the static limitations of conventional modules and achieve improved utilization of existing configurable elements. By introducing a temporary memory, a number of different functions can be implemented via the same data. Details and special embodiments, as well as features of the inventive bus system, are the subject of the dependent claims.

  There are many ring memories in the programmable module. It is a memory having its own address control unit. This address control unit. This creates a ring when it reaches the end of memory, since it operates further at the beginning. The ring memory can access a configuration register, that is, a circuit that receives configuration data of an element to be configured while writing and reading. This type of ring memory has a predetermined number of entries, which are loaded with configuration data by load logic, as described in German Offenlegungsschrift 4,416,881. In this case, the configuration of the entry is selected so that the data format corresponds to the configurable element or elements connected to the ring memory and an effective configuration adjustment setting is realized.

  In addition, there is a read position pointer. One of the ring memory entries is selected as an actual read entry. The read position pointer can be moved by control over any position / entry in the ring memory. In addition, there is a write position pointer. One of the ring memory entries is selected as an actual write entry. The write position pointer can be moved by control over any position / entry in the ring memory.

  At run time, configuration words can be transmitted through this ring memory to the element to be configured, and reconfiguration can be performed without having to manage or transmit data by central logic. By using multiple ring memories, a number of configurable elements can be reconfigured simultaneously.

  This is referred to as a switching table because the ring memory can be switched between multiple configuration modes with full control of the configurable cells.

  There are a large number of ring memories external to the programmable module or connected to this module. Corresponding to one or a plurality of ring memories, one or a plurality of control units for controlling these ring memories are provided. These control units are part of the load logic described in German Patent Application Publication No. 4416881. The ring memory contains configuration words for the elements to be configured of one or many configurable modules, where the configurable elements are clearly for networking of functional groups. And a crossbar circuit or multiplexer for interconnecting bus structures, which is also used in the prior art.

  The ring memory and the ring memory controller can be implemented directly in hardware, or can perform one or more configurations of modules that can be configured (eg, FPGAs). It can also be caused gradually by cell configuration.

A conventional ring memory can be used as the ring memory. In particular, a ring memory and / or control unit having the following characteristics can be used:
1. In this characteristic, all entries are not utilized and the ability to indicate the position at which the ring memory read and / or write position pointer is set at the beginning or end of the ring memory. This is realized by, for example, a counter or register that stores an instruction word (STOP, GOTO, etc.), a start position, and a stop position.
2. Allows separation of independent sections of the ring memory and the control of the ring memory can be tuned so that it operates in one of these sections, for example via an event described later Characteristic.
3. There are properties that allow the ring memory to be detached in independent sections and a number of controls each operating in one section. In this case, a plurality of control units can operate in the same section. This can be realized by an arbiter circuit. In this case, some processing cycles are lost. Furthermore, a register can be used in place of the RAM.
4). Each control unit has one or more read position pointers and / or one or more write position pointers.
5. These position pointers can move forward and / or backward.
6). These position pointers can start based on one or more events, set to an end or specified position.
7). The controller has a mask register which can be used to select a partial quantity from a large number of all possible events by data word entry. Only these partial amounts of events are transferred as events to the controller and trigger the advancement of one or more position pointers.
8). A control unit that operates with a clock several times the original system clock (oversampling) to enable processing of a plurality of entries in the system clock.

The control of the switching table is implemented by a conventional state machine. In addition to the simple control that requires one conventional ring memory, the switching modules described in the present invention for programmable modules (in particular, FPGAs and DPGAs (dynamically programmable gate arrays, a new subgroup of FPGAs)). In order to implement or possibly extend the control of the table, most conveniently a controller with the following characteristics is suitable:
1. A control unit that can identify specific command words. The command word is different from the others by having a sign. That is, this indicator allows the control unit to identify the data of the ring memory entry as an instruction word, not as a data word.
2. A control unit that can execute specific command words. In particular, instructions which change the state machine sequence and / or the ring memory entries can be changed by a data processing function.
3. A control unit that can identify an identification word and processes other entries of the ring memory by an internal faster (oversampling) clock based on the identification word. This is done until the end identifier is reached or until the next clock cycle of the clock that controls the oversampling clock.

  As the instruction word for meaningful control of the switching table that requires control using the instruction word, the following instructions or a part of these instructions can be considered. The instruction word for the position pointer can be applied to one or more read position pointers in each case, or can be applied to one or more write position pointers.

Possible command words:
1. WAIT instruction.
The WAIT instruction causes the control unit to wait until the next event or the next (or different) event arrives. During this state, one or more read / write position pointers are not sent first. When one or more events arrive, the read / write position pointer or pointers are positioned at the next entry.

2. SKIP instruction.
The SKIP instruction skips a specified number of entries in the ring memory in one of two ways:
a. The SKIP1 instructions are all executed in one processing cycle. For example, when SKIP5 is specified, it jumps to the entry located five entries before (after) from the current read / write entry in one processing cycle.
b. The SKIP2 instruction is implemented gradually after a certain number of processing cycles. Here, for example, it is conceivable that the instruction SKIP5 is gradually executed after five processing cycles. At this time, again, five entries are jumped forward from the entry at that time. That is, the parameter (5 in this example) is used twice in this method.
The specification of the interlace direction can be terminated in either the forward or backward direction of the position pointer or pointers by using a number with polarity.

3. SWAP instruction.
The SWAP instruction exchanges data of two specified entries with each other.

4). RESET instruction.
The RESET instruction sets one or more read / write position pointers to the beginning and / or specified entry position in the ring memory.

5. WAIT-GOTO instruction.
The WAIT-GOTO instruction, like the WAIT instruction described above, waits for one or more events and then positions the read / write position pointer to a defined starting state within one or more processing cycles. carry out.

6). NOP instruction.
The NOP instruction performs no operation. Data from the ring memory is not transmitted to the element to be configured and the position pointer is not changed. Thus, although the NOP instruction characterizes the entry as unimportant, this entry is answered and evaluated by the ring memory controller, which is necessary as one or more processing cycles.

7). GOTO instruction.
The GOTO instruction positions one or more read / write position pointers at a specified entry position.

8). MASK instruction.
The MASK instruction writes a new data word to the multiplexer, which selects different events. Therefore, this command can be used to change the event to which the control unit responds.

9. LIBACK instruction.
The LIBACK instruction generates a response to the load logic (in the meaning of German Offenlegungsschrift 4,416,881). This instruction allows the switching table to unload a relatively large area of the module. But especially unloading itself.

10. Instruction that triggers a read / modify / write cycle This instruction performs the reading of an instruction or data in another entry, for example, by a controller, load logic or an element external to the switching table. These data are then processed in any manner and again written to the same location or another location in the ring memory of the switching table. This can be done in the time interval of the processing cycle of the switching table. In that case, the process ends before the next new positioning of the position pointer.

The structure of the ring memory entry has the following format:

  The first bit characterizes the entry as an instruction or data word. The control unit of the switching table determines whether the bit chain in the data portion of the entry is treated as an instruction or configuration data.

  The second bit characterizes whether control should be continued by the next entry or the next event should be waited for, even if no other event arrives immediately. If oversampling is used and the RUN bit is set, the next entry is processed using this oversampling clock. This is done until the number of entries is reached without the RUN bit set or until the number of entries that can be processed into the system clock at the oversampling clock rate is reached. If the oversampling method is not used, the advance is done with the normal system clock and the RUN bit set. Events coming in during the sequence of instruction sequences characterized by the RUN bit are evaluated and a trigger signal is stored in the flip-flop. The control unit evaluates this flip-flop again when it reaches an entry without the RUN bit set.

  The rest of the entry contains all the necessary information depending on the type (data or instruction), so that the control unit can perform the task completely.

  The size of the ring memory can be embodied depending on the application, in particular this is the case for a programmable module in which the ring memory results from the configuration of one or more configurable cells. apply.

  At that time, the ring memory includes an element to be configured or a group of elements to be configured, an element to be configured by the selected configuration word (in the ring memory), or an element to be configured. Are connected to be entered in the configuration register of the group.

  This results in an effective and working configuration of the element to be configured or the group of elements to be configured.

  Each ring memory has one control unit or a plurality of control units, which control the positioning of the read position pointer and / or the write position pointer.

  The control unit uses a response channel as described in German Offenlegungsschrift 4 416 881 and by external events transmitted to or within another element of the module (eg interrupt, IO protocol, etc.) In response to these internal or external events, the read position pointer and / or the write position pointer are moved to another entry.

For example, the following events are possible:
1. A computing device clock cycle.
2. Internal or external interrupt signal.
3. Trigger signal for another element in the module.
4). Comparison of data flow and / or instruction flow with a value.
5. Input / output event.
6). Counter operation, overflow, new set, etc.
7). Evaluation of comparison.

  If a module has a plurality of ring memories, each ring memory controller can respond to different events.

  Each time the read position pointer moves to a new entry, the configuration word contained in this entry is transmitted to one configurable element or multiple configurable elements connected to the ring memory. Is done.

  This transmission is performed in such a way that the operation method of the module part, which is not related to the reconfiguration, is not taken into account.

  One or a plurality of ring memories may be in the module, but may be connected to the module from the outside via an external interface.

  In this case, a plurality of independent ring memories per module can be considered. These ring memories can be grouped into a single area of the module, or distributed in an effective manner and distributed across the module face.

  The configuration data is loaded into the memory of the switching table by load logic as is known from German Offenlegungsschrift 4,416,881 or by another internal cell of the module. The configuration data can then be transmitted simultaneously to a plurality of different switching tables by means of load logic or by another internal cell of the module, enabling simultaneous loading of the switching tables.

  The configuration data may then be in the main memory of the data processing device and can be transmitted by known methods such as DMA or processor controlled data transfer instead of load logic.

  After loading of the switching table ring memory by the load logic, the switching table control is set to the start state and adjusts the valid configuration of the entire module or module portion. Therefore, the control unit of the switching table starts new positioning of the read position pointer and / or the write position pointer as a response to the incoming event.

  In order to start loading new data into one switching table or a number of switching tables, the control unit sends a signal to the load logic, in the sense of DE 4416881 or new data Can be returned to another internal part of the module that is loading the switching table into the ring memory. This kind of response triggering can be done by means of a specific instruction evaluation, counter state, or externally (described in the state-back unit of German Patent Application No. 19651075.9) As can be done). The load logic or another internal cell of the module evaluates this signal, responds to this signal with possibly modified program execution, and transmits new or other configuration data to the ring memory or memories. Therefore, in that case, it is only necessary to transmit the data of the ring memory involved in the data transmission based on the signal evaluation. It is no longer necessary to transmit configuration data for the entire module.

Temporary memory One memory can be connected to each configurable element or group of elements (hereinafter referred to as functional elements). A number of methods according to the prior art can be used for the realization of this memory, in particular a FIFO. The data generated by the functional element is stored in memory until the data packet is processed by the same operation to be performed or until the memory is full. The configuration element is then reconfigured via the switching table, i.e. the function of the element changes. At this time, a full flag indicating that the memory is full can be used as a trigger signal for the switching table. In order to be able to arbitrarily determine the amount of data, the position of the full flag can be configured, i.e. the memory can likewise be configured by means of a switching table. Data in the memory is routed to the configuration element and new operations on the data are performed. Data is an operand for new calculations. Only the data from the memory can then be processed, or further data comes from outside (from outside the module or from another functional element). When processing the data, these (the result of the operation) can be transferred to subsequent configuration elements or written back into the memory. In order to allow both write and read access to the memory, the memory can consist of two memory banks, which are processed alternately or separate read and write to the same memory. A write position pointer exists. A special embodiment is the connection of a plurality of the above-mentioned memories. Thereby, in order to file a plurality of results in separate memories and to perform a predetermined function at a predetermined time, a plurality of memory areas are simultaneously led to the input side of one functional element and incorporated into the calculation.

Configuration of Ring Memory Entry Next, a description will be given of a possible configuration of the entry to the ring memory of the switching table used in the data processing apparatus as described in German Patent Application Publication No. 44169991. . The following table describes the instruction structure based on the individual bits of the instruction word:

Thus, if the entry is a data entry, bit number 0 has the value 0, ie the bits from position 2 have the following meaning:

Thus, if the entry is an instruction, bit number 0 has the value 1, that is, the bit from position 2 has the following meaning:

  The following table shows the meaning of bits 2-6 and 8-n for each instruction listed here. The overall bit width of the data word depends on the module of use for which the switching table is used. The bit width should be chosen so that all the data needed for the instruction can be encoded in bits from position 8.

ALU Reconfiguration Further, it is conceivable to use one or more switching tables to control the ALU. The invention is for example an improvement of DE 18651075.9 in which the switching table is connected to the M / F-PLUREG register or the entire M / F-PLUREG register is replaced by the switching table. Can be used.

  Next, the present invention will be described in detail with reference to the embodiments shown in the drawings. FIG. 1 shows the basic structure of a ring memory. It consists of a write position pointer 0101 and a read position pointer 0102. These pointers access the memory 1030. This memory may be realized as a RAM or a register. The RAM address 0104 is selected using the write / read position pointer. Depending on the selected access format, input data can be written to or read from this address.

  FIG. 2 shows the internal structure of a simple ring memory. One counter can be used for each of the write / read position pointers. Reference numeral 0201 represents a counter for the read position pointer 0204, and 0206 represents a counter for the write position pointer 0205. Each of the two counters 0201, 0206 has a global reset input side and an up / down input side that determines the counting direction. A write position pointer (0205) and a read position pointer (0204) for instructing the address of the memory 0203 are switched through a multiplexer 0202 to which an output of a counter is applied on the input side. Write access and read access are implemented via signal 207. For each write access or read access, each counter is incremented by one position. Therefore, the write position pointer (0205) and the read position pointer (0204) indicate the last position in the memory (the last address in the case of a counter that counts up or the first address in the case of a counter that counts down). Then, the write or read position pointers 0205 and 0204 are set to the first position of the memory 0203 at the next access (the first address in the case of the counter counting in the up direction or the last address in the counter counting in the down direction). address). In this way, a ring memory function is generated.

  FIG. 3 shows the expansion of a normal ring memory. In this expanded configuration, the counter 0303 of the write position pointer 0311 and the counter 0309 of the read position pointer 0312 can be loaded with a single value, so that each address of the memory can be directly adjusted and set. This loading process is performed via the counter data and the load input as usual. Further, the work area of the ring memory can be limited to a predetermined section of the internal memory 0306. This is done by internal logic that controls the counter 0303 of the write position pointer 0311 and the counter 0309 of the read position pointer 0312. This logic is structured as follows: the output side of the counter (0303, 0309) is led to the input side of the comparator (0302, 0308) belonging to it. Therefore, the value of each counter is compared with the value of each data register (0301, 0307). The data register stores the jump position, that is, the end of the section of the ring memory. When the two values match, the comparator (0302, 0308) sends a signal to the counter (0303, 0309). The counter then loads the value from the data register (0304, 0310) for the interlaced target address, ie the beginning of the ring memory section. The data register (0301, 0307) for the interlace position and the data register (0304, 0310) for the interlace target address are loaded by load logic (see German Patent Publication No. 4416881). This expansion allows the ring memory not to use the entire area of the internal memory, but to use only selected portions. Further, when a plurality of such write / read position pointers (0311, 0312) are used, the memory can be divided into various sections.

  FIG. 4 shows the configuration of a ring memory distributed to a plurality of sections, in which case the control unit 401 operates in one of these sections. The controller will be described in detail with reference to FIG. In order to be able to divide the ring memory into a plurality of sections, a plurality of write / read position pointers 0402, 0408 whose configuration is shown in FIG. 3 are used. At that time, the control unit selects a region in which the control unit operates through the multiplexer 0407. Write or read access is selected via multiplexer 0403. Accordingly, the address of the memory 0404 is addressed by the selected write / read position pointer.

  FIG. 5 shows an example in which a plurality of control units 0501 operate in a unique area of the ring memory via one write and read position pointers 0506 and 0502 for each control unit. At this time, a write position pointer 0506 and a read position pointer 0502 are assigned to each control unit 0501. Which of the plurality of write and read position pointers 0506 and 0502 accesses the memory 0504 is selected via the multiplexer 0505. Write access or read access is selected via the multiplexer 0503. The write / read signal of the control unit 0501 reaches the memory 0504 via the multiplexer 0507. The control signals of the multiplexers 0507, 0505, 0503 go from the control unit 0501 to the multiplexer via the arbiter 0508. Arbiter 0508 prevents multiple controllers from accessing multiplexers 0507, 0505, 0503 at the same time.

  FIG. 6 shows the connection between the ring memory 0601 and the configuration element 0602. The ring memory 0601 is connected via 0604, 0605, 0606. The address of the cell 0607 in question is transmitted via 0604. Line 0605 transmits configuration data from the ring memory. Cell 0607 transmits a response over line 0606 as to whether reconfiguration is possible. Data filed in the ring memory is entered in configuration element 0602. This configuration element 0602 determines the configuration of the configurable element 0603. The configurable element 0603 can comprise, for example, a logical unit, ALU.

  FIG. 7 shows a control that can respond to different trigger events. Since individual trigger events can then be masked, it is always assumed that there is only one trigger event. This is done by multiplexer 0701. The trigger signal is stored by flip-flop 0704. Multiplexer 0702 (see FIG. 7a), which can also be configured as a mask via an AND gate, is used to allow processing of low active trigger signals and high active trigger signals. The trigger signal stored in the flip-flop is transferred to the clock generation unit via 0705. The clock generator will be described with reference to FIG. The state machine 0703 is supplied with the clock (CLK) from the logic for generating the clock, and depending on the input signal, the output signal and the flip-flop 0704 are reset and reset to stop processing until the next trigger signal. Send a signal (CLR). The advantage of this embodiment is current saving when the clock is interrupted. This is because the state machine 0703 is static in that case. An implementation where the clock is always applied and the state machine is controlled by the state of the instruction decoder and run bit is equally conceivable.

  FIG. 7a shows the masking of the trigger signal. The trigger signal and the A line are connected to the input side of the AND gate 0706. The output side of AND gate 0706 is ORed to 0707 to generate an output signal.

  FIG. 8 shows the logic for clock generation for the state machine. At 0801, another clock is generated using the PLL. It can then be selected via multiplexer 0802 whether the normal chip clock or the PLL0801 clock is used. Signals C and B are applied to the OR gate 0804. The signal C is generated based on a trigger event in the control unit (see 0705 in FIG. 7). Signal B comes from bit 1 of the instruction word (see 1012 in FIG. 10). Since this bit has the function of a run flag, the control unit continues to operate regardless of the trigger pulse when the run flag is set. The output side of OR gate 0804 is rounded by the output of multiplexer 0802 and thus generates a clock for the state machine.

  FIG. 9 shows a control unit 0907, a load logic 0902 having a memory 0901, a ring memory 0906, a configurable element 0905, a configuration element 0908, and an internal cell used for configuration. A connection with 0903 is shown. Here, the internal cell 0903 used for configuration is shown as a normal cell having a configurable element 0905 and a configuration element 0908. The ring memory 0906 is connected to the configuration element 0908 and controlled by the control unit 0907. The controller 0907 responds to different trigger pulses, which may come from the internal cell 0903 used for configuration. Via the response channel 0909, the controller 0907 notifies the load logic 0902 when new data is to be loaded into the ring memory 0906 based on the trigger event. In addition to sending this response, the controller 0907 further sends a signal to the multiplexer 0904 and the data from the load logic 0902 is sent to the ring memory or used internally for configuration. It is selected whether data is sent from the cell 0903 to the ring memory. In addition to ring memory configuration with load logic, the ring memory can be tuned as follows: Configurable element 0903 alone or as the last element in a group of elements is associated with ring memory 0906. Connected to generate entries. In this mode, the multiplexer 0904 passes data from 0903 to the ring memory, while in the configuration by the load logic, data from the load logic is connected. It is of course also conceivable to use another functional unit which is embodied in a fixed manner as the source of the configuration signal.

  FIG. 10 shows instruction processing by the control unit for instructions filed in the ring memory. Reference numeral 1001 denotes a ring memory having the following bit distribution. Bit 0 characterizes the entry as data or instruction bit. Bit 1 characterizes run and stop modes. Bits 2 to 6 represent an instruction number for encoding the instruction. Bit 7 indicates whether an instruction for a read position pointer or an instruction for a write position pointer is used. Bit 7 is not defined if the instruction does not affect the position pointer. In bits 8 to n, data necessary for an instruction is filed. The counters 1004 and 1005 form write / read position pointers belonging to the ring memory. When the control unit receives the trigger pulse, the state machine sends the pulse to the read position pointer. The write position pointer is not required for reading instructions and is only used to enter data into the ring memory. The selected read position pointer is advanced by one position and a new instruction is selected (bit 0 = 0). The instruction decoder 1002 is then added with bits 2-6 and bit 7, decoded and the result transferred to the state machine (1024). The state machine identifies which instruction is occurring and switches accordingly.

  If it is an instruction skip bit, the state machine 1011 sends a pulse to the adder / subtracter 1006, which is supplied via the multiplexer 1003 for the data from the counters 1004 and 1005, bits 8 to The instruction word data from n is added or subtracted. The multiplexer 1003 selects the write position pointer counter 1004 or the read position pointer counter 1005 depending on the bit 7. After the data is added / subtracted, the state machine 1011 activates the gate 1010 and sends an undertake signal to the counters 1004 and 1005. As a result, the selected position pointer indicates the position forward or backward by the number of positions indicated in the data of the skip instruction.

  In the case of the GOTO instruction, the gate 1007 is activated by the state machine 1011 so that the data reaches the write or read position counters 1004 and 1005 depending on bit 7 and is accepted there.

  O In the case of a MASK instruction, the data is received by latch 1008 and stored there. These data are then prepared via the connection A of the controller shown in FIGS. 7 / 7a, where they mask all trigger inputs from which trigger pulses should not be taken.

  In the case of a WAIT instruction, an event is waited for the number indicated in the data bit. When this instruction is recorded by the state machine 1011, it sends a pulse to the wait cycle counter 1009, which takes over the data. Therefore, the cycle counter counts down one digit for each event transferred from the state machine 1011. As soon as this counter counts to zero, the carry flag is set and sent to the state machine 1011 (1023). With this carry flag, the state machine continues to operate thereafter.

  In the case of a WAIT-GOTO instruction, data indicating the number of wait events is accepted by the wait cycle counter. When the number of events indicated in the data is reached, the state machine activates gate 1007 and transfers the data for the interlace location to the selected counter.

  O The SWAP instruction is used to exchange two entries between two locations in the ring memory. The latch 1017 stores the address of the first entry to be replaced, and the latch 1018 stores the address of the second entry to be replaced. These addresses are transferred to write / read pointer multiplexers 1015 and 1016. First, entry 1 is selected via 1016 and stored in latch 1019, then entry 2 is selected and stored in 1020 via 1016. The write pointer is set to the first entry via 1015 and the previous data of entry 2 is stored via gate 1022. Thereafter, the write pointer is set to the second entry via 1015 and the previous data of entry 1 is stored via gate 1021.

  The state machine 1011 sends the response via 1014 to the load logic (see, for example, German Patent Application No. 19651075.9 via the state back unit). The state machine sends a signal as soon as the LLBack instruction is recorded via this connection line.

  Bit 1 used as a run flag is sent to the clock generation unit of the control unit shown in FIG.

  ◎ NOP instruction is recorded in the state machine, but no operation is performed.

  FIG. 11 shows data word processing stored in the ring memory. Bit 0 is set to 1 because it is a data word. The instruction decoder 1107 sends a query 1106 to the cell addressed in bits 2-6 to identify it as a data word and whether it can be reconfigured. The inquiry is transmitted simultaneously with the activation of the gate 1102, whereby the cell address is transmitted. The cell indicates via 1105 whether reconfiguration is possible. If possible, gate 1103 is manipulated to transmit configuration data to the cell. If reconfiguration is not possible, processing continues and a new reconfiguration attempt is made in the next cycle in the ring memory. This sequence can be modified as follows. The state machine activates gates 1102 and 1103 and transmits data to the addressed cell. If the cell can be reconfigured, the cell acknowledges receipt of data via 1105. If reconfiguration is not possible, the cell does not send a received signal and a new reconfiguration is attempted in the next ring memory cycle.

  FIG. 12 shows a group (functional elements) (1202) of configurable elements (1201). Data reaches the functional element via the input bus (1204) and the result is sent first via the output bus (1205). At that time, 1205 is sent to two memory banks 1203, and one of these memory banks alternately operates as a write memory or a read memory each time. The output side of these memories is connected to the input bus (1204). The entire circuit can be configured (1206) via a bus leading to the switching table, in which both the trigger signal for the switching table and the trigger signal from the switching table are transmitted via this bus. In this case, in addition to the function of the functional element, the instantaneously active write / read memory and the memory depth of each memory are adjusted and set.

  FIG. 12a shows how data from the outside (1204), ie from another functional unit or module, is calculated in the functional element (1202) and then written to the write memory (1210). ing.

  FIG. 12b shows the next step of FIG. 12a. Functional element 1202 and memory 1220, 1221 have been reconfigured via 1206 according to a trigger generated by the functional element or memory or another unit. The write memory 1210 is now configured as a read memory (1220) and sends data to the functional element. The result is stored in the write memory 1221.

  FIG. 12c shows the next step of FIG. 12b. Functional element (1202) and memory (1230, 1231) have been reconfigured via 1206 according to a trigger generated by the functional element or memory or another unit. Write memory 1221 is now configured as read memory 1230 and sends data for functional elements. The result is stored in the write memory 1231. In this example, additional operands are computed together from the outside (1204), i.e. from another functional unit or module.

  FIG. 12d shows the next step after FIG. 12c. Functional element (1202) and memory (1203, 1240) have been reconfigured via 1206 according to a trigger generated by the functional element or memory or another unit. Write memory (1231) is now configured as read memory (1240) and sends data to functional elements. The result is transferred via the output bus (1205).

  FIG. 13 shows the circuit of FIG. 12, in which a memory with separate write and read pointers is used (1301) instead of two memory banks.

  FIG. 14 shows the memory (1401) of FIG. Reference numeral 1402 denotes a read position pointer, and the entry before the pointer has already been read or is empty (1405). The pointer points to a free pointer. There is data (1406) after the read position pointer and these must still be read. This is followed by an empty space (1404) and already newly written data (1407). The write position pointer (1403) points to an empty entry that is empty or has already been read. As described above, the memory can be configured as a ring memory.

  FIG. 15 shows the circuit of FIG. 12, in which two memory banks (1203) exist twice. This allows multiple results to be stored and then processed together.

  In FIG. 15a, data from the outside (1204), ie from another functional unit or module, is calculated in the functional element (1202) and then written to the write memory (1510) via the bus 1511. Is shown.

  FIG. 15b shows the next step of FIG. 15a. Functional element (1202) and memory (1203, 1510, 1520) have been reconfigured via 1206 according to a trigger generated by the functional element or memory or another unit. In this case, data from the outside (1204), ie from outside another functional unit or module, is calculated in the functional element (1202) and then written via the bus 1521 to the write memory (1520).

  FIG. 15c shows the next step of FIG. 15b. Functional element (1202) and memory (1203, 1530, 1531, 1532) have been reconfigured via 1206 according to a trigger generated by the functional element or memory or another unit. The write memories (1501, 1520) are now configured as read memories (1531, 1532). The read memory sends a plurality of operands simultaneously to the functional element (1202). In this case, the respective read memories (1531, 1532) are connected to 1202 by independent bus systems (1534, 1535). The result is stored in the write memory (1530) via 1533 or transferred via 1205.

Conceptual definition ALU arithmetic logic unit. Basic unit for data processing. This unit can perform operations such as addition, subtraction, and depending on the situation, multiplication, division, series expansion, etc. The unit can then be configured as an integer unit or a floating point unit. Similarly, the unit can perform logical operations such as AND, OR as well as comparisons.

  Data word A data word consists of a bit string of arbitrary length. This bit string represents a processing unit for the apparatus. In a data word, instructions for modules such as processors as well as pure data are encoded.

  DFP A data flow processor described in German Patent Application Publication No. 4416881.

  DPGA Conventional dynamic configurable FPGA.

  D flip-flop A memory element that stores a signal at the rising edge of the clock.

  EALU Extended arithmetic logic unit. ALU with extended special functions that are required or effective for the operation of the data processing device described in German Offenlegungsschrift 4 168 881. This is especially a counter.

Element A collective concept for all types of units that can be used in electronic modules as components and is independent of itself. That is, the elements include:
◎ All types of configurable cells ◎ Clusters ◎ RAM blocks ◎ Logic ◎ Calculation units ◎ Registers ◎ Multiplexers ◎ Chip I / O pins

Events Events can be evaluated by hardware elements in any form and manner suitable for the application and trigger a specified action as a response to this evaluation. Thus, for example, events include:
◎ Clock cycle of computing device.
◎ Internal or external interrupt signal.
◎ Trigger signal of another element in the module.
◎ Comparison of data stream and / or instruction stream with a certain value.
◎ Input / output events.
◎ Counter start, overflow, new set, etc.
◎ Comparative evaluation.

  Flag Status bit in the register that indicates the state.

  FPGA Programmable logic module. Conventional technology.

  Gate A group of transistors that perform basic logic functions. The basic functions are, for example, NAND, NOR, and transmission gate.

  Configurable elements Configurable elements represent units of logic modules that can be adjusted by configuration words for specific functions. Thus, the configurable elements are all kinds of RAM cells, multiplexers, arithmetic logic units, registers and all kinds of internal and external netting descriptions, etc.

  Configuration Coordination settings for logical units, (FPGA) cells or PAE functions and netting (see reconfiguration).

  Configuration memory The configuration memory contains one or more configuration words.

  Configuration word The configuration word consists of a bit string of arbitrary length. This bit string represents a valid adjustment setting for the element to be configured, resulting in a functional unit.

  Load logic A unit for the configuration and reconfiguration of PAEs. It consists of a microcontroller that is specifically tailored to the task.

  Latch A memory element that normally transfers a signal transparently during a high level and stores it during a low level. In part in PAE, a latch is used whose level function is exactly inverted. In this case, the inverter is switched before the usual latch clock.

  Read position pointer The address of the entry at the moment for read access in the FIFO or ring memory.

  Logic cell A configurable cell used in DFP, FPGA, DPGA that performs simple logic or arithmetic tasks according to its configuration.

  Oversampling Timing is synchronized with the base clock at a frequency that is a multiple of the base clock. This faster clock is often generated by a PLL.

  A unit (phase closed loop circuit) for multiplying the clock based on the PLL basic clock.

  Unit for configuration and reconfiguration of PLU PAE. It consists of a microcontroller that is specifically tailored to the task.

  Ring memory A memory that has its own write / read position pointer that is located at the end of the memory, that is, at the beginning of the memory. This results in an endless memory in the form of a ring.

  RS flip-flop Reset / set flip-flop. A memory element that can be switched by two signals.

  Write position pointer The address of the entry at the moment in time for a write access in the FIFO or ring memory.

  Stateback unit A unit that controls the response of state signals to the PLU. It consists of one multiplexer and one open collector bus driver circuit.

  Switching Table The switching table is a ring memory that is responded by the controller. A switching table entry can contain any configuration word. The controller can execute the instructions. The switching table reconfigures the configurable elements in response to the trigger signal and based on the entries in the ring memory (see configuration).

  Process Cycle The process cycle describes the duration that a unit needs to reach from the defined and / or valid state to the next defined and / or valid state.

State machine Logic that can take various states. The transition between states depends on different input parameters. These machines are used to control complex functions and are compatible with the prior art

The basic structure of a ring memory is shown. This represents the internal structure of the ring memory. Fig. 4 shows a ring memory having a selectable work area. Fig. 4 illustrates a controller that can work via multiple write and read position pointers for the ring memory and different sections of the ring memory. Represents a ring memory accessed by different controls in different sections. Fig. 4 shows the connection between a ring memory and a configurable element. A control unit with logic to be able to respond to different trigger signals is shown, a) shows the realization of the mask for the trigger pulse. A clock generator for the control unit is shown. In order to allow configuration of the elements to be configured, the interconnection between the control unit and the internal cell is shown. Processing by the control unit for instructions filed in the ring memory will be described. Processing of data stored in the ring memory will be described. Fig. 4 shows the connection of a temporary memory consisting of two memory banks to a number of configurable elements. A to d indicate a data processing sequence. The sequence example of a data processing is shown. The sequence example of a data processing is shown. The sequence example of a data processing is shown. The sequence example of a data processing is shown. Fig. 4 illustrates the connection of a temporary memory with separate write / read pointers to multiple configurable elements. Fig. 6 illustrates a temporary memory functional approach with separate write / read pointers. The connection of two temporary memories, each consisting of two memory banks, to a number of configurable elements is shown. The sequence example of a data processing is shown. The sequence example of a data processing is shown. The sequence example of a data processing is shown.

Claims (2)

A data processing unit comprising a two-dimensional or multi-dimensional cell device of configurable elements and a configuration data transmission unit assigned to the cell device, The configuration data transmission unit is realized as a load logic circuit or as another fixedly implemented functional unit used as an internal cell used for configuration or as a configuration signal source, where As a communication unit between a configurable element or group thereof and the configuration data transmission unit,
A switching table is provided, and the switching table includes a configuration memory (0404) for storing configuration data from the configuration data transmission unit.
One control unit (0401) , and the control unit (0401)
A read and / or write location pointer is selected there and moved to a configuration memory location in response to the arrival of an event or combination of such events reported from the element or group of elements, in real-time, configuration A word is transmitted from the configuration memory (0404) to the element to be configured to allow reconfiguration to be performed ;
The configuration memory (0404) is divided into independent sections ;
A plurality of write position pointers (0408) and a plurality of read position pointers (0402) are provided,
Of the plurality of write position pointers (0408), one write position pointer that accesses the configuration memory (0404) is selected via a write position pointer multiplexer (0407), and the plurality of read position pointers are selected. Among the pointers (0402), one read position pointer that accesses the configuration memory (0404) is selected via the read position pointer multiplexer (0407).
Write access or read access is selected via the multiplexer (0403) for write access or read access.
A data processing unit characterized by that. A data processing unit comprising a two-dimensional or multi-dimensional cell device of configurable elements and a configuration data transmission unit assigned to the cell device, The configuration data transmission unit is realized as a load logic circuit or as another fixedly implemented functional unit used as an internal cell used for configuration or as a configuration signal source, where As a communication unit between a configurable element or group thereof and the configuration data transmission unit,
A switching table is provided, and the switching table includes a configuration memory (0504) for storing configuration data from the configuration data transmitting unit .
A plurality of control units (0501) , and the control unit (0501)
A read and / or write location pointer is selected there and moved to a configuration memory location in response to the arrival of an event or combination of such events reported from the element or group of elements, in real-time, configuration A word is transmitted from the configuration memory (0504) to the element to be configured to allow reconfiguration to be performed ;
The configuration memory (0504) is divided into independent sections ;
One write position pointer (0506) and one read position pointer (0502) are assigned to each control unit (0501), and the plurality of control units (0501) each have one write and read position pointer. Operate in a unique region of the configuration memory (504) via (0506, 0502),
Of the plurality of write position pointers (0506), one write position pointer that accesses the configuration memory (0504) is selected via a write position pointer multiplexer (0505), and the plurality of read position pointers. Among the pointers (0506), one read position pointer that accesses the configuration memory (0504) is selected via the read position pointer multiplexer (0505), and
Write access or read access is selected via the multiplexer (0503) for write access or read access,
The write / read signal of the control unit (0501) reaches the configuration memory (0504) via the write / read signal multiplexer (0507).
Control signals for the write position pointer multiplexer (0505), the read position pointer multiplexer (0505), the write access or read access multiplexer (0503), and the write / read signal multiplexer (0507) are: From the control unit (0501) to each multiplexer via the arbiter (0508),
A data processing unit characterized by that.

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