JP4543055B2 - Nonvolatile semiconductor memory device - Google Patents

Description

  The present invention relates to an electrically rewritable nonvolatile semiconductor memory device (EEPROM), and more particularly to a data rewriting / reading data temporarily holding write data and read data which can realize a cache function and a multi-value logic operation function. The present invention relates to a reading circuit.

  In large-capacity flash EEPROMs used for file memory applications, it is a problem to reduce the bit unit price. Therefore, not only miniaturization with process technology and cell structure, but also a movement to increase capacity by using multi-value logic technology is becoming active.

  FIG. 42 shows a data rewrite / read circuit (hereinafter referred to as a page buffer) that realizes a multi-valued logic operation (4-valued logic operation) for storing 2-bit data in one nonvolatile memory cell in a NAND flash EEPROM. Designated). The page buffer is provided with a latch circuit 1 connected to the data input / output terminal I / O via the data input / output buffer 50 and a latch circuit 2 not directly connected to the data input / output buffer 50. Transfer transistors 42, 60, 30, and 61 are provided between the respective latch circuits 1 and 2 and the bit line BL of the memory cell 5, and transfer transistors 71 and 70 transfer VSS to a path for transferring VCC. Transfer transistors 80 and 81 are respectively provided in the paths for transferring, and transfer transistors 63 and 64 are provided for transferring the precharge potential VA to the bit line and transferring the shield potential VB.

  Thus, the two bit lines BLe and BLo are selectively connected to the page buffer so as to share one page buffer (refer to Non-Patent Document 1 for details).

  The 2-bit / cell implementation is achieved by defining the correspondence between the threshold distribution of memory cells and 2-bit logical data as shown in FIG. 43 (a), and assigning the first and second bits to different row addresses. One memory cell can write and read quaternary data. The first bit is the upper bit and the second bit is the lower bit. For example, in the case of “10”, the first bit is “1” and the second bit is “0”.

  When writing the second bit data in the write operation, first, write data corresponding to the second multi-value row address is loaded into the latch circuit 1 from the data input / output terminal. When the write data is “0”, writing is performed from the “11” state in FIG. 43A to the “10” state. When the write data is “1”, it becomes non-write (write prohibition) and remains in the “11” state.

  When writing the data of the first bit, as shown in FIG. 44, the write data corresponding to the first multi-value row address is loaded from the data input / output terminal to the latch circuit 1 and already written from the memory cell. The read second bit data is read out to the latch circuit 2. When the write data of the latch circuit 1 is “0”, when the second bit data held in the latch circuit 2 is “1”, the state is changed from the “11” state to the “01” state. When the second bit data held in the circuit 2 is “0”, writing is performed from the “10” state to the “00” state. When the write data of the first bit held in the latch circuit 1 is “1”, it is not written and the threshold value state of the second bit is kept as it is, and the “11” state is the “11” state. The “10” state maintains the “10” state.

  In this conventional example, 2-bit logical data is stored in one nonvolatile memory cell, but the first bit data is the first multi-value row address data, and the second bit data is the second multi-value data. It is treated as value row address data, and two row addresses are assigned to one memory cell. Here, the two row addresses are referred to as a first multi-value row address and a second multi-value row address.

  In the read operation, the selected word line voltage is set in the order of Vr00, Vr01, and Vr10 in FIG. 43A, the data at Vr00 is read to the latch circuit 1, and the data at Vr01 is read to the latch circuit 2. The read data at Vr10 is read out to the latch circuit 1 so that the bit line is recharged or redischarged with the data of the latch circuit 1 and the latch circuit 2 after the bit line is discharged and logically consistent. This is an example of a multi-valued operation. As described above, the page buffer corresponding to the multi-valued operation requires at least two latch circuits.

  While the capacity is increased by such multi-value operation, it is also important to improve the writing speed and reading speed of the flash EEPROM. Therefore, as shown in FIG. 45 (a), when the memory cell array 100 is divided into two parts 100a and 100b, the data is written simultaneously in the two cell arrays 100a and 100b after the data load for two pages. It is effective to increase the effective writing speed by increasing. In order to further improve the effective write speed, the write unit may be increased to 4 pages or 8 pages as a 4-split array or an 8-split array.

  However, when the number of cell array divisions is increased, the data load time becomes conspicuous as the write unit increases. For example, if one page (512 bytes) of data is loaded in a 1-byte data input cycle 50 ns, it takes about 25 us and 4 pages takes about 100 us. One writing time is about 200 us. Therefore, although the effective writing speed is improved by quadrupling the batch writing unit, it is necessary to wait about 100 us for loading data for four pages in order to write the next four pages continuously. In practice, when the number of cell array divisions is increased in this way, the chip area increases and the power consumption also increases.

As described above, the flash EEPROM is expected to have a large capacity and a high writing speed. However, in the case of multi-value operation, normal 1-bit logical data is stored in one nonvolatile memory cell. The writing time is several times longer than the binary operation writing. Therefore, since the write time is much longer than the data load time, in the case of multi-value operation, increasing the amount of data that can be collectively written by dividing the cell array is effective in improving the effective write speed. On the other hand, in order to increase the effective write speed during binary operation, it is effective to make the data load time invisible because the ratio of the data load time is large and inefficient due to the cell array division alone as described above. is there. For this purpose, as shown in FIG. 45 (b), caches (data registers) 140b1 and 140b2 may be provided separately from the page buffers 140a1 and 140a2 so that the next write data can be loaded during execution of the write operation. . The functional conditions of the caches 140b1 and 140b2 are that the page buffers 140a1 and 140a2 can exchange data with the data input / output terminals during read and write operations, can stably hold data, and the page buffers 140a1 and 140a2 In other words, bidirectional data transfer is possible.
K. Takeuchi et al. "A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memory", IEEE J. Solid-State Circuit Circuits, VOL. 33, pp. 1228-1238, Aug. 1998.

  As described above, the flash EEPROM is desired to realize a multi-valued logic function for increasing the capacity and to realize a cache function for increasing the speed. Both of these functions can be realized by providing two latch circuits in one page buffer. The present invention has been made in view of the above circumstances, and an object thereof is to provide a nonvolatile semiconductor memory device having a rewrite / read circuit capable of realizing a cache function and a multi-valued logic operation function under optimum conditions. To do. Another object of the present invention is to provide a nonvolatile semiconductor memory device having a sense amplifier circuit that can sense bit line data with a high sense margin.

  A nonvolatile semiconductor memory device according to the present invention includes a memory cell array in which electrically rewritable nonvolatile memory cells are arranged, a plurality of data temporarily storing data to be written to the memory cell array, and sensing read data from the memory cell array And a control circuit for controlling the data rewrite operation and the read operation of the memory cell array, each rewrite / read circuit being selectively connected to the memory cell array and mutual data A first latch circuit and a second latch circuit capable of transferring data, and storing two-bit quaternary data in one memory cell as different threshold voltage ranges; Rewriting / reading the upper and lower bits of the quaternary data using the second latch circuit With respect to the value logic operation mode and 1-bit binary data stored in one memory cell, a period in which data is exchanged between the memory cell selected by the first address and the first latch circuit. And a cache operation mode in which data is exchanged between the second latch circuit and the input / output terminal for the second address.

  According to the present invention, the data rewriting / reading circuit that temporarily holds the write data and the read data is provided with the secondary latch circuit, and the secondary latch circuit is operated effectively so that the cache function and the multiple Each value logic function can be realized under optimum conditions. That is, it becomes possible to switch between a flash EEPROM with priority on the writing speed by the cache function and a large capacity flash EEPROM by the multi-valued logic operation. In this case, the cache operation in the multi-level logic operation and the binary logic operation may be executed while being switched in time by command input, or depends on the data address in the multi-level operation. It is also possible for the cache operations to be performed by overlapping.

  The nonvolatile semiconductor memory device according to the present invention also temporarily stores a memory cell array in which electrically rewritable nonvolatile memory cells are arranged, data to be written to the memory cell array, and senses read data from the memory cell array A plurality of rewrite / read circuits; a data rewrite operation of the memory cell array; and a control circuit for controlling the read operation; each rewrite / read circuit includes a first transfer switch element on a selected bit line of the memory cell array And a first latch circuit connected in series via the second transfer switch element, and a connection node between the first transfer switch element and the second transfer switch element via the third transfer switch element And a data node of the second latch circuit is a second latch circuit. Characterized in that through the arm selection switch is connected to the data input and output lines. In this way, the cache function and the multi-valued logic operation function can be realized by setting the connection relationship between the first and second latch circuits constituting the rewrite / read circuit.

  In a preferred aspect of the present invention, after the data is written to the selected memory cell, a verify read operation for reading and confirming the write data is performed. Data sense and data holding in the verify read operation are performed by the first latch circuit. Shall be. In the present invention, more specifically, the rewrite / read circuit uses the first and second latch circuits so as to store 2-bit quaternary data in one memory cell as different threshold voltage ranges. A multi-valued logic operation mode for rewriting / reading upper and lower bits of quaternary data, and a memory cell selected by a first address for 1-bit binary data stored in one memory cell; It is assumed that a cache operation mode in which data is exchanged between the second latch circuit and the input / output terminal for the second address during a period in which data is exchanged with the first latch circuit is assumed. More specifically, the quaternary data is defined as “11”, “10”, “00”, “01” from the lower threshold voltage distribution of the memory cell. Assume that different row addresses are assigned to upper bits and lower bits, and writing and reading are performed.

  Further, in a preferred mode of the data write operation in the multi-level logic operation mode, after the lower bit data is loaded into the second latch circuit, it is transferred and held in the first latch circuit, and is based on the held data in the first latch circuit. The first data write operation for writing to the selected memory cell, and after the upper bit data is loaded into the second latch circuit, transferred and held in the first latch circuit, and the lower order of the already written selected memory cell The bit data is read, transferred and held in the second latch circuit, and written to the selected memory cell based on the data held in the first latch circuit under the condition determined according to the data held in the second latch circuit. 2 write operations.

  In a preferred mode of data reading in the multi-level logic operation mode, the read voltage applied to the control gate of the selected memory cell is set between the threshold voltage distributions of “10” and “00” of the four-value data, The first read operation for determining the bits “0” and “1” and the read voltage applied to the control gate of the selected memory cell are between the threshold voltage distributions of “00” and “01” of the quaternary data. The second read operation for determining the lower bits “0” and “1” when the upper bit is “0” and the read voltage applied to the control gate of the selected memory cell is “11” of the four-value data And a third read operation for setting the read voltage between the threshold voltage distribution of “10” and determining “0”, “1” of the lower bits when the upper bit is “1” And

  Further, in the present invention, for example, each rewrite / read circuit can switch connection to a plurality of bit lines of the memory cell array by a bit line selection switch element. In the rewrite / read circuit, a common signal line to which a predetermined potential is applied may be connected to a connection node between the first transfer switch element and the second transfer switch element via the fourth transfer switch element. A temporary storage node for saving and temporarily storing the potential of the data node of the first latch circuit, and a first storage node inserted between the fourth transfer switch element and the common signal line and controlled by the potential of the temporary storage node. 5 transfer switch elements.

  The nonvolatile semiconductor memory device according to the present invention also temporarily stores a memory cell array in which electrically rewritable nonvolatile memory cells are arranged, data to be written to the memory cell array, and senses read data from the memory cell array A plurality of rewrite / read circuits, a data rewrite operation of the memory cell array, and a control circuit for controlling the read operation, and each rewrite / read circuit is selectively connected to the memory cell array and The first latch circuit and the second latch circuit capable of data transfer, and the binary data stored in one memory cell, the memory cell selected by the first address and the first latch The second latch circuit for a second address during a period in which data is exchanged with the circuit. It characterized by having a cache operation mode in which data transfer is performed between the input and output terminals and. According to the present invention, it is possible to obtain a high-speed EEPROM in which a cache function is realized by cooperation of two latch circuits.

  In the present invention, when the data write operation cycle for the selected memory cell of the memory cell array is performed by repeatedly applying the write pulse and the write verify read, the write operation cycle with the write verify read data held in the first latch circuit. And a test mode in which the cell current of the selected memory cell is read out to the input / output terminal by keeping the second latch circuit inactive. Thus, if there is a test mode for measuring the cell current during the write operation, it can be used for various analyses.

  The nonvolatile semiconductor memory device according to the present invention also includes a memory cell array having nonvolatile memory cells in which data is stored depending on whether or not the current of the bit line is drawn, and a sense amplifier circuit for reading the bit line data of the memory cell array. The sense amplifier circuit includes a sense node connected to the bit line of the memory cell array via a clamp transistor, and the bit line is pre-connected via the clamp transistor connected to the sense node. A precharge circuit for charging; a sense amplifier body including an inverter having an input terminal connected to the sense node; and one end connected to the sense node and the other end as a drive terminal when sensing the bit line data A boost capacitor for boosting the sense node; Characterized in that was.

  In this way, when bit line data is sensed, the potential of the sense node is controlled by the boosting capacitor, so that the “H” and “L” levels of the binary data read out to the sense node are converted into an inverter circuit of the sense amplifier body. The optimum state can be adjusted in relation to the threshold value, and a high sense margin can be obtained.

  Specifically, the bit line data sensing of the sense amplifier circuit including the boosting operation of the sense node using the boosting capacitor is performed by the following series of operations. (A) The bit line is precharged by the precharge circuit while the clamping transistor is on, and (b) the clamping transistor while the potential changes according to the data of the selected memory cell. Off, keep the precharge circuit on and continue to precharge the sense node, (c) turn off the precharge circuit, drive the boosting capacitor to boost the sense node, and (d) the clamping transistor A read voltage is applied to the gate to transfer the bit line data to the sense node. More specifically, after (d) bit line data transfer, (e) the read voltage applied to the clamping transistor is lowered to a voltage higher than the threshold voltage of the clamping transistor, and then boosted. The boosting operation of the sense node by the capacitor is stopped.

  Even if the on-resistance of the selected memory cell is large and the “L” level of the data read out to the sense node is not sufficiently low by the sensing operation including such a boosting operation, the sensing operation is performed at a lower level. Data can be reliably determined regardless of variations in circuit threshold values of the amplifier body. Also, by reducing the read voltage of the clamping transistor after data transfer, it is possible to prevent the sense node from swinging in the negative potential direction as a result of the boosting operation in the case of a sufficiently low “L” level read. Can do.

  The nonvolatile semiconductor memory device according to the present invention further includes a memory cell array having a nonvolatile memory cell in which data is stored depending on whether or not the current of the bit line is drawn, and a sense amplifier circuit for reading the bit line data of the memory cell array. The sense amplifier circuit includes a sense node connected to the bit line of the memory cell array via a clamp transistor, and the bit line is pre-connected via the clamp transistor connected to the sense node. A precharge circuit for charging; a sense amplifier body including a sense transistor having a gate connected to the sense node and a source fixed at a reference potential; one end connected to the sense node; and the other end serving as a drive terminal When the bit line data is sensed, the sense node is increased. A boosting capacitor to characterized by comprising a.

  In the case of a sense amplifier circuit system including a sense transistor having a gate connected to a sense node between a latch circuit or the like that holds read data and a sense node, a boost capacitor is provided at the sense node, and a bit line Similarly, a high sense merge can be obtained by controlling the potential of the sense node during data sensing. The data sensing operation in this case is also performed by the series of operations (a) to (d) described above or the series of operations (a) to (e).

  As described above, according to the present invention, a rewrite / read circuit having two latch circuits realizes a flash EEPROM with priority on the writing speed by the cache function and a flash EEPROM with priority on increasing the capacity by the multi-value logic function. be able to.

[Embodiment 1]
FIG. 1 is a block diagram showing the overall configuration of a NAND flash EEPROM according to an embodiment of the present invention. As shown in FIG. 3, the memory cell array 100 includes a plurality of (16 in the illustrated example) stacked gate structure electrically rewritable nonvolatile memory cells MC0 to MC15 connected in series to NAND cell units NU ( NU0, NU1,. Each NAND cell unit NU has a drain side connected to the bit line BL via the selection gate transistor SG1, and a source side connected to the common source line CELSRC via the selection gate transistor SG2. The control gates of the memory cells MC arranged in the row direction are commonly connected to the word line WL, and select gate transistors SG1. The gate electrode of SG2 is connected to select gate lines SGD and SGS arranged in parallel with the word line WL.

  A range of memory cells selected by one word line WL is one page as a unit of writing and reading. A range of a plurality of NAND cell units NU in one page or an integral multiple of one page is one block which is a unit of data erasure. The rewrite / read circuit 140 includes a sense amplifier circuit (SA) and a latch circuit (DL) provided for each bit line in order to write and read data in page units, and is hereinafter referred to as a page buffer.

  The memory cell array 100 of FIG. 3 has a simplified configuration, and a page buffer may be shared by a plurality of bit lines. In this case, the number of bit lines selectively connected to the page buffer at the time of data write or read operation is a unit of one page. FIG. 3 shows a range of the cell array in which data is input / output to / from one data input / output terminal (I / O). In order to select a word line WL and a bit line BL of the memory cell array 100, a row decoder 120 and a column decoder 150 are provided, respectively. The control circuit 110 performs sequence control of data writing, erasing and reading. The high voltage generation circuit 130 controlled by the control circuit 110 generates a boosted high voltage or intermediate voltage used for data rewriting, erasing, and reading.

  The input / output buffer 50 is used for data input / output and address signal input. That is, data is transferred between the I / O terminals I / O 0 to I / O 8 and the data rewrite / read circuit 140 via the input / output buffer 50. An address signal input from the I / O terminal is held in the address register 180 and sent to the row decoder 120 and the column decoder 150 to be decoded.

  An operation control command is also input from the I / O terminal. The input command is decoded and held in the command register 170, whereby the control circuit 110 is controlled. External control signals such as chip enable signal CEB, command latch enable CLE, address latch enable signal ALE, write enable signal WEB, and read enable signal REB are taken into operation logic control circuit 190, and an internal control signal is generated according to the operation mode. Is done. The internal control signal is used for control such as data latch and transfer in the input / output buffer 50, and is sent to the control circuit 110 to perform operation control. The ready / busy register 210 informs the outside whether the chip is in a ready state or a busy state.

  In this embodiment, the rewrite / read circuit (that is, the page buffer) 140 is configured to be able to switch between a multi-value operation function and a cache function. That is, a cache function is provided when 1-bit binary data is stored in one memory cell, or a cache function is provided when 2-bit quaternary data is stored in one memory cell. Although limited by the address, the cache function can be enabled. A specific configuration of the rewrite / read circuit 140 for realizing such a function is shown in FIG. In FIG. 2, two bit lines BLe and BLo are selectively connected to the page buffer 140. In this case, the NMOS transistor 60 or 61 is turned on by the bit line selection signal BLTRe or BLTRo, and either the bit line BLe or the bit line BLo is selectively connected to the page buffer 140.

  While the one bit line is selected, the other bit line in the non-selected state is set to a fixed GND potential or Vdd potential, which is effective in reducing noise between adjacent bit lines. In addition to the NAND flash memory, in an EEPROM that serially inputs / outputs one page of data for a certain row address and collectively processes a write operation and a read operation to a memory cell, The layout size of the writing circuit and the reading circuit is determined. As the bit line pitch becomes narrower, the layout of these circuits becomes difficult, so sharing the page buffer with multiple bit lines not only increases the degree of layout freedom but also reduces the area of the page buffer layout. There are benefits.

  The page buffer 140 in FIG. 2 includes a main rewrite / read circuit 10 including the first latch circuit 1 and a second latch circuit 2. The main rewrite / read circuit 10 including the first latch circuit 1 mainly contributes to read and write operations by operation control described later. The second latch circuit 2 is a secondary latch circuit that realizes a cache function in the binary operation, and supplementarily contributes to the operation of the main rewrite / read circuit 10 when the cache function is not used. Multi-level operation will be realized.

  The latch circuit 1 of the main rewrite / read circuit 10 is configured by connecting clocked inverters CI1 and CI2 in antiparallel. The bit line BL of the memory cell array is connected to a sense node N4 via an NMOS transistor 41 which is a transfer switch element. The sense node N4 is further connected to a data holding node N1 of the latch circuit 1 via an NMOS transistor 42 which is a transfer switch element. It is connected to the. A precharge NMOS transistor 47 is provided at the sense node N4.

  The node N1 is connected to a temporary storage node N3 for temporarily storing data of the node N1 through an NMOS transistor 45 which is a transfer switch element. An NMOS transistor 46 for precharging VREG is also connected to the storage node N3. A capacitor 49 for maintaining the level is connected to the node N3. The terminal of the capacitor 49 is grounded.

  The common signal line COM in FIG. 2 is disposed in common in the rewrite / read circuit 140 for 1 byte for each column. The common signal line COM is connected to the sense node N4 via an NMOS transistor 44 that is a transfer switch element controlled by the node N3 and an NMOS transistor 43 that is a transfer switch element controlled by the control signal REG. The common signal line COM is used as a Vdd power supply line used when the sense node N4 is selectively charged, and as a signal line for performing pass / fail judgment in the write / erase verify operation.

  Similar to the first latch circuit 1, the second latch circuit 2 is configured by connecting clocked inverters CI 1 and CI 2 in antiparallel. The two data nodes N5 and N6 of the latch circuit 2 are connected to data lines io and ion connected to the data buffer via column gate NMOS transistors 51 and 52 controlled by a column selection signal CSL. The node N5 is connected to a precharging PMOS transistor 82 for charging it to Vdd. The node N5 is also connected to the node N4 of the main rewrite / read circuit 10 via the NMOS transistor 30 which is a transfer switch element.

  FIG. 3 shows a connection relationship between the page buffer 140 and the data input / output buffer 50. The processing unit of reading and writing of the NAND flash EEPROM has a capacity of 512 bytes for one page that is simultaneously selected at a certain row address. Since there are eight data input / output terminals I / O, there are 512 bits for one data input / output terminal I / O, and FIG. 3 shows the configuration for 512 bits.

  When the cell array is divided into a plurality of cells as shown in FIG. 45, the portion 140a including the first latch circuit 1 of the page buffer 140 corresponds to the plurality of page buffers 140a1 and 140a2, and the second latch circuit 2 The portion 140b including “” is a portion corresponding to the plurality of caches in FIG. For example, in the write operation, 512 page buffers are required to simultaneously write 512-bit data. Each 512-bit data corresponds to a column address. One page buffer is selected from 512 page buffers by signals CSL0 to CSL511 obtained by decoding column addresses, and data is input / output to / from the data signal line io via the column selection switch element.

  Next, the basic operation of the rewrite / read circuit 140 in this embodiment will be described with reference to FIGS. When data is written to the memory cell, write data is taken into the second latch circuit 2 from the data signal lines io and ion. Since the write data must be in the first latch circuit 1 to start the write operation, the data held in the latch circuit 2 is subsequently transferred to the latch circuit 1. In the read operation, since the read data must be in the latch circuit 2 in order to output data to the data input / output terminal I / O, the data read by the latch circuit 1 needs to be transferred to the latch circuit 2. There is. Therefore, as shown in FIG. 4, it is possible to transfer data between the latch circuit 1 and the latch circuit 2 by making the switch elements 42 and 30 conductive. At this time, data is transferred after the transfer destination latch circuit is deactivated, and then the transfer destination latch circuit is returned to the active state to hold the data.

  FIG. 5 shows a state during writing to the memory cell and reading operation from the memory cell. Except for the case of multi-value operation, normally, the write operation control and the read operation control are performed by the main rewrite / read circuit 10 including the first latch circuit 1. At this time, the switch element 30 is held in the non-conductive state, and the switch elements 41 and 42 are set in the conductive state, so that data can be exchanged between the latch circuit 1 and the bit line of the memory cell array.

  FIG. 6 shows that only the switch elements 43 and 42 are in a conductive state as an operation during the write verify read for checking the write state. This is due to the bit-by-bit verify function in the write operation. For example, when “1” is written to the “1” cell in the erased state, it is a non-write (write inhibit) operation. Even so, the selected bit line is discharged by the verify read, and the read data becomes “1”, that is, a write failure. In order to pass this, the switches 42 and 43 are turned on after the bit line is discharged, and the latch circuit 1 is controlled to be recharged to “H” level. Here, “pass” means a state in which a desired write operation is completed, and “fail” means a state in which a desired write operation is not completed.

  FIG. 7 shows a state in which a write operation is performed in the multi-value operation mode. There is a case where the first bit write data is temporarily held in the latch circuit 1 and the second bit data is held in the latch circuit 2 to perform the write operation. At this time, the second bit data is read from the memory cell. In order to read data, the switch element 42 is turned off, the first bit write data is held in the latch circuit 1, the switch elements 41 and 30 are turned on, and data is read from the memory cell to the latch circuit 2. Further, in the write verify read after the write pulse application operation in this write operation, there is an operation of precharging the bit line from the latch circuit 2, and also in this case, the switch elements 41 and 30 are controlled to be in a conductive state.

  FIG. 8 shows a state in the read operation when the second multi-value row address is selected in the multi-value operation mode. The data read from the bit line can be forcibly changed by controlling the switch elements 42 and 43 to the conductive state and setting the common signal line COM to the GND potential. As a result, the data is correctly read according to the relationship between Vt and data in FIG.

  Next, the multi-value logic operation will be specifically described. In this embodiment, a multi-value operation is performed with respect to FIG. 43 (a) based on the correspondence between the threshold value (Vt) of the memory cell and 2-bit logical data as shown in FIG. 43 (b). . The correspondence between the Vt of the memory cell and the data is different from the case of FIG. 43A, but the upper bit and the lower bit are the data corresponding to different row addresses, respectively. That is, only in the multi-value operation, there are two row addresses for the same selected cell, and the row addresses assigned to the upper bit and the lower bit are respectively designated as the first multi-value row address and the second multi-value address. This will be referred to as a row address for use.

  Here, the data when the first multi-value row address is selected is the first bit (upper bit) of FIG. 43B, and the data when the second multi-value row address is selected is shown in FIG. This is the second bit (lower bit) of b). For example, in the case of “10”, the data of the first bit (upper bit) is “1”, and the data of the second bit (lower bit) is “0”.

  First, writing and write verify reading when the second multi-value row address is selected will be described. FIG. 9A is a flowchart of the write operation when the second multi-value row address is selected. First, write data when the second multi-value row address is selected is loaded from the data signal line io / ion to the latch circuit 2 (step S11). Data corresponding to the column address is taken into the latch circuit 2 while 512 bytes of data for one page are serially input. When the data load for one page is completed, data transfer from the latch circuit 2 to the latch circuit 1 is performed (step S12).

  A timing diagram of data transfer from the latch circuit 2 to the latch circuit 1 is shown in FIG. Write data is transferred from the latch circuit 2 to the latch circuit 1 by setting the gate BLCD of the switch element NMOS transistor 42 and the gate BLCD2 of the switch element NMOS transistor 30 to the “H” level potential at which Vdd can be transferred. In FIG. 10A, “H” data is loaded into the latch circuit 2 after data loading, and the node N5 is at the “H” level (Vdd). After this data transfer, a write operation is started (step S13).

  FIG. 11 shows the timing of the write pulse application operation. Write data of the latch circuit 1 is transferred to the selected bit line via the NMOS transistor 42, the NMOS transistor 41, and the bit line selection transistor 60. A voltage sufficient to transfer Vdd to the bit line BLe is applied to the gate of the transfer transistor between the latch circuit 1 and the bit line BLe. In this example, among the two bit lines sharing one page buffer, BLe is selected by the address. In all of the following operation descriptions, BLe is a selected bit line.

  At this time, when the node N1 which is one end of the latch circuit 1 is at the “H” level, the “H” level is transferred to the bit line BLe, and the non-write state “1” is set. Conversely, when the node N1 is at the “L” level, the “0” write state is entered. In FIG. 11, the “L” level is transferred to the selected bit line BLe (solid line), and “0” is written from the “11” state to the “10” state.

  Here, in the NAND flash EEPROM, the erased state before writing is a state of a negative threshold Vt as shown in the “11” state of FIG. In the erase operation, as shown in FIG. 12A, all the word lines 510 of the selected block are set to 0V, the source / drain 512 of the memory cell is floated, and the P well 513 of the memory cell is set to a positive high erase voltage (about 20V). Then, electrons are extracted from the floating gate 511. In the write pulse application operation, as shown in FIG. 12B, the selected word line 510 is set to a positive high write voltage Vpgm (15 to 20 V), the P well 513 is set to 0 V, and electrons are supplied to the floating gate 511. A bias relationship is set so as to be injected.

  At this time, when 0 V is transferred from the latch circuit 1 to the bit line BLe, the N-type diffusion layer 512 is set to 0 V via the bit line, the bit line side selection transistor, and the non-selected cell in the NAND cell unit. Is transferred, a potential difference sufficient for writing occurs between the channel of the memory cell and the floating gate 511, and electrons are injected. On the other hand, when the “H” level is transferred from the latch circuit 1 to the selected bit line, the channel potential of the selected memory cell increases, and the potential difference between the channel of the memory cell and the floating gate 511 decreases. Electrons are not injected. In order to increase the channel potential when data is not written in this way, an intermediate potential (about 8 V) called Vpass is applied to the word lines of unselected memory cells. However, Vpass is applied only to unselected word lines in the NAND cell unit having the selected word line.

  Write verify read Verify10 is performed after the write pulse application operation (step S14). This timing is shown in FIG. In Verify 10, reading is performed with the potential of the selected word line set to Vv 10 (see FIG. 43B). A pass voltage Vread is applied to unselected word lines in the same NAND cell unit to set the unselected cells as pass transistors, and only the conduction state of the memory cells on the selected word line is determined. From time R4 to R7, which is the bit line precharge period, the NMOS transistors 47 and 41 and the bit line selection transistor 60 are turned on to precharge the bit line BLe. At this time, Vpre is applied to the gate of the NMOS transistor 41, and the bit line BLe is precharged with a voltage Vpre-Vt lower than Vpre by the threshold voltage Vt. This bit line precharge potential Vpre-Vt is a potential lower than Vdd.

  When the source side select transistor SG2 of the NAND cell unit NU is turned on at time R7, the discharge of the bit line BLe is started according to the threshold state of the selected cell. That is, if Vt of the selected memory cell is lower than Vv10, the selected memory cell is turned on and the bit line precharge potential Vpre-Vt is discharged. On the other hand, if Vt of the selected memory cell is higher than Vv10, since the selected memory cell is not turned on, the bit line precharge potential Vpre-Vt is held. Thereafter, the write data is stored in the node N3 before the bit line potential is amplified and sensed. Before time S1, node N3 is charged with Vdd + α to be in a floating state, and then DTG is set to Vdd at time S2. The capacitor 49 is provided in order to make it difficult to receive a potential drop due to a leakage current or noise due to coupling between wirings during a period in which the potential of the node N3 is kept floating.

  When the node N1 holding the write data is at the “H” level, the MOS transistor 45 is not turned on. Therefore, the node N3 holds the “H” level, and when the node N1 is at the “L” level. Since the MOS transistor 45 is turned on, the node N3 becomes “L” level. Thereafter, the latch circuit 1 is deactivated in order to amplify and sense the bit line potential. That is, LAT and SEN are set to “L”, and their inverted signals LATB and SENB (see FIG. 2) are set to “H”.

  After the latch circuit 1 is deactivated, the BLCD is set to the “H” level, the switch element 42 is turned on, the nodes N1 and N4 are set to the same potential, the NMOS transistor 47 is turned on, and these nodes are turned on. Charge to H ”level. At time S7, the sense voltage Vsen is applied to BLCLAMP. When the bit line potential is discharged from Vpre-Vt to Vsen-Vt, the NMOS transistor 41 is turned on, so that the potentials of the nodes N1 and N4 are decreased to be substantially equal to the bit line potential. At this time, the potentials of the nodes N1 and N4 drop from Vdd to the bit line potential. Further, since the bit line capacitance is very large compared to the capacitances of the nodes N1 and N4, the charges at the nodes N1 and N4 are instantaneously released. When the bit line potential is not discharged to Vsen−Vt, the NMOS transistor 41 is not turned on, so that Vdd is held at the nodes N1 and N4.

  When the potential of the node N1 decreases, the potential decreases only to the bit line potential. However, when Vdd is held, the bit line amplitude is amplified because Vdd is higher than the bit line precharge potential Vpre-Vt. appear. In the drawing, the solid line of the waveform of the bit line BLe indicates that the memory cell is a memory cell that is insufficiently written or non-written because it is discharged.

  At time S9, REG is set to “H”, and the switch element transistor 43 is turned on. When the node N3 is “L”, that is, when the write pulse application operation is in the “0” write state, the NMOS transistor 44 is not turned on, so the potentials of the nodes N1 and N4 are not changed, and the time The potential reflecting the bit line potential is held at the node N1 until S11. When SEN is set to “H” and SENB is set to “L” at time S11, the clocked inverter of the latch circuit 1 having the node N1 as a gate is activated, and the potential of the node N1 is sensed by the clocked inverter. When the latch circuit 1 is activated by setting the LAT to “H” and the LATB to “L” at the time S12, the potential of the node N1 is fetched as binary information of “L” or “H”. As a result, when “L” is latched at the node N 1, “L” is transferred to the selected bit line again in the next write pulse application operation, so that “0” is written.

  Further, if the cell current does not flow and the bit line precharge level is maintained as shown by the broken line waveform of the bit line BLe in the drawing, “H” is latched in the latch circuit 1 after sensing, and writing in this memory cell is performed. finish. When “H” is latched as a result of the write verify read, the “H” level is transferred to the selected bit line even when the next write pulse application operation is started, and a non-write “1” write state is set.

  When the node N3 is “H”, that is, when the write pulse application operation is in the “1” write state, the “H” level is transferred from the common signal line COM to the nodes N1 and N4. Therefore, “H” is latched again at the node N1 at time S12. Therefore, in the “1” write state, regardless of the result of the write verify, “H” is latched at the node N1, and the non-write “1” write state is held.

  FIG. 32 and FIG. 33 summarize the potential relation of each part of these operations. In the page buffer that has been written, the node N1 changes to the “1” write state at the “H” level, and therefore the state of the node N1 of all the page buffers in one page or the inverted state N2 thereof is detected. Thus, it can be determined whether or not writing for one page has been completed (step S15). If there is even one page buffer whose node N1 is at "L" level, the write pulse application operation and the write verify read shown in FIG. 11 are performed again.

  In the NAND flash EEPROM, as a result of the write verify read as described above, in the memory cell in which writing has been completed, the page buffer connected to the memory cell is changed to the “1” write state. Even if the write pulse application operation is performed until the cell is written, the Vt distribution can be controlled narrowly. This method of controlling writing in individual page buffers in one page is referred to as bit-by-bit verification. In order to improve the writing speed, the write pulse application operation is performed by gradually increasing the write voltage Vpgm every time the write pulse application operation and the write verify read are repeated. Therefore, when only the potential of the selected word line is viewed, a waveform (solid line) as shown in FIG. 14 is obtained.

  Next, writing and write verify reading when the first multi-value row address is selected will be described. FIG. 9B shows a flowchart of the write operation of the upper bits (when the first multi-value row address is selected). First, write data when the first multi-value row address is selected is loaded from the external data input / output terminal to the latch circuit 2 (step S21). Thereafter, the write data is transferred from the latch circuit 2 to the latch circuit 1 at the timing of FIG. 10 (step S22). The steps so far are step 1 in FIG.

  Next, as shown in FIG. 15B, the data of the lower bits (when the second multi-value row address is selected) already written in the memory cell is taken into the latch circuit 2 (step S23). This operation is called internal data loading. The internal data load timing is shown in FIG. The state of the latch after data transfer is illustrated as N1 being “L” (solid line). Here, reading is performed with the potential of the selected word line set to Vr10 (see FIG. 43B). Here, the first multi-value row address and the second multi-value row address select the same word line. From time R4 to R7 in the bit line precharge period, the NMOS transistors 47 and 41 and the bit line selection transistor 60 are turned on to precharge the bit line BLe. At this time, Vpre is applied to the gate of the NMOS transistor 41, and Vpre-Vt is precharged to the bit line BLe.

  When the source side select transistor SG2 of the NAND cell unit is turned on at time R7, the discharge of the bit line is started depending on the state of the cell. The solid line of the bit line BLe waveform in the figure assumes a cell in the “11” state. Only in this read operation, read data is taken into the latch circuit 2. Therefore, before sensing the bit line potential, CLAT and CSEN are set to “L” at time S4 to make the latch circuit 2 inactive. CLATB and CSENB are inverted signals of CLAT and CSEN, respectively. At time S5, the BLCD 2 is set to the “H” level to make the switch element 30 conductive, and the NMOS transistor 47 precharges the nodes N4 and N5 to Vdd.

  When the sense voltage Vsen is applied to BLCLAMP at time S7, potentials reflecting the bit line potential appear at the nodes N4 and N5 by the operation using the clamp described above. At time S11, CSEN is set to “H” and CSENB is set to “L” to activate the clocked inverter of the latch circuit 2 in which the node N5 is an input gate, and the node N5 is sensed by the clocked inverter. CLAT is set to “H”, CLATB is set to “L”, and the latch circuit 2 is activated to capture data (step S23). During this operation, since the BLCD is “L”, the NMOS transistor 42 is in a non-conductive state, and the write data input from the outside is held in the latch circuit 1.

  As described above, the write pulse application operation is performed in a state where the write data of the first multi-value row address is read from the latch circuit 1 and the second multi-value row address data is read from the memory cell and held in the latch circuit 2. Is started (step S24). The write pulse application operation is performed at the timing of FIG. 11 as described above, and the data held in the latch circuit 1 is transferred to the selected bit line to perform the write pulse application operation. In writing when the first multi-value row address is selected, the distribution of Vt is changed as shown in FIG. When the “L” level is held at the node N1 of the latch circuit 1, the “11” state is written into the “01” state and the “10” state is written into the “00” state. Further, when the “H” level is held at the node N1 of the latch circuit 1, “1” writing is performed without writing, so that the “11” state and the “10” state are held as they are. Therefore, there are four cases, and the summary of each operation is shown in FIGS.

  Writing from the “11” state to the “01” state and the “10” state to the “00” state is performed simultaneously by applying the same write voltage to the selected word line. Therefore, as shown in FIG. 9B, the write verify read Verify 00 (Step S25) in the “00” state and the write verify read Verify 01 (Step S26) in the “01” state are performed once in the write pulse application operation. It needs to be done later. Therefore, it is necessary to prevent the memory cell that has been written to the “01” state from being terminated by the write verify in the “00” state. This is because, in the write verify read (Verify00) in the “00” state, reading is performed with the selected word line voltage set to Vv00, but in the memory cell to be written to the “01” state, Vt rises to the “00” state. This is because Verify00 does not discharge the bit line potential, so that it appears as if it was written.

Therefore, here, the write verify read control is performed based on the data corresponding to the second multi-value row address held in the latch circuit 2. The timing of the write verify read Verify 00 in step S25 is shown in FIG. Times R4 to R7 are a bit line precharge period, during which the NMOS transistors 30, 41 and the bit line select transistor 60 are turned on to perform bit line precharge. By turning on the MOS transistor 30, the node N5 of the latch circuit 2 is precharged to the bit line BLe.
In the writing from the “11” state to the “01” state, which is a problem, the node N5 of the latch circuit 2 is set to “L” after performing an internal data load for reading data corresponding to the second multi-value row address. It has become. This is because in the internal data load described above, the selected word line voltage is set to Vr10, so that the memory cell in the "11" state is turned on to discharge the precharge potential of the bit line, and "L" is taken in after sensing. Because. Therefore, the page buffer that is writing to the “01” state precharges the “L” level. For the memory cell to be written to the “01” state, the result of the write verify read must be failed at Verify 00, so that the file is precharged from the beginning. On the other hand, in the page buffer for writing from the “10” state to the “00” state, the node N5 of the latch circuit 2 is “H”. Therefore, in this case, the bit line precharge similar to other read operations is performed. Since the latch circuit 2 is included in each page buffer in the page which is a write unit, the page buffer which is writing to the “00” state performs normal precharge to the selected bit line and the “01” state. In the page buffer in which data is written, precharge for failing is selectively performed.

  If the bit line is held at 0V before the operation of Verify00, unnecessary precharge current does not flow during the period in which Verify00 is started and selective precharge from the latch circuit 2 is performed. There is also an advantage that the current is reduced. The waveforms of the node N5 and the bit line BLe in FIG. 17 indicate the case where the solid line is written to the “00” state as a result of the internal data load, and the broken line holding the GND level from the beginning is written to the “01” state. Show.

  After time R7, it is the same as the above-mentioned write verify read. In the page buffer for writing in the “00” state, the bit line BLe is precharged during the period up to time R7 as shown by the solid line of the bit line BLe waveform. Depending on the conduction state of the selected memory cell, the bit line BLe is not discharged or discharged, and is amplified and sensed by the sense voltage Vsen after time S7, and the write result is taken into the latch circuit 1. On the other hand, similarly, in the “1” write in which the “10” state in which “H” is held in the latch circuit 2 is held in the “10” state, the node N1 of the latch 1 holds the “H” level. Therefore, by the above-described verify operation for each bit, the node N1 is charged to the “H” level by the data of the node N3 at time S9, so that the “1” write state is maintained.

  Next, the subsequent write verify read (Verify01) to the “01” state in step S26 will be described. The timing is shown in FIG. Here, reading is performed with the selected word line potential set to Vv01 (see FIG. 43B). This case is the same as Verify 10 described above except for the selected word line potential.

  In the page buffer for writing from the “11” state to the “01” state, it is only necessary to sense the bit line potential at the selected word line potential Vv01. The battery is charged and the “1” write state is maintained. On the other hand, in the page buffer for writing from the “10” state to the “00” state, the memory cell that has failed to write in Verify00 always fails in Verify01. This is because the Vt of the memory cell that fails at Vverify00 is lower than Vv00, so that the selected word line voltage Vv01 at the time of Vverify01 makes reading easier. Further, in the “1” write page buffer that holds the “00” state, the “1” write state is held by the aforementioned bit-by-bit verify operation, so that there is no problem.

  As described above, the desired write verify read can be realized at Verify 00 and Verify 01, and the write cycle including the write pulse application operation and the write verify read is performed until writing is completed in all the page buffers in the page (Step S27). Repeatedly, writing at the time of selecting the first multi-value row address can be executed.

  Next, the reading operation will be described. As shown in FIG. 43 (b), 2-bit logical data at the time of multi-value operation, the upper bit is the data when the first multi-value row address is selected, and the lower bit is the second multi-value row address selection. Like time data, since it is assigned to a row address, the reading method differs depending on the row address. 19A and 19B show a flowchart of the read operation during the multi-value operation.

  In the case of reading the upper bits to which the first multi-value row address is inputted, the step is performed as shown in FIG. 19B by reading with the selected word line potential set to Vr00 (see FIG. 43B). The binary data “0” or “1” can be read out only by performing one read operation Read00 shown in S41. When the second multi-value row address is input, it is necessary to read the selected word line potentials at Vr01 and Vr10 (see FIG. 43B), and steps S31 and S32 shown in FIG. The two read operations Read01 and Read10 are required.

  First, a read operation when the first multi-value row address is selected will be described. The timing of this read operation Read00 is shown in FIG. During the bit line precharge period up to time R7, the NMOS transistors 47 and 41 and the bit line selection transistor 60 are turned on. Since Vpre is applied to the gate of the NMOS transistor 41, Vpre-Vt is precharged to the bit line BLe. When the source side select transistor SG2 of the NAND cell unit is turned on at time R7, discharge of the selected bit line is started depending on the threshold state of the cell.

  At time S4, LAT and SEN are set to the “L” level, the latch circuit 1 is deactivated, the NMOS transistor 42 is turned on, the nodes N1 and N4 are set to the same potential, and the MOS transistor 47 is turned on to Vdd. To charge. At time S7, the gate BLCLAMP of the NMOS transistor 41 is set to Vsen, and the bit line potential is clamped and read. As a result, the bit line potential with the small amplitude Vpre−Vsen (about 0.4 V) can be amplified and read at the node N1 as described above. Thereafter, at times S11 and S12, SEN and LAT are sequentially set to “H”, the clocked inverter of the latch circuit 1 is sequentially activated, and the data of the node N1 is taken into the latch circuit 1 and held.

  After the read data is taken into the latch circuit 1, the read data held in the latch circuit 1 for one page is simultaneously transferred to the latch circuit 2 (step S42). When one page is 512 bytes, data is transferred from the latch circuit 1 to the latch circuit 2 in each page buffer for 512 bytes. FIG. 10B shows the timing for transferring data from the latch circuit 1 to the latch circuit 2.

  Since the latch circuit 2 is connected to the data input / output buffer 50 by the column selection transistors 51 and 52, when the column decode signal CSL becomes “H” according to the column address, the data signal lines io / ion from the respective latch circuits 2 The data is output to the outside via the data input / output buffer 50. When the memory cell array is composed of two arrays as shown in FIG. 45 (b) and one page of each cell array is selected with one row address and the above read operation is performed simultaneously, two memory pages are stored. This data transfer can be performed simultaneously in the page buffer. In this case, after data transfer, first, the data input / output buffer 50 is controlled so that one page of data in the cell array 100a is output from the latch circuit 2 and then one page of data in the cell array 100b is output to the outside. .

  As described above, the data when the first multi-value row address is selected in the multi-value operation mode can be output to the outside by one read operation and data transfer. Next, a read operation when the second multi-value row address is selected will be described. As shown in FIG. 19A, the read operation when the second multi-value row address is selected is two read operations Read01 and Read10 in steps S31 and S32.

  FIG. 21 shows the timing of the read Read01. Except for the fact that the selected word line potential is Vr01, it is the same as the above-mentioned read Read00, and therefore detailed description is omitted. After the read Read01, the read data is held in the latch circuit 1. Subsequently, read Read10 is performed. The timing of this read Read10 is shown in FIG.

  Reading is performed with the selected word line potential set to Vr10 (see FIG. 43B), and from the bit line precharge to time S9 is substantially the same as the read Read10. However, unlike Read 00 and Read 01, COMRST is set to “H” and the node COM is held at the “L” level. In Read00 and Read01, the potential of the node N3 is not related to the read operation, but in Read10, the potential of the node N3 affects the operation. In Read10 performed after Read01, the read data in Read01 is held in the latch circuit 1 until time S4.

  Until time S2, the node N3 is charged to a voltage of Vdd + α and is in a floating state. When DTG becomes Vdd at time S2, if the node N1 of the latch circuit 1 is “H”, the node N3 holds Vdd + α. If the node N1 is “L”, the potential of the node N3 is discharged to 0V. It becomes. After the bit line potential is amplified at time S7, when REG becomes "H" level at time S9, if "H" is latched at node N1 at Read01, N3 is at "H" level, so the MOS transistor 44 is turned on, the nodes N1 and N4 are discharged to the node COM side, and "L" is taken into the node N1 at time S12. That is, when the memory cell is in the “01” state of FIG. 43B, “L” as “1” data is latched to N1.

  When “L” is latched at the node N1 in the read Read01, the NMOS transistor 44 is not turned on and the nodes N1 and N4 are not discharged at time S9, so that the potential of the node N1 obtained by amplifying the bit line potential is set at time S11. , Sense and latch in S12. When Read01 and Read10 are completed, the data read out for the second multi-value row address is held in the latch circuit 1, and this is stored in the latch circuit 2 at the timing shown in FIG. The data is transferred (step S33), the data output from the latch circuit 2 to the outside is made possible, and the process is terminated.

  The states during reading in the above multi-value operation mode are shown in FIGS. FIG. 38 shows the upper bit reading operation, and FIGS. 39 to 41 show the lower bit reading. 40 and 41 show the second lower bit read operation when the node N1 of the first lower bit read result is “H” and “L”, respectively.

  Next, a description will be given of the case where the latch circuit 2 is used as a cache in order to improve the effective write speed. The relationship between the Vt distribution of the memory cell and the data at this time is as shown in FIG. At the time of reading, since only one reading operation is required, reading is performed by the same control as the above-described read Read00 except that the selected word line voltage is set to Vr0 in FIG.

  FIG. 24 shows a timing chart of a read operation using a cache. FIG. 24A shows a read operation with only one array. First, after receiving a read command 00H and inputting a first row address, Ready // Busy (hereinafter referred to as R / BB) is set to “L”, that is, a busy state is output, and “page read 1” is performed. This page read 1 is a read operation similar to the above-described read Read00. When page read 1 is completed, 512-byte data corresponding to the read first row address is held in the latch circuit 1 of each page buffer. Is transferred to the latch circuit 2.

  After that, when R / BB is set to “H”, that is, ready state, the read enable signal ReadEnableB enables serial data output, and the data corresponding to the first row address is synchronized with the ReadEnable signal. Is output. Internally, the second row address is selected and “page read 2” is executed. At this time, the internal R / BB becomes “L”, that is, Busy.

  If the serial data output 1 from the latch circuit 2 does not end, the data of the latch circuit 1 as a result of the page read 2 cannot be transferred to the latch circuit 2. Therefore, the end of the serial output 1 is detected and R / BB is set to “L”. "In other words, the data is transferred from the latch circuit 1 to the latch circuit 2 in the Busy state. When the data transfer is completed, R / BB is set to “H” again, that is, Ready to start serial data output 2, and the third row address is selected and “page read 3” is executed internally. .

  Since the read operation of the second row address is performed while data corresponding to the first row address is being output by this read operation, the time tdb between the serial data output 1 and the serial data output 2 can be shortened. If the capacity of one page is 512 bytes, the page read time is 10 us, and the serial data output cycle is 50 ns, the conventional effective read speed is 14 MByte / s. On the other hand, according to this embodiment, for example, when tdb = 1 us, the maximum effective reading speed can be increased to 19 MByte / s.

  Here, R / BB is a Ready // Busy signal for determining whether or not the user who uses the flash EEPROM can input / output data. The internal R / BB shown in FIG. This means that the control circuit 110 shown in the block diagram 1 is a flag signal for determining operation control. The same applies to the operation described later.

  FIG. 24B shows a case where two arrays are simultaneously read in a two-array configuration. After inputting the read command 00H and the address, the cell array 100a performs “page read 1” for the input first row address. Similarly, in the cell array 100b, “page reading 2” is performed on the first row address. In this case, two pages are selected for the first row address, and the page capacity appears to be doubled outside the chip. Similarly to FIG. 24A, R / BB is “L”, that is, Busy until each reading is completed and data is transferred.

  In this case, at the time of data output, “data output 1” of the cell array 100a and “data output 2” of the cell array 100b are sequentially performed. When data output starts, the second row address is selected, and “page read 3” is performed in the cell array 100a, and “page read 4” is performed in the cell array 100b. In this case as well, when the effective read speed is compared with tdb = 1 us, the conventional value is 17 MByte / s, but can be improved to 20 MByte / s at the maximum.

  Next, a write operation using a cache will be described with reference to FIG. Here, a case where data is simultaneously written in the cell arrays 100a and 100b as shown in FIG.

  After the data input command 80H and address input, first, write data (Data1) corresponding to the first row address is input to the cell array 100a ("Load1"), and then similarly to the cell array 100b, 80H is input. After the address input, write data input corresponding to the second row address is performed (“Load 2”). Since writing is performed simultaneously in two cell arrays, 10Hd is a dummy write execution command and does not actually enter the write operation. Further, in order to enable continuous data loading “Load3” and “Load4”, the R / BB outputs a Busy signal “L” and immediately outputs a pseudo Ready signal “H”. After the first data input command 80H, the latch circuit 2 serving as a cache is reset in all page buffers (C.Rst in the figure).

  The PMOS transistor 82 in FIG. 2 is a transistor for resetting the latch circuit 2 at this time. With the write execution command 10Hc after the data load “Load2”, writing is simultaneously started in the two cell arrays. Here, data is transferred from the latch circuit 2 of each page buffer to the latch circuit 1, and then the above-described write pulse application operation and write verify read are performed.

  The data transfer is executed at the timing shown in FIG. 10A, the write pulse application operation is executed at the timing shown in FIG. 11, and the write verify read is performed with the selected word line voltage set to Vv0, as shown in FIG. The verify read is executed at the same timing as Verify 10.

  During this time, since writing is being performed internally, the internal R / BB is in the Busy state “L”. As described above, since all the latch circuits 2 are disconnected from the write pulse application operation after data transfer, a pseudo Ready state “H” is output to the R / BB. The data load to the latch circuit 2 is made possible.

  When the write execution command 10Hc is input again after the data load “Load4”, if the simultaneous writing of Data1 and Data2 is not completed at this time, the data of Data3 and Data4 held in the latch circuit 2 at this time is stored. Since data cannot be transferred to the latch circuit 1, the data transfer is performed after the writing of Data1 and Data2 is completed and the internal R / BB becomes Ready “H”. Then, writing of Data3 and Data4 is executed, and Ready “H” is output to the external R / BB to enable data loading to the latch circuit 2 again.

  Further, as described in the case of reading, the configuration may be such that one page is selected for each row address in two or more arrays. The write operation using the cache in that case is shown in FIG. Following the data load Load1 of the cell array 100a, the data load Load1 of the cell array 100b is executed. In this case, the write operation of Data1 and Data2 is started internally by the write execution command 10Hc, and the next data load is enabled externally. FIG. 25C shows a write operation when a cache is used in one array configuration. Also in this case, the command 10Hc is controlled to enable execution of internal write operation and external data load. In the cases of (b) and (c), as in (a), the data loaded into the cache (latch circuit 2) can be transferred to the latch circuit 1 after the internal R / BB is in the Ready state. .

  The effective writing speed is as follows. Assuming that the serial data input cycle is 50 ns, 512 bytes for one page, and 200 us for the time for completing writing for one page, even if simultaneous writing is performed in a 2-array configuration, 4.1 MByte / s. is there. On the other hand, when a cache is used as in this embodiment, the data load time for two pages is hidden behind the writing time and cannot be seen, so it is 5.1 MByte / s. Further, in the case of simultaneous writing in a 4-array configuration, the effect is very large at 10 MByte / s compared to the conventional 6.8 MByte / s.

  The page buffer of FIG. 2 not only enables multi-value operation in this way, but also can realize a cache function that improves the effective write speed and read speed in the binary operation. In the configuration of FIG. 2, if the latch circuit 2 and the NMOS transistor 30 are omitted, the configuration is almost the same as that of the page buffer for binary operation. The PMOS transistor 90 and the NMOS transistor 91 connected to the node COM may be shared by a plurality of page buffers, for example, one by eight page buffers having the same number of I / Os. Therefore, this circuit realizes a multi-value operation and a cache function by a very simple method. In addition, since the multi-value operation and the cache function are supported with the same circuit configuration, both functions can be switched by changing the control of the read and write operations. Since the control is performed by the control circuit 110, a control method and an address space are changed by command input and a multi-value operation function is realized in time, or a cache function is realized at the time of binary operation. Switching is possible.

[Embodiment 2]
In the above-described cache operation, the case of a two-array configuration will be described. The reset of the latch circuit 2 serving as a cache is performed at the time of address input before loading data for two pages. For example, the reset is performed when the address before “Load 1” in FIG. 25 is input and when the address of “Load 3” is input. The latch circuit 2 must be in a reset state before data loading, but a write operation is started after data transfer and the latch circuit 2 is reset after a data load command executed during that time. Then, since the timing at which the data load command is input becomes indefinite, there is a possibility that the reset operation of the latch circuit 2 enters at an arbitrary timing during the write operation. In this case, power supply noise due to the reset operation of the latch circuit 2 may be input during the write verify read sensing operation, which is not preferable.

  Therefore, as shown in FIG. 26, after the data transfer from the latch circuit 2 to the latch circuit 1, the reset operation of the latch circuit 2 may be performed subsequently. That is, the reset operation of the latch circuit 2 is always executed before the write operation. However, since the latch circuit 2 needs to be reset before the first data load, 80H that is entered during the execution of the write operation in relation to the internal R / BB is not reset when the address is input. By doing so, it is possible to eliminate the reset of the latch circuit 2 performed at an indefinite timing during writing.

  FIG. 27 shows a write operation using the cache in this case. In FIG. 27, the case of applying to the case of FIG. 25A is shown, but the same control is possible also in the case of FIGS. 25B and 25C. After data load “Load1” and “Load2” for two pages, the simultaneous write operation of two pages is started, the data transfer from the latch circuit 2 to the latch circuit 1 and the reset (C.Rst) of the latch circuit 2 are finished. Now, R / BB is set to a pseudo ready state “H”. Even if the timing t1 of the data load command during writing of Data1 and Data2 and the subsequent t2 change that can be accepted, the latch circuit 2 can always be reset only before the writing operation. Therefore, unnecessary power supply noise can be reduced in writing using a cache.

[Embodiment 3]
In the first embodiment, the rewrite / read circuit (page buffer) 140 in FIG. 2 switches between multi-value operation for storing 2-bit logical data in one nonvolatile memory cell and cache operation in the case of binary operation. Explained that it is possible. However, even during the multi-level operation, a cache operation using the latch circuit 2 is possible during a period when the latch circuit 2 is not used.

  For example, the latch circuit 2 is not used in the read operation in the multilevel operation mode. Therefore, as shown in FIG. 28A, data can be output from the latch circuit 2 while the main rewrite / read circuit including the latch circuit 1 is connected to the selected bit line and performing a read operation. It is. Similarly, the latch circuit 2 is not used in the write operation when the second multi-value row address is selected in the multi-value operation mode. Therefore, as shown in FIG. 28B, the next write data can be loaded into the latch circuit 2 during writing. However, in writing at the time of selecting the first multi-value row address, the data at the time of selecting the second multi-value row address is read to the latch circuit 2 by the internal data load described above, and the write operation is performed while holding it. The cache function cannot be used.

  FIG. 29 shows a write operation using the cache in the multi-value operation mode described above. In the figure, “lower data” means write data corresponding to the second multi-value row address, and “upper data” means write data corresponding to the first multi-value row address. ing.

  In FIG. 29, first, lower data 1 and lower data 2 which are write data corresponding to the second multi-value row address are sequentially input in the data loads “Load 1” and “Load 2”. When the first write execution command 10Hc is input, data is transferred from the latch circuit 2 to the latch circuit 1 simultaneously in two arrays, and a write operation corresponding to the second multi-value row address is executed internally. Meanwhile, the next data load “Load3”, “Load4” is performed. In FIG. 29, in these data loads, upper data 1 and upper data 2 which are write data corresponding to the first multi-value row address are input.

  When the write operation corresponding to the previous second multi-value row address is completed, the write data corresponding to the first multi-value row address is transferred from the latch circuit 2 to the latch circuit 1 and writing is started. In the writing corresponding to the first multi-value row address, although not shown in FIG. 29, the data corresponding to the second multi-value row address is stored in the memory cell in the latch circuit 2 by the internal data load described above. Is read and held. Therefore, the next data load cannot be performed until the writing of the upper bits (when the first multi-value row address is selected) is completed. Therefore, in this case, when continuous writing is performed, the cache function may or may not be used depending on the row address to be written, but half the data load time can be omitted by the cache operation.

  Since the write time in the multi-level operation mode is long, the effect is small as compared with the normal binary operation mode in which 1-bit logic data is stored in one nonvolatile memory cell, but half the data is also obtained in this embodiment. Since the load time can be omitted, the effective writing speed is improved.

[Embodiment 4]
FIG. 30 shows a rewrite / read circuit 140 according to an embodiment in which the connection state of the latch circuit 2 serving as a cache is different from that in FIG. In this case, the NMOS transistor 31 as a switch element is interposed between the node N1 of the first latch circuit 1 and the node N5 of the second latch circuit 2.

  In such a connection, there is no multi-value operation function, but the above-described cache function can be realized. When data is transferred between the latch circuit 1 and the latch circuit 2, the MOS transistor 31 may be controlled to be in a conductive state capable of transferring “L” level and “H” level. The cache function is the same as that described above.

[Embodiment 5]
In the NAND flash EEPROM, the write pulse application operation and the write verify read are repeatedly executed until all 512-byte cells in the page can be written. The voltage waveform applied to the selected word line shown in FIG. 14 indicates step-up pulse writing in which the write voltage Vpgm is gradually increased while the write pulse application operation and the write verify cycle are repeated. This operation is automatically executed by the control circuit. However, by setting the page buffer 140 as shown in FIG. 2, it is possible to interrupt the operation halfway and measure the cell current at that time.

  As described above, the write verify operation in the binary operation is controlled by the main rewrite / read circuit unit 10, and the data after the write verify read is held in the latch circuit 1. Therefore, after one write pulse application operation and the write verify read cycle are completed, the normal write control for executing the next write pulse application operation is interrupted according to the verify result, and the latch circuit 1 during writing is interrupted. A test operation that measures cell current is possible without destroying data.

  When measuring the cell current, the BLCD is set to “L” to hold the switch element 42 in the non-conductive state, the latch circuit 1 data is held, CSEN and CLAT are set to “L”, and CSENB and CLATB are set to “H” at the same time. Thus, the latch circuit 2 is deactivated, all the transfer switches from the selected bit line to the data line io, that is, the bit line selection transistor 60, the transfer transistors 41 and 30, and the column gate transistor 51 are made conductive, and the data signal line The external data input / output terminals are also made conductive from io. In this way, the cell current can be measured from the external data input / output terminal.

This operation is shown in FIG. 31 (b) in correspondence with FIG. 31 (a) in the case of the conventional method. Even in the conventional test mode, there are a write voltage setting, an operation mode in which only writing is performed, a cell current measurement mode, and the like, and similar operations are possible as shown in FIG. However, conventionally, when the cell current measurement mode is turned on, the data of the latch circuit 1 holding the write verify result is destroyed. Therefore, when the correlation between the determination of the cell current and the verify result is confirmed, the verify is performed. Complicated control is required, such as reading the result from the latch circuit 1, loading the verify result again after the cell current has been read, and performing the next writing. Further, in order to boost the voltage to the voltage set for each write operation, as shown in FIG. 31A, the rising characteristic of the boosting circuit affects the rising characteristic of the selected word line voltage. The applied voltage waveform may also change. On the other hand, in the present embodiment shown in FIG. 31B, the cell current measurement mode can be performed by temporarily interrupting the write cycle while maintaining the verify result during the write. After the cell current measurement is completed, it is possible to resume writing in the next cycle.

[Embodiment 6]
FIG. 46 shows another configuration example of the page buffer 140 for realizing the multi-valued logic operation and the cache function. Unlike the configuration of FIG. 2, in this embodiment, data exchange between the first latch circuit 1 and the second latch circuit 2 is performed between the node N <b> 2 of the first latch circuit 1 and the second latch circuit 2. This is performed by NMOS transistors 203 and 204 interposed in series between the node N6.

  The other end of the clamping NMOS transistor 41b whose one end is connected to the selected bit line is a sense node N4b. The sense node N4b is not directly connected to the node N1 of the first latch circuit 1 as in the case of FIG. 2, but is connected to the gate of the sense NMOS transistor 201. The source of the NMOS transistor 201 is grounded, and the drain is connected to the nodes N1 and N2 of the first latch circuit 1 through the NMOS transistors 202 and 203, respectively.

  That is, the sense NMOS transistor 201 is turned on or off according to the data read to the sense node N4b by the clamp NMOS transistor 41b. The state of the transistor 201 is transferred to the node N1 or N2 via the NMOS transistor 202 or 203 that is selectively activated by the signal BLSEN0 or BLSEN1. As a result, the sense data is read out to the latch circuit 1. Data exchange between the latch circuits 1 and 2 is performed between the nodes N2 and N6 via the NMOS transistors 203 and 204 which are turned on by the signals BLSEN1 and BLSEN2.

  At the time of data writing, the NMOS transistor 42b for transferring the potential of the node N1 to the selected bit line according to the data held in the first latch circuit 1 is arranged on a different path from the clamping NMOS transistor 41b. . The node N5 of the second latch circuit 2 is connected to the sense node N4b through the NMOS transistor 30b. The NMOS transistor 30b is turned on when the selected bit line is precharged in accordance with the data held in the second latch circuit 2 in the multi-level logic operation mode. In addition, a capacitor 48 having one end as a control terminal CAPG is connected to the sense node N4b so that the potential of the sense node N4b can be controlled by capacitive coupling.

  A multi-valued logic operation using this page buffer 140 will be described. For the relationship between the threshold voltage Vt and the data of the memory cell in the multi-valued logic operation, the relationship shown in FIG. Regarding the write operation, the operation flow of the write operation of the first bit (upper bit) and the write operation of the second bit (lower bit) are the same as those in FIG. 9 of the previous embodiment. As for the read operation, as shown in FIG. 47, the second bit read operation is different from FIG. 9 of the previous embodiment. That is, Read 10 that applies Vr10 to the selected word line comes first (step S31 '), and then Read01 that applies Vr01 to the selected word line is executed (step S32'). Other than that, it is the same as FIG.

  Specifically, write and write verify read operations will be described with reference to FIG. First, the lower bit (second bit) will be described. Write data is input from the data input terminal to the second latch circuit 2 via the data signal lines io and ion (S11). Then, as in the previous embodiment, the write data is transferred from the second latch circuit 2 to the first latch circuit 1 (S12).

  At this time, the control signals SEN and LAT of the first latch circuit 1 are set to “H”, SENB and LATB are set to “L”, and the clocked inverters CI1 and CI2 are deactivated, and the control signals BLSEN1 and BLSEN2 are set to “ H ”. As a result, the potential of the node N6 of the latch circuit 2 is transferred to the node N2 of the latch circuit 1 through the NMOS transistors 203 and 204 that are turned on, and then the clocked inverters CI1 and CI2 are activated in this order to transfer the transferred data. Hold. Similarly, when data is transferred from the first latch circuit 1 to the second latch circuit 2, data transfer is performed after the second latch circuit 2 is deactivated.

  Next, a write pulse application operation is performed (S13). In this write pulse application operation, in the case of this page buffer 140, the NMOS transistor 42b is turned on to transfer the data of the node N1 of the first latch circuit 1 to the selected bit line. At this time, in order to transfer the “L” level (0 V) and “H” level (Vdd) of the node N1 without lowering the level, the control signal BLCD applied to the gate of the NMOS transistor 42b has a potential boosted from Vdd. Is preferably used.

  After the write operation, the voltage Vv10 shown in FIG. 43 is applied to the selected word line to perform the write verify read Verify10 (S14). FIG. 48 shows an operation state when there is “L” data in the node N 1 of the first latch circuit 1. Bit line precharging for verify reading is performed by turning on the precharging NMOS transistor 47b and turning on the clamping NMOS transistor 41b. The operation of bit line data sensing using the NMOS transistor 41b is the same as in the previous embodiment.

  The reset operation in FIG. 48 is an operation necessary for a normal read operation, and is an operation for resetting the latch state before the sense data is taken into the latch circuit. This reset operation is not performed in the write verify read operation.

  After the amplified read data potential appears at the node N4b, this is taken into the first latch circuit 1 as binary data by turning on the control signal BLSEN1 and thus turning on the NMOS transistor 203. That is, when the potential of the node N4b is close to Vdd, the sense NMOS transistor 201 is turned on, and the potential of the node N2 is lowered to the “L” level via the NMOS transistors 203 and 201. When the potential of the node N4b is low, the NMOS transistor 201 is not turned on or has a high on-resistance, and the potential of the node N2 of the latch circuit 1 is held.

  The above operation is performed when the first latch circuit 1 is in the active state. In order to ensure that this operation is performed, the transistors are set so that the on-resistances of the NMOS transistors 201, 202, 203, and 204 are sufficiently smaller than those of the PMOS transistors 11, 13, 15, and 17 constituting the latch circuit 1. It is preferable to set the size.

  When the selected cell is read and the threshold value of the memory cell after the application of the write pulse is increased, the bit line is not discharged and the bit line potential is kept at “H”, so that the first latch When “L” is taken into the node N2 of the circuit 1, the writing is completed. On the other hand, when the threshold value of the memory cell is low even after the write pulse is applied, the bit line is discharged, and the node N2 of the latch circuit 1 holds “H” in the verify read. At this time, the application of the write pulse and the verify read are repeated until the node N2 becomes “L”.

  FIG. 49 shows a state when “H” data is present at the node N1 of the first latch circuit 1 (in the case of “1” write, that is, non-write) with respect to FIG. At this time, since the threshold value of the memory cell is not changed by the application of the write pulse, the result of the write verify read can be ignored. The node N2 of the first latch circuit 1 is at the “L” level from the beginning, and there is no state change in the operation of taking the sense data of the bit line into the first latch circuit 1.

  As in the previous embodiment, in the simultaneous writing for one page, in all the page buffers, the write operation is performed until the node N2 of the first latch circuit 1 becomes “L” and the node N1 becomes “H”. The verify read operation is repeated. Then, the writing of all the cells is determined (S15), and the writing is completed.

  Next, the upper bit (first bit) write operation will be described with reference to FIG. In each page buffer, the upper bit data is written to the second latch circuit 2 via the I / O signal line (S21), and then this write data is transferred to the first latch circuit 1 (S22). Next, internal data loading is performed (S23). This internal data load is an operation of reading the lower bit data already written in the memory cell to the second latch circuit 2 as described in the previous embodiment.

  As in the previous embodiment, the data of the first bit and the second bit stored in one memory cell corresponds to the first multi-value row address and the second multi-value row address. . The word lines and memory cells selected by the first multi-value row address and the second multi-value row address are the same.

  FIG. 50 shows the operating state when loading internal data. The second latch circuit 2 is reset between the bit line precharge and the sense of the bit line potential. That is, by turning on the reset NMOS transistor 84, the node N5 is reset to “L” and the node N6 is reset to “H”. Thereafter, the read voltage Vr10 shown in FIG. 43B is applied to the selected word line, and the bit line potential is read to the node N4b. Then, the control signal BLSEN2 is set to “H” to turn on the NMOS transistor 204, whereby the sense result of the node N4b is taken into the second latch circuit 2. If the selected cell is “11”, the node N5 becomes “L”, and if the selected cell is “10”, the node N5 becomes “H”.

  Then, after the write pulse application operation (S24), the write verify read Verify00 for “00” is performed (S25), and then the write verify verify Verify01 for “01” is performed (S26).

  FIG. 51 shows a state change when the operation of writing “0” of the first bit is performed from the cell in the “11” state. Since writing “0”, the node N1 of the first latch circuit 1 at the start of writing is “L”. In the verify read Verify 00, the bit line precharge is performed from the node N5 of the second latch circuit 2. At this time, the NMOS transistor 30b interposed between the node N5 of the second latch circuit 2 and the node N4b on the first latch circuit 1 side is turned on, and the NMOS transistor 41b is further turned on. A boosted potential capable of transferring the “H” level Vdd without lowering the potential is applied to the gate of the transistor 30b, and Vpre is applied to the gate of the transistor 41b to determine the bit line precharge potential during the read operation.

  When the “11” cell is read by the internal data load described above, since the “L” level is held at the node N5, the bit line is precharged to 0V. Therefore, the bit line potential sense result appearing at the node N4b by the verify read Verify 00 is “L”. At this time, even if the NMOS transistor 203 is turned on, the data held in the first latch circuit 1 does not change.

  In the next verify read Verify 01, the bit line precharge is performed by the NMOS transistor 47b. In other words, the node N4b is set to Vdd in the same way as the bit line precharge during normal reading, and the bit line is precharged. In this case, the bit line potential corresponding to the threshold value of the selected cell after application of the write pulse is read to the node N4b. Therefore, when the NMOS transistor 203 is turned on, the verify read result is taken into the first latch circuit 1. In the case of writing from the “11” cell to the “01” cell, if “H” is taken into the node N1 of the first latch circuit 1 in the verify read Verify 01, the writing is completed.

  FIG. 52 shows a state change when a “0” write operation of the first bit is performed from a cell in the “10” state. Since writing “0”, the node N1 of the first latch circuit 1 at the start of writing is “L”. In the verify read Verify 00, the bit line precharge is performed from the node N5 of the second latch circuit 2. At this time, the NMOS transistor 30b interposed between the node N5 of the second latch circuit 2 and the node N4b on the first latch circuit 1 side is turned on, and the NMOS transistor 41b is further turned on. At this time, Vpre is applied to the gate of the transistor 41b as described above.

  Unlike writing from the “11” cell, in the case of the “01” cell, the node N5 is at the “H” level, and the bit line precharge is performed as in the case of normal reading. Thereafter, the bit line potential is read to the node N4b according to the threshold value of the selected cell after the write pulse application operation. This data is taken into the first latch circuit 1 by turning on the NMOS transistor 203.

  In the case of writing from the “10” cell to the “00” cell, if “H” is taken into the node N1 of the first latch circuit 1 in the verify read Verify00, the writing is completed. Subsequently, verify read Verify01 is performed. In this case, as shown in FIG. 43B, the read voltage Vv01 of the selected word line is high. Accordingly, the “00” cell is turned on by this verify reading, the bit line becomes “L” potential, and the sense data appearing at the node N4b becomes “L”. As a result, even if data is taken into the first latch circuit 1, the state does not change. As described above, in the verify read Verify 01, those for which writing has been completed hold “H” at the node N1, and those that have not been completed hold “L” at the node N1.

  FIG. 53 and FIG. 54 show the state change of the operation of “1” write from the “11” cell and the “10” cell, respectively. As in the case of “0” write, after the write pulse is applied, the write verify read Verify00 and Verify01 are sequentially performed. However, the node N1 of the first latch circuit 1 holds the “H” level and the node N2 Holds “L”. Therefore, even when the NMOS transistor 203 is turned on at the time of verify reading, the state of the first latch circuit 1 does not change. Then, until it is determined that the node N1 of all the page buffers becomes “H” (S27), the writing and the verify reading are repeated, and the writing is completed.

  Next, a normal multi-value data read operation using the page buffer 140 of FIG. 46 will be described. FIG. 55 shows a state change during the read operation of the first bit. The read operation of the first bit is a read operation when the first multi-value row address is selected, and the flow is as shown in FIG.

  A read voltage Vr00 shown in FIG. 43B is applied to the selected word line to perform a read operation (S41). At this time, the control signal BLSEN0 is set to “H” to turn on the NMOS transistor 202 between the bit line precharge and the bit line potential sense, and the NMOS transistor 201 is turned on by the precharge transistor 47b. The first latch circuit 1 is reset. In the reset state, the node N1 is “L” and the node N2 is “H”.

  As a result of the bit line data sense, the node N4b becomes “H” or “L”. This is taken into the first latch circuit 1 by setting the control signal BLSEN 1 to “H” and turning on the NMOS transistor 203. When the selected cell is “11” or “10”, the bit line data sense result is that the node N4b is “L”. At this time, the NMOS transistor 201, 203 does not discharge the node N2, and the first latch circuit 1 Node N1 holds “L”. This is read to the outside as “1”.

  On the other hand, when the selected cell is “00” or “01”, the bit line data sense result indicates that the node N4b is “H”. At this time, the node N2 is discharged by the NMOS transistors 201 and 203, and the data of the first latch circuit 1 is inverted, and the node N1 becomes “H”. This is read as “0” to the outside. In the actual data reading to the external input / output terminal, the data of the first latch circuit 1 is transferred to the second latch circuit 2 (S42), and column address selection is performed, so that the column gate transistors 51 and 52 are read. Is done through.

  56 to 58 show state changes at the time of reading the second bit by the flow shown in FIG. The second bit read operation is a read operation when the second multi-value row address is selected. As shown in FIG. 47A, the second read Read10 (S31 ′) and Read01 (S32) are performed twice. '). Among these, the state change at the first read Read10 is shown in FIG.

  In the first read Read10, the read voltage Vr10 shown in FIG. 44B is applied to the selected word line. The operation is the same as the read Read00 described above except for the read voltage of the selected word line. As for the read result, the node N1 of the first latch circuit 1 becomes “L” in the case of the “11” cell, and the node of the first latch circuit 1 in the case of the “10”, “00”, and “10” cells. N1 becomes “H”.

  Next, the second read Read01 is performed by applying the read voltage Vr01 shown in FIG. 43B to the selected word line. FIG. 57 shows the state change when the node N1 of the first latch circuit 1 is “L” (that is, “11”) in the first read in this read operation, and FIG. 58 shows the first change. Is read, the node N1 of the first latch circuit 1 is “H” (that is, “10”, “00”, “10”).

  In the second read read01, the reset operation before the bit line potential sensing is not performed. Accordingly, the read result of the first read Read 10 is held in the first latch circuit 1. Then, the result of bit line data sensing obtained at the node N4b is taken into the first latch circuit 1 by turning on the control signal BLSEN0 and thus turning on the NMOS transistor 202.

  When the selected cell is “11”, since “L” is held in the node N1 of the first latch circuit 1, the node N1 holds “L” regardless of the state of the node N4b (FIG. 57). ). When the selected cell is “10” or “00”, since the selected word line voltage is Vr01, the selected cell is turned on and the sense data of the node N4b becomes “L”. Therefore, the NMOS transistor 201 is in a high resistance state even when it is turned off or on, and the potential of the node N1 does not change even when the NMOS transistor 202 is turned on. That is, the data of the previous read Read00 is held (FIG. 58).

  When the selected cell is “01”, the selected word line voltage Vr01 is not turned on and the bit line is not discharged, so that the node N4b after bit line potential sensing is “H”. Therefore, when the NMOS transistor 201 is turned on and the NMOS transistor 202 is turned on, the node N1 is discharged and pulled down to “L” (FIG. 58).

  As a result, when the second bit is “1”, the node N1 is “L”, and when the second bit is “0”, the data is the first latch circuit 1 so that the node N1 is “H”. Is taken in. Thereafter, the data of the first latch circuit 1 is transferred to the second latch circuit 2 (S33), and the read data is output to the external terminal by selecting the corresponding column address. As described above, the read operation of the multi-valued logic storage is possible.

  In the case of binary storage, as in the previous embodiment, the first latch circuit 2 can be operated as a cache. The rewrite / read circuit 10 including the first latch circuit 1 serves as a main page buffer, and only performs data input / output via the second latch circuit 2 in the binary operation. In the read operation, the same control as read Read00 shown in FIGS. 47B and 55 may be performed by applying a read voltage between the threshold distributions of the binary data to the selected word line. During the write operation, the same control as in FIG.

  As described in the previous embodiment, in the read operation, after the read data is transferred from the first latch circuit 1 to the second latch circuit 2, the main page buffer 10 moves to the next page read. It is possible. In the write operation, after the write data is transferred from the second latch circuit 2 to the first latch circuit 1, the write data of the next page address can be loaded into the second latch circuit 2. As described above, the cache function can be realized.

  In the circuit of the embodiment of FIG. 46, the size of the NMOS transistors 201, 202, 203, 204 used for data inversion of the latch circuit 1 in the active state is important. 46, unlike the circuit of FIG. 2, the “H” and “L” bit line data sense result of the sense node N4b is received by the gate of the NMOS transistor 201. The “H” level at the time of data sensing of the sense node N4b is Vdd, and the “L” level is a potential substantially equal to the potential of the bit line discharged by the on-state cell. The NMOS transistor 201 needs to be turned on in a sufficiently low resistance state when the sense node N4b is at “H” level, and turned off or at least in a sufficiently high resistance state when at the “L” level. In particular, in order to ensure the inversion of the latch data, it is important that the on-resistances of the NMOS transistors 201, 202, and 203 are small.

  However, it is not easy to obtain a sufficient margin only by designing these transistor sizes. As a countermeasure against this point, it is effective to control the potential of the sense node N4b by capacitive coupling using the capacitor 48 shown in FIG. In other words, after precharging the bit line using the transistor 47b and before sensing data, for example, a positive potential is applied to the terminal CAPG to boost the sense node N4b, so that the NMOS at the time of “H” output and “L” output By controlling the potential so that the channel resistance ratio of the transistor 201 is maximized, a large sense margin can be obtained.

  As described above, in the page buffer 140 shown in FIG. 2, the main page buffer 10 including the first latch circuit 1 constitutes a sense amplifier circuit having a latch function for performing bit line data sensing. The NAND flash memory tends to have a large capacity, but its cell current is small due to its memory cell configuration, and high-speed reading is difficult compared to a NOR memory or the like. For this reason, a method is generally used in which data of one page of memory cells (for example, 512 bytes) selected by one selected word line is simultaneously read and the read data is serially transferred and output. In order to apply this method, a 512-byte sense amplifier circuit is arranged for a 512-byte memory cell.

  As a sense amplifier circuit system, as shown in FIG. 2, a clamping transistor 41 is used to perform a bit line potential clamping operation and a pre-sensing operation so that high-speed reading is performed as much as possible. However, since the clamp operation is used, the sense margin of “0” and “1” data is small. In particular, when the power supply voltage is lowered and the circuit threshold value of the latch circuit 1 constituting the sense amplifier circuit is lowered, the sense margin becomes smaller.

  Specifically, description will be made using the sense operation waveform of FIG. At the time of reading, a read voltage is applied to the selected word line of the NAND cell block, and a read pass voltage for using the memory cells connected in series as a pass transistor is applied to the remaining non-selected word lines. Applied. When the bit line is discharged by the selection gate line SGS on the source side of the NAND cell, the drain side selection gate line SGD is always on and the source side selection gate line SGS is off to perform the bit line precharge (time) T0-time T1). That is, the clamping transistor 41 is turned on and the precharging transistor 47 is turned on to perform bit line precharging.

  At this time, as shown in FIG. 59, the potential Vdd + Vtn boosted from the power supply Vdd is applied to the gate terminal BLPRE of the precharging transistor 47, Vdd is applied to the sense node N4, and the gate terminal BLCLAMP of the clamping transistor 41 is provided. Is precharged to Vpre-Vtn by applying Vpre. Here, Vtn is a threshold value of the NMOS transistor.

  After that, when BLCLAMP is returned to 0 V and the source side selection gate is turned on, the bit line is discharged or held without being discharged depending on the data of the selected cell. At time T2, the transistor 42 is turned on, the sense node N4 and the node N1 of the latch circuit 1 are connected, and the node N1 is precharged to Vdd. At time T2, before precharging node N1 to Vdd, SEN and LAT are set to “L” level, and latch circuit 1 is deactivated.

  At time T3, the precharge transistor 47 is turned off and the node N1 is held in a floating state, and the read potential Vsen is applied to the gate terminal BLCLAMP of the clamp transistor 47 during time T4-T5. As a result, when the data of the selected cell is “1”, the bit line potential is lowered by the discharge and is equal to or lower than Vsen−Vtn. The clamping transistor 41 is turned on at the nodes N4 and N1, and the bit line potential is reduced. To fall. On the other hand, when the selected cell is “0” data, since the bit line holds the precharge potential, the clamping transistor 41 is off, and the nodes N1 and N4 hold the precharge potential of Vdd.

  As a result, in the case of the “1” cell, the bit line amplitude Vpre−Vsen is amplified and read as Vdd− (Vsen−Vtn) at the nodes N1 and N4. For example, if the hit line precharge potential is 0.7V, the amplitude of the nodes N1 and N4 is amplified to about 2V when the read amplitude of the bit line is set to about 0.25V.

  After this clamping operation, the potential of the node N1 is taken into the latch circuit 1 as “H” or “L”. In a normal read operation, data is captured by activating the clocked inverter CI2 of the latch circuit 1 at time T7 and then activating the clocked inverter CI1 at time T8.

  From the above description, the “L” level potential (waveform q in FIG. 59) obtained at the nodes N1 and N4 after the bit line potential amplification by the clamping operation must be lower than the circuit threshold value of the latch circuit 1. Conversely, the circuit threshold value of the latch circuit 1 must be higher than the “L” level read to the nodes N1 and N4. Therefore, even when the power supply voltage is lowered and the circuit threshold value of the clocked inverter is lowered, “H”, “ L "level must be set.

  On the other hand, if the bit line precharge potential is too low at the time of reading, the cell current becomes small due to the drain voltage dependence of the cell current, and therefore the reading time becomes long. On the contrary, in order to increase the on-current of the “1” data cell in order to perform high-speed reading, it is limited by the circuit threshold value of the latch circuit 1. Therefore, a sense amplifier circuit system is desired in which the bit line precharge potential and amplitude are not limited by the circuit threshold of the sense amplifier circuit.

  Considering the above circumstances, a preferred embodiment will be described below as a sense amplifier circuit corresponding to the main page buffer 10 of FIG. It should be noted that the sense amplifier circuit described in each of the following embodiments can be applied to the main page buffer of each of the previous embodiments that realizes a multi-valued logic operation and a cache function, and more generally stores binary storage. It is also effective for ordinary NAND flash memories. Furthermore, the present invention is not limited to electrically rewritable non-volatile memories, but can be used as sense amplifier circuits for other non-volatile memories as long as they have memory cells that store data depending on whether or not the current is drawn in the bit line. It is possible to use. Actually, the sense amplifier circuits of the following embodiments will be described by paying attention to the binary data read operation of the NAND flash memory.

[Embodiment 7]
FIG. 60 shows the sense amplifier circuit 141a of such an embodiment corresponding to the page buffer 10 of FIG. The bit line selection switch circuit 141b is for selecting one of the two bit lines BLo and BLe and connecting it to the sense amplifier circuit 141a. The latch circuit 1 composed of the two clocked inverters CI1 and CI2 functions to hold the memory cell data for one page at the same time in a read operation until it is serially transferred and output. The latch circuit 1 holds the write data for each page until the write operation is completed.

  FIG. 61 shows the connection relationship between the sense amplifier circuit 141a and the cell array in the case of specifically storing binary data. The sense amplifier circuit (B / P) 141a for one page is connected to the bit line BLo or BLe via the selection switch circuit 141b. The cell array shows two NAND cell blocks 101 and 102 in the figure. The sense amplifier circuit 141 a is connected to the data input / output buffer 50 through the column gate 150. The read data held in the sense amplifier circuit 141a is converted into serial data by the column gate 150 switched by the column address, and is taken out.

  In the sense amplifier circuit 141a, the sense node N4 is connected to the selected bit line via the clamp NMOS transistor 41, the precharge NMOS transistor 47 is provided in the sense node N4, and the sense node N4 and the latch circuit The transfer NMOS transistor 42 is provided between one node N1 (which is the input terminal of the clocked inverter CI2) as in the case of FIG. The verify circuit 20 is a circuit used at the time of write verify, and corresponds to the transistors 44, 45, and 46 and the capacitor 49 in FIG.

  In this embodiment, a capacitor 31 is connected to the data sense node N4, and a terminal BOOST2 of the capacitor 31 is used as a drive terminal for controlling the potential of the sense node N4 by capacitive coupling during data sensing. .

  FIG. 62 shows the operation waveform at the time of data sensing of the sense amplifier circuit 141a of FIG. 60 corresponding to FIG. First, as usual, at time T0, Vdd + Vtn is applied to the gate BLPRE of the precharging transistor 47, and Vpre is simultaneously applied to the gate BLCLAMP of the clamping transistor 41 to precharge the bit line from the sense amplifier circuit 141a. At this time, the transistor 42 is off, and the latch circuit 1 is held in an active state. By this precharge operation, the sense node N4 in the sense amplifier circuit 141a is set to Vdd, and the bit line is set to Vpre-Vtn.

  Next, at time T2, the clamping transistor 41 is turned off, the selection gate of the NAND cell is turned on, and the bit line is discharged according to the data of the selected cell. After starting the bit line discharge, Vdd + Vtn is applied to the gate BLCD of the NMOS transistor 42 at time T2 to turn it on. Further, SEN and LAT are set to “L” level to make the latch circuit 1 inactive. Thereby, the node N1 is charged from the node N4 to Vdd. At time T3, BLPRE is set to 0V, the precharging transistor 47 is turned off, and at the same time, the terminal BOOST2 of the capacitor 48c is raised from the first potential to the second potential. Specifically, for example, the voltage is increased from 0V to 1V.

  At this time, since the node N4 is in a floating state, the potential of the node N4 rises due to capacitive coupling. The rise in potential at node N4 is determined by the capacitance ratio between capacitor 48c and node N4. Since the gate BLCD of the transistor 42 is Vdd + Vtn, the node N1 can only rise to Vdd, and there is no potential rise due to capacitive coupling. The capacitor 48c is conventionally used to exclude the influence of leakage current and parasitic capacitance when the node N4 is held in a floating state, but this is not used for boosting.

  Thereafter, at time T4, Vsen is applied to the gate BLCLAMP of the clamping transistor 41 to connect the selected bit line and the sense node N4. In FIG. 62, several cases (a) to (d) of the potential change of the node N4 at this time are shown corresponding to the bit line potential change according to the data of the selected cell. Case (a) is a case where the selected cell is in a data “0” state having a sufficiently high threshold. At this time, since the bit line potential almost holds the precharge potential, the clamping transistor 41 does not conduct, and the node N4 holds the boosted potential.

  Case (d) is a case where the selected cell is data “1” and the threshold value is extremely low. At this time, since the bit line is connected to the node N4 in a state where the bit line is discharged to approximately 0V, the node N4 is discharged to approximately 0V which is the same as the bit line. Case (c) is a case where the selected cell is “1” but the threshold is high. In this case, the discharge of the bit line is slow, and the node N4 has an intermediate potential substantially the same as that of the bit line. Case (b) is a case where the selected cell is “0”, but the threshold is close to the selected word line potential and a subthreshold current flows. In this case, the bit line potential slightly decreases and the node N4 also slightly decreases.

  Thus, unlike the conventional method, the operation at time T4 is to perform bit line potential amplification with the node N4 at a high potential. At time T5, the gate BLCLAMP of the clamping transistor 41 is changed to Vsup that is slightly lower than Vsen. This voltage Vsup is lower than Vsen and higher than the threshold value, and the clamping transistor 41 is made conductive near 0V. As a result, the node N4 and the bit line are not conducted unless the bit line potential is lower than when Vsen is applied.

  At time T6, the capacitor terminal BOOST2 is returned to 0V. Since the gate voltage of the clamping transistor 41 is lowered, it is difficult for the node N4 and the bit line to be electrically connected. Therefore, the node N4 is likely to float. For this reason, in the cases of (a), (b), and (c), the potential of the node N4 decreases as the potential of the BOOST2 falls. On the other hand, in the case of (d) in which the node N4 becomes substantially 0 V after the time T4, if the node N4 is floating, the voltage drops to a negative potential, but current flows from the bit line due to the conduction of the clamping transistor 41. The decrease to the negative potential is suppressed. This is possible because the capacitance of the capacitor 48c is smaller than the bit line capacitance.

  As described above, in the case of reading “0” data as shown in (a), the potential of the node N1 returns to Vdd before boosting by the capacitor 41. On the other hand, in the case of a “1” cell having a slow bit line discharge as shown in (c), the potential of the node N1 can be lowered than the bit line potential. That is, in the sense amplifier circuit of this embodiment, it is equivalent to not only amplifying the node N1 to the high potential side but also the low potential side with respect to the bit line amplitude. The difference in “L” is large.

  At time T7, the gate BLCLAMP of the clamping transistor 41 is set to 0 V, and the bit line and the node N4 are completely disconnected. Thereafter, the clocked inverter CI2 is activated at time T9, and then the clocked inverter CI1 is activated at time T10. As a result, the binary data by “H” and “L” of the node N1 is taken into the latch circuit 1.

  In FIG. 62, the range of the circuit threshold value (inversion threshold value) of the CMOS clocked inverter of the latch circuit 1 is shown in consideration of the power supply Vdd and process variations. In the case of this embodiment, the bit line data sense by the clamping operation is performed in a state where the potential of the node N4 is boosted using the capacitor 48c, and then the node N4 is stepped down to thereby decrease the node when the “1” cell is read. Since the “L” level of N4 is shifted to a potential lower than the bit line level, even if the “L” level of the bit line potential is higher than the circuit threshold value, there is no erroneous reading and a normal reading operation can be performed. In order to increase the set value of the “H” level precharge potential or “L” read potential of the bit line, the potential amplitude applied to the capacitor 48c may be increased.

  The gate BLCD of the transistor 42 between the nodes N4 and N1 is set to Vdd + Vtn, and only the node N4 among the nodes N1 and N4 is boosted. The node N1 has a drain of the PMOS transistor 13 of the latch circuit 1. Because is connected. That is, when the node N1 is boosted at the same time as the node N4, the pn junction of the PMOS transistor becomes a forward bias, and the node N4 is not boosted. This is prevented. At this time, the voltage applied to the gate BLCD of the transistor 42 may not be Vdd + Vtn, but may be any gate voltage that can transfer a voltage higher than the circuit threshold of the clocked inverter and lower than Vdd.

  The control signal REG at time T8 in FIG. 62 is used in a read operation such as write verify, and is a gate control signal for the transistor 43 between the verify circuit 20 and the node N4 in FIG. That is, in the NAND flash memory, data is written in units of pages, but the write pulse application operation and the write verify read are repeated several times in order to keep the threshold range of the write data within a predetermined range. Then, for each bit for which writing has been completed, data is set so as to be in a non-written state in the next write pulse application operation.

  Specifically, in the “0” data write, the bit line precharge is performed at the “L” level of the node N1, and if “0” write (electron injection to the floating gate) is sufficient, the bit can be verified read. The node N1 becomes “H”. That is, after that, the write is prohibited. If the “0” write is insufficient, the node N1 becomes “L” by the verify read, and the “0” write is performed again for this bit.

  On the other hand, in the bit for writing “1” data (that is, writing is prohibited), the bit line precharge is performed at the “H” level of the node N1, and when the cell data is “1”, it is held as it is. At this time, the node N1 becomes “L” by the verify reading, and therefore, if the next writing is performed by performing the bit line precharge in this state, the writing becomes “0”. Therefore, in this case, it is necessary to invert the read data of the node N4 to “H” in the non-write state by the verify read operation. In this manner, the verify circuit 20 controls the data of the nodes N1 and N2 during the write verify read. That is, only when the data of the node N1 at the time of applying the write pulse is “H”, when the “H” is applied to the gate REG of the NMOS transistor 43, the nodes N1 and N4 are set to the “H” state. Then, the verify circuit 20 works.

[Embodiment 8]
FIG. 63 shows a sense amplifier circuit 141a according to an embodiment obtained by slightly modifying the circuit of FIG. A difference from FIG. 60 is that a capacitor 48a whose one end is grounded is added in addition to the capacitor 48c for applying a boosted voltage to the sense node N4. The sense amplifier circuit operation is the same as in the case of FIG.

  In this embodiment, when a drive voltage is applied to the terminal BOOST2 of the capacitor 48c to boost the node N4, the capacitance of the node N4 is substantially larger by the capacitor 48a. In order to obtain the above, a higher drive voltage is required than in the previous case. In other words, in the case of this embodiment, the values of the capacitors 48c and 48a are selected even when an intermediate voltage is required as the drive voltage in order to obtain the necessary boosted voltage of the node N4 in the circuit of FIG. Thus, the power supply voltage Vdd can be used. If the voltage amplitude of the capacitor terminal BOOT2 is set to 0 V and Vdd in this manner, it is preferable that the peripheral circuit is not complicated.

[Embodiment 9]
FIG. 64 shows a sense amplifier circuit 141a according to an embodiment obtained by further modifying the circuit of FIG. In this embodiment, a PMOS transistor 82b whose gate is controlled by a control signal PPRE is added to the node N1 as a precharge circuit. Further, in order to hold the charge of the node N1, a capacitor 48b having one end grounded is added to the node N1.

  In the sense amplifier circuit of FIG. 60, Vdd + Vtn is applied to the gate BLCD of the transistor 42 in order to prevent the node N1 from being boosted when boosting the node N4 by controlling the capacitor terminal BOOST2. If this voltage is not set with high accuracy, the pn junction of the PMOS transistor of the latch circuit 1 becomes forward bias, and the node N4 cannot be boosted. Therefore, it is necessary to set the voltage of the gate BLCD so that the node N1 is equal to or lower than Vdd and higher than the circuit threshold value of the latch circuit 1.

  In the embodiment of FIG. 64, the node N1 can be precharged independently of the node N4 in order to make the control of the transistor 42 easier. In this case, the voltage of the gate BLCD of the transistor 42 may be any voltage as long as the bit line and the node N4 are connected by the clamping operation and the read voltage obtained at the node N4 can be transferred to the node N1. Good. For example, the power supply voltage Vdd may be applied at a predetermined timing.

  FIG. 65 shows operation waveforms of the sense amplifier circuit of this embodiment. The bit line precharge operation from time T0 to time T1 is the same as that of the circuit of FIG. At time T2, the control terminal PPRE is set to “L” (Vss), and the node N1 is precharged to Vdd by the transistor 82b. At this time, the BLCD is “L”, and the node N1 is precharged independently of the node N4. At time T3, the BLCD is set to a voltage equal to or higher than Vsen, for example, Vdd. When the BLCD and the nodes N1 and N4 are all at Vdd, the NMOS transistor 42 is off. In this state, the node N4 is boosted by BOOST2.

  In the case of FIG. 64, the two capacitors 48c and 48a are used as the booster circuit of the node N4 as in FIG. 63, but only one capacitor 48c may be used as in FIG.

  At time T4, the precharge control signal PPRE is set to “H”, the precharge operation of the node N1 is stopped, and the node N1 is brought into a floating state. This improves the cutoff of the NMOS transistor 42, so that the node N4 can be boosted stably. However, as described above, there are cases where the nodes N4 and N1 are discharged to “L” and then charged to “H” again, as in the verify reading after writing “0”. Therefore, before the activation of the latch circuit 1, the gate BLCD of the transistor 42 is raised to Vdd + Vtn at time T8.

[Embodiment 10]
FIG. 66 shows a sense amplifier circuit 141a according to still another embodiment. In this embodiment, the boost control of the node N4 is not performed. Capacitors 48a and 48b, each of which is grounded, are connected to nodes N4 and N1, and a reset NMOS transistor 82c is provided at node N1.

  FIG. 67 shows operation waveforms in this embodiment. In this embodiment, bit line data sensing by bit line precharging and clamping is performed without boosting the sense node N4. During this time, the BLCD is set to 0 V, and the node N4 and the bit line are connected by a clamping operation with the transistor 42 turned off. After the bit line potential appears at the node N4, Vdd + Vtn is applied to the BLCD at time T5. Until this time T5, the reset signal NRST is set to “H” and the node N1 is reset to 0V.

  When such control is performed, the transistor 42 is turned on, whereby the charge held in the capacitor 48a at the node N4 is distributed to the capacitor 48b at the node N1. Thereby, as shown in FIG. 67, the potential of the node N4 decreases and the potential of the node N1 increases. Therefore, even when the “L” level of the bit line data read to the node N4 is higher than the circuit threshold value of the latch circuit 1, it can be captured as “L”.

  The operation control of the sense amplifier circuit of this embodiment is simpler than the circuits of FIG. 60, FIG. 63, and FIG. However, when the “H” level potential of the node N1 determined by the charge distribution from the node N4 is too low at time T5 and becomes lower than the circuit threshold value of the latch circuit 1, “0” reading cannot be performed. Therefore, the degree of freedom in setting the bit line potential at the time of reading is smaller than that of the circuits of FIGS.

[Embodiment 11]
FIG. 68 shows a sense amplifier circuit 141a according to still another embodiment. In the circuits of FIGS. 60, 63, 64, and 66, the data of the sense node N4 is directly transferred to the node N1 of the latch circuit 1 through the transistor 42. In this embodiment, the data of the node N4 is transferred. A sense NMOS transistor 70 that receives data at the gate is used. The source of the transistor 70 is grounded, and the drain is connected to the nodes N2 and N1 of the latch circuit 1 via switching NMOS transistors 71 and 72, respectively.

  The NMOS transistor 42 for transferring the data of the node N1 of the latch circuit 1 to the bit line at the time of data writing is provided on a different path from the clamping transistor 41. This sense amplifier circuit system is the same as that of FIG. In the circuit of this embodiment, a boosting capacitor 48c having one end BOOST2 as a drive terminal is connected to the sense node N4, as in the circuit of FIG.

  A normal data read operation of the sense amplifier circuit 141a according to this embodiment will be described with reference to operation waveforms of FIG. At time T0, Vdd + Vtn is applied to the gate BLPRE of the precharging transistor 47, Vpre is applied to the gate BLCLAMP of the clamping transistor 41, and the selected bit line is precharged to Vpre−Vtn. At this time, since the node N4 becomes Vdd, when the control signal BLSEN0 is simultaneously set to Vdd, the node N1 of the latch circuit 1 is reset to “H” and the node N2 is reset to “L”.

  When the bit line precharge operation is terminated at time T1 and the selection gate of the NAND cell block is turned on, the bit line is discharged or held without being discharged depending on the data state of the selected cell. Until the time T2, the precharge transistor 47 is kept on and then turned off. When the BOOST2 is increased by about 1 V at the time T3, the node N4 is boosted by capacitive coupling.

  Then, when the gate BLCLAMP of the clamping transistor 41 is set to Vsen at time T4, reading is performed with the amplitude of Vpre−Vsen on the bit line side. At this time, the node N4 shows potential changes as shown in (a) to (d) in correspondence with FIG. 62 in accordance with the threshold state of the cell. That is, the bit line amplitude is amplified by the clamping transistor 41 and output to the node N4.

  In the cases (a) and (b), the transistor 70 is turned on, and in the cases (c) and (d), the transistor 70 is turned off. At time T5, when the control signal BLSEN1 is set to Vdd and the transistor 71 is turned on, in the case of (a) and (b), the latch circuit 1 inverts the node N2 to “L”, and (c) and (d) In this case, the node N2 holds the “H” state.

  In the case of this sense amplifier circuit system, the size of the transistors 70, 71, 72 tends to increase in order to perform the operation of forcibly inverting the latch circuit. However, in the case of this embodiment, since the node N4 is boosted during data sensing, these transistor dimensions can be reduced.

  In the operation of FIG. 69, data is fetched into the latch circuit 1 while the node N4 is boosted, but after the boosted state of the node N4 is released, as in the embodiment of FIG. Data may be taken into the latch circuit 1. Similarly to the embodiment of FIG. 63, a capacitor having one end grounded may be added to the node N4 in addition to the boosting capacitor.

  FIG. 70 shows a configuration example of capacitors 48c, 48a, 48b used in the embodiment shown in FIG. FIG. 70A shows a MOS capacitor using a D-type NMOS transistor. The gate is connected to nodes N4, N1, and the like, and the drain and source are connected in common to form a BOOST2 terminal (or ground terminal). In this case, it is desirable that the transistor be kept on even when BOOST2 is raised from 0V to a positive voltage.

  FIG. 70B shows an example in which a capacitor is configured between the first layer polycrystalline silicon 515 (1 poly) and the second layer polycrystalline silicon 514 (2 poly). Since a stacked gate structure is usually used for a nonvolatile memory cell, it is easy to build such a capacitor when using a nonvolatile memory cell.

  FIG. 70C shows an example in which a capacitor is configured between an n-type well 517 and an electrode 515 formed thereon via an insulating film. An n + -type diffusion layer 516 is formed in the n-type well 517, and this is connected to the BOOST2 terminal. In order to obtain a stable capacitance regardless of the potential of BOOST2, it is preferable to form an n-type layer 518 having a higher concentration on the surface of the n-type well 517.

1 shows a block configuration of a NAND flash EEPROM according to an embodiment of the present invention. 2 shows a configuration of a rewrite / read circuit according to the embodiment. 2 shows a configuration of a memory cell array and a rewrite / read circuit according to the embodiment. An operation mode of the rewrite / read circuit according to the embodiment is shown. The other operation | movement aspect of the rewriting / reading circuit of the embodiment is shown. The other operation | movement aspect of the rewriting / reading circuit of the embodiment is shown. The other operation | movement aspect of the rewriting / reading circuit of the embodiment is shown. The other operation | movement aspect of the rewriting / reading circuit of the embodiment is shown. The flow of data writing in the multilevel logic operation of the embodiment is shown. The timing of data transfer between the latch circuits in the multilevel logic operation of the embodiment is shown. The timing of the data write operation of the embodiment is shown. Operation modes of erasing and writing in the memory cell of the same embodiment are shown. The timing of the verify read operation of the same embodiment is shown. The write voltage waveform of the same embodiment is shown. The operation mode of the rewrite / read circuit of the same embodiment is shown. The operation timing of internal data loading of the embodiment is shown. The operation timing of verify read Verify00 of the same embodiment is shown. The operation timing of verify read Verify 01 of the embodiment is shown. The read operation flow of the multi-value operation of the same embodiment is shown. The operation timing of the read Read00 of the same embodiment is shown. The operation timing of read Read01 of the embodiment is shown. The operation timing of the read Read 10 of the same embodiment is shown. The memory cell threshold distribution in the case of binary operation is shown. It is a figure which shows the read-out operation | movement using the cache of the embodiment. It is a figure which shows the write-in operation | movement using the cache of the embodiment. The timing of the data transfer operation of the latch circuit in the write operation is shown. It is a figure which shows the other write-in operation | movement using the cache of other embodiment. The data transfer operation of the cache operation in the multi-value operation is shown. A write operation using a cache in a multi-value operation is shown. 6 shows a configuration of a rewrite / read circuit according to another embodiment. The operation waveforms in the test mode in other embodiments are shown in comparison with the conventional example. The potential relationship of each part at the time of writing the lower bit “0” in the multilevel operation of the embodiment is shown. The potential relationship of each part at the time of writing the lower bit “1” in the multilevel operation of the embodiment is shown. The potential relationship of each part at the time of writing the upper bit “0” in the multilevel operation of the embodiment is shown. The potential relationship of each part at the time of writing the upper bit “1” in the multilevel operation of the embodiment is shown. The potential relationship of each part at the time of writing the upper bit “1” in the multilevel operation of the embodiment is shown. The potential relationship of each part at the time of writing the upper bit “1” in the multilevel operation of the embodiment is shown. FIG. 9 shows the relationship between the potentials of each part at the time of reading upper bits in the multi-value operation of the embodiment. FIG. 9 shows the relationship between the respective potentials of the first part of the lower bit reading in the multi-value operation of the embodiment. FIG. 9 shows the relationship between the respective potentials of the second portion of lower bit reading in the multi-value operation of the embodiment. FIG. FIG. 9 shows the relationship between the respective potentials of the second portion of lower bit reading in the multi-value operation of the embodiment. FIG. 1 shows a conventional multi-value flash memory configuration. The memory cell threshold value distribution of multi-value operation is shown. A state of data loading in a conventional multi-value operation is shown. The relationship between the memory cell array configuration and the page buffer is shown. It is a figure which shows the structure of the rewriting / reading circuit by other embodiment. It is a read operation flow at the time of multi-value logic operation according to the same embodiment. It is a figure which shows the 2nd bit "0" write state of the same multi-value logic operation. It is a figure which shows the 2nd bit "1" write state of the same multi-value logic operation. It is a figure which shows the operation | movement of the internal data load of the same multi-value logic operation. It is a figure which shows the 1st bit "0" write state of the same multi-value logic operation. It is a figure which shows the 1st bit "0" write state of the same multi-value logic operation. It is a figure which shows the 1st bit "1" write state of the same multi-value logic operation. It is a figure which shows the 1st bit "1" write state of the same multi-value logic operation. It is a figure which shows the 1st bit read state of the same multi-value logic operation. It is a figure which shows the 2nd bit read 1st state of the same multi-value logic operation. It is a figure which shows the 2nd bit read second state of the same multi-value logic operation. It is a figure which shows the 2nd bit read second state of the same multi-value logic operation. It is a figure which shows the waveform of data read-out operation | movement. It is a figure which shows embodiment of a preferable sense amplifier circuit. It is a figure which shows the example of application of the same sense amplifier circuit. It is a figure which shows the operation | movement waveform of the same sense amplifier circuit. This is a configuration of a sense amplifier circuit according to another embodiment. This is a configuration of a sense amplifier circuit according to another embodiment. It is a figure which shows the operation | movement waveform of the same sense amplifier circuit. This is a configuration of a sense amplifier circuit according to another embodiment. It is a figure which shows the operation | movement waveform of the same sense amplifier circuit. This is a configuration of a sense amplifier circuit according to another embodiment. It is a figure which shows the operation | movement waveform of the same sense amplifier circuit. It is a structural example of the capacitor used for the sense amplifier circuit of each embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 ... Memory cell array, 120 ... Row decoder, 140 ... Rewrite / read circuit (page buffer), 150 ram decoder, 110 ... Control circuit, 130 ... High voltage generation circuit, 50 ... Data input / output buffer, 170 ... Command register, 180 ... Address register, 190 ... Operation logic control, 200 ... Status register, 210 ... Ready / busy register, 1 ... First latch circuit, 2 ... Second latch circuit, 30, 41, 42, 43, 44 ... Transfer switch Element, 51, 52: Column selection switch element.

Claims (5)

A memory cell array in which electrically rewritable nonvolatile memory cells are arranged;
A plurality of rewrite / read circuits for temporarily storing data to be written to the memory cell array and sensing read data from the memory cell array;
A control circuit for controlling a data rewrite operation and a read operation of the memory cell array,
Each rewrite / read circuit includes a first latch circuit connected to a selected bit line of the memory cell array via a first transfer switch element and a second transfer switch element in series, and the first transfer switch A second latch circuit connected via a third transfer switch element to a connection node between the element and the second transfer switch element, and the data read from the memory cell to the first latch circuit is The data is output from the input / output terminal after being transferred to the second latch circuit, and the data input from the input / output terminal to the second latch circuit is transferred to the first latch circuit and then written to the memory cell. And a data node of the second latch circuit is connected to a data input / output line via a column selection switch ,
The data input / output line is for performing data input / output from the input / output terminal, and is connected only to the second latch circuit of the first latch circuit and the second latch circuit. and has <br/> nonvolatile semiconductor memory device, characterized in that.   A verify read operation for reading and confirming the write data after data is written to a selected memory cell, and data sensing and data holding in the verify read operation are performed by a first latch circuit. Item 12. A nonvolatile semiconductor memory device according to Item 1. In a multi-valued logic operation mode in which 2-bit data is stored in one nonvolatile memory cell , the first transfer switch element and the third transfer switch element are made conductive to connect the second latch circuit and the bit line. 2. The nonvolatile semiconductor memory device according to claim 1, further comprising a write verify operation for performing bit line precharging with data held in the second latch circuit. In the rewrite / read circuit, a common signal line to which a predetermined potential is applied is connected to a connection node between the first transfer switch element and the second transfer switch element via a fourth transfer switch element. The nonvolatile semiconductor memory device according to claim 1. The rewrite / read circuit is inserted between a temporary storage node for temporarily storing the potential of the data node of the first latch circuit, and between the fourth transfer switch element and a common signal line. 5. The nonvolatile semiconductor memory device according to claim 4, further comprising a fifth transfer switch element controlled by the potential of the temporary storage node.

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