JP4233213B2 - MEMORY CONTROLLER, FLASH MEMORY SYSTEM PROVIDED WITH MEMORY CONTROLLER, AND FLASH MEMORY CONTROL METHOD - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a memory controller, a flash memory system, and a flash memory control method, particularly when a corresponding logical address is not correctly written or a value of a corresponding logical address already written has changed for some reason. The present invention relates to a memory controller, a flash memory system, and a flash memory control method that can recognize a correct correspondence between a logical address and a physical address.
[0002]
[Prior art]
In recent years, flash memories, particularly NAND flash memories, are often used as semiconductor memories used for memory cards, silicon disks, and the like. In the NAND flash memory, when a memory cell is changed from an erased state (logical value = 1) to a written state (logical value = 0), this can be performed in units of memory cells. When changing from the written state (0) to the erased state (1), this cannot be performed in units of memory cells, and can be performed only in predetermined erase units composed of a plurality of memory cells. Such a batch erase operation is generally called “block erase”.
[0003]
As described above, in the flash memory, the memory cell can be changed from the written state to the erased state only in units of blocks. Therefore, in order to write new data to a block in which data has already been written, A process is required in which all memory cells included in the block are erased, and then new data is written. Therefore, when writing new data to a block that already contains data, to prevent the data already stored in this block from being lost, move the data contained in this block to another erased block. It is necessary to let
[0004]
Therefore, when the host computer instructs to write new data to a block in which data is already stored, the new data and data already stored in this block are written into the erased block. Such processing is called “inter-block transfer”. Thereafter, all the memory cells included in the transfer source block are erased, so that the transfer source block becomes a new erased block.
[0005]
As described above, in the flash memory, it is necessary to move new data and data not to be overwritten to another block every time the host computer instructs data overwriting. Therefore, the relationship between the logical address given from the host computer and the physical address on the flash memory corresponding to the logical address dynamically changes every time the host computer instructs data overwriting. For this reason, each block needs to store what logical address it is accessed by.
[0006]
Then, in the initialization operation such as when the power is turned on, the corresponding logical address stored in each block is read under the control of the controller, and based on this, the correspondence between the logical address and the physical address is shown. An address translation table is created.
[0007]
[Problems to be solved by the invention]
Thus, since the correspondence between the logical address and the physical address is indicated by the address conversion table created in the initialization operation, the corresponding logical address is not correctly written, or the value of the already written corresponding logical address is If it has changed for some reason, the correct correspondence between the logical address and the physical address becomes unknown. In this case, it is impossible to read the already written user data.
[0008]
The phenomenon that the corresponding logical address is not written correctly or the value of the corresponding logical address that has already been written changes for some reason may be caused by the disturb phenomenon as well as by the presence of a defective cell. It is done. The disturb phenomenon is a phenomenon in which when a memory cell is read or written, the state of another memory cell having a common bit line with the memory cell changes. It is known that the occurrence rate is increased by repeating the write / erase operations.
[0009]
Therefore, even if the corresponding logical address is not written correctly or the value of the already written corresponding logical address has changed for some reason, the correct correspondence between the logical address and the physical address is recognized. A memory controller, a flash memory system, and a flash memory control method that can be used are desired.
[0010]
Therefore, the object of the present invention is to ensure that the logical address and the physical address are correct even if the corresponding logical address is not correctly written or the value of the already written corresponding logical address has changed for some reason. To provide a memory controller, a flash memory system, and a flash memory control method capable of recognizing correspondence.
[0011]
[Means for Solving the Problems]
  An object of the present invention is a memory controller that accesses a memory composed of a plurality of blocks each including a plurality of pages based on a block address and a page address.A host address was specifiedIn response to a request to write user data,Address generating means for generating the block address and the page address based on the host address;Generate additional information corresponding to the block addressAdditional information generationAnd at least for the predetermined plurality of pages without writing the block address and the additional information to a page that is not any of the predetermined plurality of continuous pages including the page specified by the page address and the first page. Write the block address and the additional informationwritingAnd a memory controller comprising the means.
[0012]
According to the present invention, even when the block address is not written correctly or the value of the already written block address has changed for some reason, the block is written on a predetermined number of consecutive pages including the first page. Since the address and additional information are written, a correct block address can be obtained. In addition, since the block address and the additional information are not written to the page specified by the page address and the page that is not any of the predetermined plurality of pages, unnecessary writing time does not occur.
[0013]
In a preferred embodiment of the present invention, the additional information is information capable of detecting an error included in the block address.
[0014]
In a further preferred aspect of the present invention, the predetermined plural pages are at least four consecutive pages.
[0015]
  In a further preferred aspect of the present invention, the block address and the additional information written on the first page are read out.readingDetermining whether or not the read block address contains an error based on the read additional informationError detectionMeans further comprising:Error detectionIn response to determining that the read block address contains an error, the meansreadingMeans reads out the block address and the additional information written in the next page of the first pageIs configured as.
[0016]
  In a further preferred embodiment of the present invention,writingMeans writes the block address and the additional information to the page specified by the page address and the predetermined plurality of pages.Is configured as.
[0017]
  The object of the present invention is also a memory controller for accessing a memory composed of a plurality of blocks each including a plurality of pages based on a host address supplied from a host computer, wherein a logical block address and Generate page addressAddress generationAnd whether or not a physical block address corresponding to the logical block address exists.JudgmentMeans and saidJudgmentIn response to determining that there is no physical block address corresponding to the logical block address by means, a free block is selected from the plurality of blocks.Free block selectionAnd additional information capable of detecting an error in the logical block address.Additional information generationMeans and saidFree block selectionAmong the plurality of pages constituting the empty block selected by the means, the logical block address and the additional information are not included in a page that is not any of a predetermined plurality of continuous pages including the page specified by the page address and the first page. Write the logical block address and the additional information to at least the predetermined plurality of pages without writingwritingAnd a memory controller comprising the means.
[0018]
  In a further preferred aspect of the present invention, an error-free logical block address is specified based on the additional information among the logical block addresses written in the predetermined plurality of pages, and an address conversion table is created based on the specified logical block address.Create tableMeans further comprisingJudgmentMeans makes the determination by referring to the address translation tableIs configured as.
[0019]
  The object of the present invention is also provided with a flash memory composed of a plurality of blocks each including a plurality of pages, and a memory controller that accesses the flash memory based on a host address supplied from a host computer. A block address and a page address are generated based on the host address.Address generationAnd additional information corresponding to the block address is generated in response to the user data write request from the host computer.Additional information generationAnd at least for the predetermined plurality of pages without writing the block address and the additional information to a page that is not any of the predetermined plurality of continuous pages including the page specified by the page address and the first page. Write the block address and the additional informationwritingAnd a flash memory system.
[0020]
  The object of the present invention is also achieved from a host computer.A host address was specifiedIn response to a request to write user data,An address generation step of generating a block address and a page address based on the host address; andGenerate additional information corresponding to block addressAdditional information generationAnd at least the predetermined plurality of pages without writing the block address and the additional information to a page that is not any of the predetermined plurality of continuous pages including the page specified by the page address and the first page. Write the block address and the additional informationwritingAnd a method for controlling a flash memory comprising the steps.
[0021]
  In a preferred embodiment of the invention,The flash memory control method isUntil an error-free block address is obtained for the predetermined plurality of pageswritingRead the block address written in stepreadingMore stepsHaveThe
[0022]
Preferred Embodiment of the Invention
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0023]
FIG. 1 is a block diagram schematically showing a flash memory system 1 according to a preferred embodiment of the present invention.
[0024]
As shown in FIG. 1, the flash memory system 1 has a card shape, and four flash memory chips 2-0 to 2-3, a controller 3, and a connector 4 are integrated in one card. Composed. The flash memory system 1 is used by being detachably attached to the host computer 5 and used as a kind of external storage device for the host computer 5. Examples of the host computer 5 include various information processing apparatuses such as a personal computer and a digital still camera that process various information such as characters, sounds, and image information.
[0025]
Each of the flash memory chips 2-0 to 2-3 is a semiconductor chip having a storage capacity of 128 Mbytes (1 Gbit). In the flash memory system 1, 512 bytes are used as one page, and this is the minimum access unit. Accordingly, each of these flash memory chips 2-0 to 2-3 includes an address space of 256K pages, and the flash memory chips 2-0 to 2-3 have a total of 1M pages of address space. In the flash memory system 1, these four flash memory chips 2-0 to 2-3 have a storage capacity of 512M bytes (4G bits) and are handled as one large memory having an address space of 1M pages. It is. Therefore, in order to access a specific page from the address space consisting of these 1M pages, 20-bit address information is required. Therefore, the host computer 5 accesses a specific page by supplying 20-bit address information to the flash memory system 1. Hereinafter, the 20-bit address information supplied from the host computer 5 to the flash memory system 1 is referred to as a “host address”.
[0026]
The controller 3 includes a microprocessor 6, a host interface block 7, an SRAM work area 8, a buffer 9, a flash memory interface block 10, an ECC (error collection code) block 11, and a flash sequencer block 12. Composed. The controller 3 constituted by these functional blocks is integrated on one semiconductor chip.
[0027]
The microprocessor 6 is a functional block for controlling the operation of the entire functional blocks constituting the controller 3.
[0028]
The host interface block 7 is connected to the connector 4 via the bus 13 and exchanges data, address information, status information, and external command information with the host computer 5 under the control of the microprocessor 6. That is, when the flash memory system 1 is attached to the host computer 5, the flash memory system 1 and the host computer 5 are connected to each other via the bus 13, the connector 4, and the bus 14, and in this state, the host computer 5 The data supplied to the flash memory system 1 is taken into the controller 3 through the host interface block 7 as an entrance, and the data etc. supplied from the controller 3 to the host computer 5 exits the host interface block 7. To the host computer 5. The host interface block 7 further includes a task file register (not shown) for temporarily storing a host address and an external command supplied from the host computer 5 and an error register (not shown) that is set when an error occurs. Z).
[0029]
The SRAM work area 8 is a work area in which data necessary for controlling the flash memory chips 2-0 to 2-3 by the microprocessor 6 is temporarily stored, and includes a plurality of SRAM cells.
[0030]
The buffer 9 is a buffer for temporarily storing data read from the flash memory chips 2-0 to 2-3 and data to be written to the flash memory chips 2-0 to 2-3. That is, data read from the flash memory chips 2-0 to 2-3 is held in the buffer 9 until the host computer 5 can receive the data, and should be written to the flash memory chips 2-0 to 2-3. The data is held in the buffer 9 until the flash memory chips 2-0 to 2-3 are writable and an error correction code is generated by the ECC block 11 described later.
[0031]
The flash memory interface block 10 exchanges data, address information, status information, and internal command information with the flash memory chips 2-0 to 2-3 via the bus 15, and each flash memory chip 2-0. This is a functional block for supplying corresponding chip selection signals # 0 to # 3 to 2-3. The chip selection signals # 0 to # 3 are based on the upper 2 bits of the internal address generated based on the host address supplied from the host computer 5 when data reading or writing is requested from the host computer 5. One of them is a signal to be activated. Specifically, if the upper 2 bits of the internal address are “00”, the chip selection signal # 0 is activated, if it is “01”, the chip selection signal # 1 is activated, and if it is “10”. The chip selection signal # 2 is activated, and if it is “11”, the chip selection signal # 3 is activated. The flash memory chips 2-0 to 2-3 in which the corresponding chip selection signal is activated are in a selected state, and data can be read or written. The “internal command” is a command for the controller 3 to control the flash memory chips 2-0 to 2-3, and is distinguished from an “external command” for the host computer 5 to control the flash memory system 1. Is done.
[0032]
The ECC block 11 generates an error correction code to be added to the data to be written to the flash memory chips 2-0 to 2-3, and based on the error correction code added to the read data, the error included in the read data is corrected. This is a functional block for correction.
[0033]
The flash sequencer block 12 is a functional block for controlling data transfer between the flash memory chips 2-0 to 2-3 and the buffer 9. The flash sequencer block 12 includes a plurality of registers (not shown), and reads data from the flash memory chips 2-0 to 2-3 or flash memory chips 2-0 to 2 under the control of the microprocessor 6. When values necessary for writing data to -3 are set in these registers, a series of operations necessary for reading or writing data is automatically executed.
[0034]
Next, a specific structure of each flash memory cell constituting each flash memory chip 2-0 to 2-3 will be described.
[0035]
FIG. 2 is a cross-sectional view schematically showing the structure of each flash memory cell 16 constituting the flash memory chips 2-0 to 2-3.
[0036]
As shown in FIG. 2, the flash memory cell 16 includes an N-type source diffusion region 18 and a drain diffusion region 19 formed in the P-type semiconductor substrate 17, and between the source diffusion region 18 and the drain diffusion region 19. Tunnel oxide film 20 formed so as to cover P-type semiconductor substrate 17, floating gate electrode 21 formed on tunnel oxide film 20, insulating film 22 formed on floating gate electrode 21, and insulating film 22 And a control gate electrode 23 formed on the substrate. A plurality of flash memory cells 16 having such a configuration are connected in series in the flash memory chips 2-0 to 2-3 to form a NAND flash memory.
[0037]
The flash memory cell 16 is in either “erased state” or “written state” depending on whether electrons are injected into the floating gate electrode 21. The fact that the flash memory cell 16 is in the erased state means that the data “1” is held in the flash memory cell 16, and the fact that the flash memory cell 16 is in the written state means that the flash memory cell 16 This means that data “0” is held in. That is, the flash memory cell 16 can hold 1-bit data.
[0038]
As shown in FIG. 2, the erased state refers to a state where electrons are not injected into the floating gate electrode 21. In the erased state, when no read voltage is applied to the control gate electrode 23, no channel is formed on the surface of the P-type semiconductor substrate 17 between the source diffusion region 18 and the drain diffusion region 19. The diffusion region 18 and the drain diffusion region 19 are electrically insulated by the P-type semiconductor substrate 17. On the other hand, when a read voltage is applied to the control gate electrode 23, a channel (not shown) is formed on the surface of the P-type semiconductor substrate 17 between the source diffusion region 18 and the drain diffusion region 19. Diffusion region 18 and drain diffusion region 19 are electrically connected by a channel. In other words, the source diffusion region 18 and the drain diffusion region 19 are electrically insulated when the read voltage is not applied to the control gate electrode 23, and the source diffusion is performed when the read voltage is applied to the control gate electrode 23. The region 18 and the drain diffusion region 19 are electrically connected.
[0039]
FIG. 3 is a cross-sectional view schematically showing the flash memory cell 16 in the written state.
[0040]
As shown in FIG. 3, the writing state refers to a state in which electrons are accumulated in the floating gate electrode 21. Since the floating gate electrode 21 is sandwiched between the tunnel oxide film 20 and the insulating film 22, the electrons once injected into the floating gate electrode 21 stay in the floating gate electrode 21 for a very long time. In the written state, electrons are accumulated in the floating gate electrode 21, so that the region between the source diffusion region 18 and the drain diffusion region 19 is independent of whether or not the read voltage is applied to the control gate electrode 23. A channel 24 is formed on the surface of the P-type semiconductor substrate 17. Therefore, the source diffusion region 18 and the drain diffusion region 19 are always electrically connected by the channel 24 regardless of whether or not the read voltage is applied to the control gate electrode 23.
[0041]
Here, whether the selected flash memory cell 16 is in the erased state or in the written state can be read as follows. That is, a read voltage is applied to the control gate electrodes 23 of all the flash memory cells 16 other than the selected flash memory cell 16 among a plurality of flash memory cells 16 connected in series. It is detected whether or not a current flows through the series body of cells 16. As a result, if a current flows through the series body, it is determined that the selected flash memory cell 16 is in a write state. If no current flows through the series body, the selected flash memory cell 16 is erased. It is judged that. In this way, it is possible to read out whether the data held in any flash memory cell 16 included in the serial body is “0” or “1”. However, in the NAND flash memory, data held in two or more flash memory cells 16 included in one serial body cannot be read simultaneously.
[0042]
When the flash memory cell 16 that is in the erased state is changed to the written state, a positive high voltage is applied to the control gate electrode 23, whereby electrons are injected into the floating gate electrode 21 through the tunnel oxide film 20. Is done. Electrons can be injected into the floating gate electrode 21 using an FN tunnel current. On the other hand, when the flash memory cell 16 that is in the written state is changed to the erased state, a negative high voltage is applied to the control gate electrode 23, and as a result, it is accumulated in the floating gate electrode 21 through the tunnel oxide film 20. Electrons are discharged.
[0043]
Next, a specific configuration of the address space of each flash memory chip 2-0 to 2-3 will be described.
[0044]
FIG. 4 is a diagram schematically showing the structure of the address space of the flash memory chip 2-0.
[0045]
As shown in FIG. 4, the address space of the flash memory chip 2-0 is configured by 8192 blocks including blocks # 0 to # 8191. Although not shown in FIG. 4, the flash memory chips 2-1 to 2-3 are also configured by 8192 blocks including blocks # 0 to # 8191 as in the flash memory chip 2-0. . Each of these blocks has a storage capacity of 16 Kbytes.
[0046]
Here, each block is a data erasing unit. That is, in the flash memory chips 2-0 to 2-3, the state of each flash memory cell 16 cannot be changed from the written state to the erased state, and the flash memory cell 16 is changed from the written state to the erased state. In the case of changing to, all flash memory cells 16 included in the block to which the flash memory cell 16 belongs are collectively erased. On the contrary, in the flash memory chips 2-0 to 2-3, the state of each flash memory cell 16 can be changed from the erased state to the written state.
[0047]
Further, as shown in FIG. 4, each block # 0 to # 8191 constituting the flash memory chip 2-0 includes 32 pages each including pages # 0 to # 31. Also, the blocks # 0 to # 8191 constituting the flash memory chips 2-1 to 2-3 are each composed of 32 pages, as are the blocks # 0 to # 8191 constituting the flash memory chip 2-0. It is configured.
[0048]
Each of these pages is an access unit for reading and writing data. As shown in FIG. 4, 8 bits consisting of bits b0 to b7 are defined as 1 byte, and a user area 25 of 512 bytes and a redundant area 26 of 16 bytes, respectively. Consists of. The user area 25 is an area in which user data supplied from the host computer 5 is stored.
[0049]
FIG. 5 is a diagram schematically showing the data structure of the redundant area 26.
[0050]
As shown in FIG. 5, the redundant area 26 includes an error correction code 28, a corresponding logical block address 29, a cyclic redundancy bit (CRC) 31 for the corresponding logical block address, a start page flag 32, a start page data 33, and other additions. Consists of information.
[0051]
The error collection code 28 is additional information for correcting an error in the user data stored in the corresponding user area 25, and if the number of data errors included in the data stored in the user area 25 is equal to or less than a predetermined number. This can be corrected using the error collection code 28 to obtain correct data.
[0052]
The corresponding logical block address 29 is additional information that is valid for pages # 0 to # 3 and page # 31, and indicates what logical block address the block is accessed by. Details of the corresponding logical block address 29 will be described later.
[0053]
The CRC 31 is additional information effective for the pages # 0 to # 3 and the page # 31, and is used to detect an error included in the corresponding logical block address 29. Unlike the error correction code 28 that can correct an error included in user data, the CRC 31 cannot correct an error included in the corresponding logical block address 29. It is only used to detect whether or not there is.
[0054]
The start page flag 32 is a flag composed of at least 2 bits. Of these, the upper 1 bit is a valid bit in page # 0, and the lower 1 bit is a valid bit in pages # 0 to # 30. It is. Specifically, if the start page flag 32 of the page # 0 is “1x (x is arbitrary)”, it indicates that the start page exists in the block, and the start page flag 32 of the page # 0 is “0x”. If present, it indicates that there is no start page in the block. If the start page flag 32 of the pages # 0 to # 30 is “x0”, it indicates that the corresponding start page data 33 is valid, and if the start page flag 32 is “x1”, the corresponding start page data 33 is valid. Indicates that the page data 33 is invalid.
[0055]
The start page data 33 is additional information for specifying the start page of the block. Here, the “start page” means that one or more continuous pages including the last page in the block are empty pages in which no data is stored. Points to the first page. For example, when data is stored only in pages # 0 to # 10 of a certain block, the start page is page # 11, and when data is stored only in page # 23 of a certain block, the start page is It becomes page # 24. Therefore, in each block, the pages after the start page are guaranteed to be empty pages in which no data is stored.
[0056]
Identification of the start page using the start page data 33 can be performed by “start page search”. In the start page search, first, the start page data 33 of page # 0 is referred to, and the start page flag 32 of the page indicated by the content is referred to. For example, if the start page data 33 of page # 0 is “00111B (7)”, then the start page flag 32 of page # 7 is referred to. As a result, if the start page flag 32 is “x0” and it is determined that the corresponding start page data 33 is valid, the start page flag 32 of the page indicated by the content is further referred to. Thus, based on the start page data, it is determined one after another whether or not the corresponding start page flag 32 is valid, and the start page search is terminated when the referenced start page flag 32 becomes “x1”. The page is determined to be a “start page”. For example, in the above example, if the start page flag 32 of page # 7 is “x1”, it is determined that the start page is page # 7.
[0057]
The other areas of the redundant area 26 store a block status or the like that displays an abnormality regarding the block, but the description thereof is omitted.
[0058]
Thus, each page is composed of a 512-byte user area 25 and a 16-byte redundant area 26, so that each page is composed of 8 × (512 bytes + 16 bytes) = 4224 flash memory cells. Become.
[0059]
As described above, each of the flash memory chips 2-0 to 2-3 is configured by 8192 physical blocks. Of these, 8000 physical blocks are blocks that can actually store data (hereinafter, “ The remaining 192 blocks are treated as “redundant blocks”. The redundant block is an empty block waiting for data writing. The address space of the flash memory chips 2-0 to 2-3 is composed only of actual use blocks. When a defect occurs in a physical block and becomes unusable, the number of physical blocks allocated as redundant blocks is reduced by the number of blocks in which the defect has occurred.
[0060]
Since the flash memory chips 2-0 to 2-3 having such a configuration are handled as one large memory having an address space of 1M pages as described above, the address space consisting of these 1M pages is changed to a specific page. To access, a 20-bit host address is used as described above. Of the 20-bit host address, the upper 15 bits are used to specify the flash memory chip and the block included in the specified flash memory chip, and the remaining 5 bits (lower 5 bits) are the specified block. Used to specify the pages included in the.
[0061]
The flash memory chip and block using the upper 15 bits of the host address are identified by dividing the upper 15 bits of the host address by “8000” and accessed by the quotient (0 to 3) obtained by the division. The flash memory chip to be determined is determined, and the “logical block address” is determined by the remainder (0 to 7999). Such a logical block address is converted into a “physical block address” in an “address conversion table” to be described later, whereby a block to be actually accessed is specified.
[0062]
Here, the necessity of converting a logical block address into a physical block address using an address conversion table will be described.
[0063]
As described above, the flash memory cells 16 constituting the flash memory chips 2-0 to 2-3 can be changed from the erased state to the written state in units of memory cells. Changing to the erased state cannot be performed in units of memory cells, but can be performed only in units of blocks. For this reason, when data is written to a certain page, it is necessary that all flash memory cells 16 constituting the user area 25 of the page are in an erased state. The page in which even one flash memory cell 16 constituting the user area 25 of the page is in a write state cannot be directly overwritten with data different from this. Therefore, in order to write new data different from this to a page in which data has already been written, all the flash memory cells 16 constituting the block to which this page belongs are temporarily erased, and then new data is written. Processing is required.
[0064]
Therefore, when overwriting old data stored in a page with new data, in order to prevent the data stored in the other page included in the block to which this page belongs from being lost, It is necessary to move the stored data to another block. Therefore, the relationship between the logical block address obtained from the host address and the physical block address on the flash memory chips 2-0 to 2-3 corresponding to the logical block address is instructed by the host computer 5 to overwrite data. Change dynamically every time. For this reason, in order to access the flash memory chips 2-0 to 2-3 from the host computer 5, the relationship between the logical block address and the physical block address on the flash memory corresponding to the logical block address is determined. This is because an address conversion table in which the information shown is stored is required. Details of the address conversion table will be described later.
[0065]
Next, various work data stored in the SRAM work area 8 will be described. In the SRAM work area 8, at least the address conversion table 27 and the erased block queue 30 are stored.
[0066]
FIG. 6 is a schematic diagram showing the data structure of the address conversion table 27 stored in the SRAM work area 8.
[0067]
As shown in FIG. 6, the address conversion table 27 is composed of four tables consisting of tables # 0 to # 3. Each table has 8000 flags, 8000 physical block address storage areas, and 8000. The start page storage area. These tables # 0 to # 3 correspond to the flash memory chips 2-0 to 2-3, respectively.
[0068]
Corresponding physical block addresses (13 bits) are stored in 8000 physical block address storage areas # 0 to # 7999 in the tables # 0 to # 3, respectively. The address conversion information indicating the corresponding relationship is formed. That is, the physical block address storage areas # 0 to # 7999 in the table # 0 are assigned physical block addresses of 8000 actual used blocks constituting the flash memory chip 2-0, and these assigned logical block addresses. And the physical block address stored therein have a correspondence relationship. Similarly, the physical block address storage areas # 0 to # 7999 in the tables # 1 to # 3 are allocated with physical block addresses of 8000 actually used blocks constituting the flash memory chips 2-1 to 2-3, respectively. It is done.
[0069]
For example, if “101010101010101B” consisting of the upper 15 bits of the host address supplied from the host computer 5 is divided by 8000, the quotient is “2” and the remainder is “5845”. If the physical block address storage area # 5845 in # 2 is selected and the physical block address stored here, for example, the stored physical block address is “0000000011111B”, “31” is set as the physical block address. Thus, the conversion from the logical block address # 5845 in the flash memory chip 2-2 to the physical block address # 31 in the flash memory chip 2-2 is completed.
[0070]
The 8000 flags in each table # 0 to # 3 correspond to the physical block address storage areas # 0 to # 7999 in the table, respectively, and the physical stored in the corresponding physical block address storage area. Indicates whether the block address is a valid value. Specifically, if the flag is “1”, it indicates that the physical block address stored in the corresponding physical block address storage area is a valid value, and if the flag is “0”, the corresponding physical block address is stored. Indicates that the physical block address stored in the block address storage area is not a valid value. Therefore, it means that a physical block address is not yet associated with a logical block address whose corresponding flag is “0”.
[0071]
Furthermore, the 8000 start page storage areas # 0 to # 7999 in the tables # 0 to # 3 correspond to the physical block address storage areas # 0 to # 7999 in the table, respectively, and the corresponding physical blocks Information on the start page of the block indicated by the physical block address stored in the address storage area is stored.
[0072]
In 8000 start page storage areas # 0 to # 7999 in each table # 0 to # 3, information about the start page is stored in 5 bits. Specifically, when the start page stored in the start page storage area is “00000B”, it indicates that there is no start page in the corresponding block, and when it is “00001B”, it corresponds Although the start page exists in the block to be performed, it is indicated that the start page needs to be obtained by the above-described start page search. When the value is other than that, it is indicated that the value is the start page. For example, when the start page stored in the start page storage area is “01100B”, the start page of the block is page # 12.
[0073]
As described above, the address conversion table 27 is composed of 32000 physical block storage areas and 32000 start page storage areas, and each physical block storage area must store 13-bit information. Since it is necessary to store 5-bit information in each start page storage area, the address conversion table 27 occupies about 72 kbytes of the storage capacity of the SRAM work area 8.
[0074]
The address conversion table 27 is generated as follows.
[0075]
Of the blocks constituting the flash memory chips 2-0 to 2-3, the redundant area 26 included in each head page (page # 0) of the block storing data has the block as described above. A corresponding logical block address 29 indicating which logical block address corresponds is included, and the corresponding logical block address 29 and CRC 31 stored in each head page of each block are flashed under the control of the microprocessor 6. Read through the memory interface block 10.
[0076]
At this time, the CRC 31 is used to check whether each corresponding logical block address 29 contains an error. If it is determined that the corresponding logical block address 29 contains an error, the block 31 The corresponding logical block address 29 and CRC 31 stored in page # 1 are newly read out. In this way, the corresponding logical block address 29 read from page # 1 is also checked for errors by using CRC 31, and the corresponding logical block address 29 contains an error. If it is determined, the corresponding logical block address 29 and CRC 31 stored in page # 2 of the block are newly read out. Such processing is performed up to page # 3. If there is an error in the corresponding logical block address 29 of page # 3, whether or not the block is a bad block is diagnosed, and as a result, it is diagnosed as a bad block. If it is, subsequent use is prohibited.
[0077]
On the other hand, when the corresponding logical block address 29 without error is read from any of the pages # 0 to # 3 of each block, these corresponding logical block addresses 29 are used under the control of the microprocessor 6. It is determined whether the block is an erased empty block.
[0078]
Here, in the erased empty block, the corresponding logical block address 29 stored in the redundant area 26 should be “all 1 (111111111111B)”. That is, as described above, the corresponding logical block address 29 is only from # 0 (0000000000000B) to # 7999 (1111100111111B). Therefore, when this is all 1 (1111111111111B), the corresponding empty block is erased. Can be determined. On the other hand, when the corresponding logical block address 29 is “0000000000000000B” to “1111100111111B”, the corresponding logical block address 29 is a valid logical block address.
[0079]
Therefore, the microprocessor 6 refers to the corresponding logical block address 29 included in the redundant area 26 of pages # 0 to # 3 of each block, and if this indicates the number of a valid logical block address instead of all 1, The corresponding logical block address 29 is read into the physical block address storage area to which the same logical block address as the read corresponding logical block address 29 is allocated among the physical block address storage areas belonging to the table corresponding to the chip number. The physical block address of the block is stored, and the corresponding flag is set to “1”. For example, if the block from which the corresponding logical block address 29 is read belongs to the flash memory chip 2-0, the physical block address is “10”, and the read corresponding logical block address 29 is “123”, the table Of the physical block address storage areas belonging to # 0, “10” is written as the physical block address to the physical block address storage area # 123 to which “123” is assigned as the logical block address, and the corresponding flag is “ 1 ”.
[0080]
Furthermore, if the corresponding logical block address 29 indicates a valid logical block address number, the microprocessor 6 starts the start page flag 32 stored in the redundant area 26 of each first page (page # 0) of the block. Refer to As described above, the start page flag 32 in the page # 0 indicates that a start page exists in the block if “1x”, and indicates that no start page exists in the block if “0x”. As a result of referring to the start page flag, if this is “1x”, the content of the corresponding start page storage area in the address conversion table 27 is “00001B”, and if this is “0x”, the address conversion table 27. The content of the corresponding start page storage area is “00000B”.
[0081]
On the other hand, if the corresponding logical block address 29 indicates a valid logical block address number, the same logical block as the read corresponding logical block address 29 in the physical block address storage area belonging to the table corresponding to the chip number. The flag corresponding to the physical block address storage area to which the address is assigned is set to “1”.
[0082]
The processing as described above is performed for all the blocks in which data is stored, whereby the creation of the address conversion table 27 is completed.
[0083]
Next, the data structure of the erased block queue 30 stored in the SRAM work area 8 will be described.
[0084]
FIG. 7 is a schematic diagram showing the data structure of the erased block queue 30 stored in the SRAM work area 8.
[0085]
As shown in FIG. 7, the erased block queue 30 is configured by eight queues including queues # 0 to # 7. Each of these queues # 0 to # 7 uses a 2-byte storage area of the SRAM work area 8, and each of them stores a physical block address as 13-bit data. Therefore, the erased block queue 30 occupies 16 bytes of the storage capacity of the SRAM work area 8.
[0086]
Among the queues # 0 to # 7 constituting the erased block queue 30, the queues # 0 and # 1 are queues for the flash memory 2-0, and the queues # 0 and # 1 include the flash memory 2-0. Are stored, that is, physical block addresses of blocks in which all flash memory cells 16 constituting the user area 25 and the redundant area 26 are in the erased state. Similarly, queues # 2 and # 3 are queues for the flash memory 2-1, queues # 4 and # 5 are queues for the flash memory 2-2, and queues # 6 and # 7 are flash queues. This is a queue for the memory 2-3.
[0087]
The generation of the erased block queue 30 is performed when the above-described address conversion table 27 is generated under the control of the microprocessor 6.
[0088]
That is, the redundant area 26 included in page # 0 to page # 3 of each block constituting the flash memory chips 2-0 to 2-3 includes the corresponding logical block address 29 as described above. When the conversion table 27 is generated, a block whose corresponding logical block address 29 is “all 1 (1111111111111B)” is searched under the control of the microprocessor 6. As a result of such a search, a maximum of 192 erased blocks are detected for each flash memory chip to become redundant blocks, and a maximum of two redundant blocks are selected from these, and the physical block address corresponds to the corresponding flash memory chip. Are stored in two queues.
[0089]
The generation of the erased block queue 30 is performed when the above-described address conversion table 27 is generated under the control of the microprocessor 6.
[0090]
Next, various data write operations by the flash memory system 1 according to this embodiment will be described.
[0091]
Write operation 1 (when writing data to an empty block)
When data is written to an empty block, the page # 0 to # 3 and page # 31 redundant area 26 of the block has a corresponding logical block regardless of the page to which user data is to be written and the page to which user data is to be written. Address 29 and CRC 31 are stored.
[0092]
The reason why the corresponding logical block address 29 and the CRC 31 are stored in the redundant areas 26 of the pages # 0 to # 3 is that they are referred to when the address conversion table 27 is created. Also, the corresponding logical block address 29 and CRC 31 are stored in the redundant area 26 of page # 31 because the contents are incomplete because the power is unexpectedly cut off during the transfer between blocks. This is because it is possible to specify the corresponding logical block address in the state immediately before the current block when there is a new block.
[0093]
Here, the reason why pages # 0 to # 3 are selected as the targets to write the corresponding logical block address 29 and CRC 31 regardless of the page to which user data is to be written is as follows. In other words, regardless of the page to which user data is to be written, the smaller the number of pages to which the corresponding logical block address 29 and CRC 31 are to be written, the smaller the number of pages written to the pages other than the page to which user data is to be written. While the writing process can be executed at a higher speed, the probability that this error can be remedied when an error occurs in the corresponding logical block address 29 is reduced. On the other hand, the more pages to which the corresponding logical block address 29 and CRC 31 are written regardless of the page to which user data is to be written, the higher the probability that this error can be remedied when an error occurs in the corresponding logical block address 29. On the other hand, since the number of write processes for pages other than the page to which user data is to be written increases, a long time is required for a series of write processes. For this reason, the page to which the corresponding logical block address 29 and CRC 31 are written regardless of the page to which user data is to be written is determined in consideration of the number of pages including the first page (page # 0). There is a need to. Therefore, in the present embodiment, if any of the corresponding logical block addresses 29 stored in the pages # 0 to # 3 includes an error, the possibility that a fatal defect exists in the block is extremely high. Therefore, pages # 0 to # 3 are selected as pages to which the corresponding logical block address 29 and CRC 31 are to be written regardless of the page to which user data is to be written.
[0094]
On the other hand, for pages where data is actually written in the user area 25, even if this is other than pages # 0 to # 3 and page # 31, the corresponding logical block address 29 and CRC 31 are stored in the redundant area 26 of the page. Stored.
[0095]
As described above, when data is written in an empty block, the writing process is always executed for pages to which user data is to be written, pages # 0 to # 3 and page # 31. On the other hand, for the pages that belong to pages # 4 to # 30 and are not pages to which user data is to be written, the corresponding logical block address 29 and CRC 31 are not written.
[0096]
Next, the writing of the start page flag 32 and the start page data 33 in the redundant area 26 when writing data to an empty block will be described.
[0097]
When data is written in an empty block, the page number that becomes the start page by the writing process is written as the start page data 33 in the redundant area 26 of page # 0 and the start page flag 32 of the redundant area 26 of page # 0. Is rewritten to “10”. However, if the start page does not exist as a result of the writing process, that is, if page # 31 is included in the page to which user data is to be written, the start page flag 32 of the redundant area 26 of page # 0. Is rewritten to “0x”.
[0098]
Here, the page serving as the start page is a page next to the last page of the page in which user data is to be written.
[0099]
The above-described data writing process for the empty block will be described in more detail with a specific example.
[0100]
Here, an external write command, which is a kind of external command, and two host addresses “0000001111010000001B” (host address # 0) and “0000001111010000010B” (host) from the host computer 5 via the bus 14, the connector 4 and the bus 13. An example will be described in which the address # 1) and data to be written to each of these host addresses are supplied to the flash memory system 1.
[0101]
First, when host addresses # 0 and # 1 and an external write command are supplied to the controller 3, the host address and external write command are temporarily stored in a task file register (not shown) of the host interface block 7. Is done. Further, when write data is supplied to the controller 3, it is sent to the ECC block 11 under the control of the microprocessor 6. The ECC block 11 that has received the supply of the write data analyzes this to generate an error collection code 28 and temporarily holds it. Furthermore, the ECC block 11 generates data obtained by adding 1 to the lower 5 bits of the host address # 1 as start page data, and temporarily holds this data. In this case, the start page data is “00011 (3)”.
[0102]
Next, whether or not the host addresses # 0 and # 1 stored in the task file register (not shown) are correct addresses, that is, these host addresses do not indicate an originally nonexistent address or an invalid address. Is determined by the host interface block 7.
[0103]
As a result of the determination, if it is determined that the host addresses # 0 and # 1 stored in the task file register (not shown) are valid addresses, they are converted into internal addresses using the address conversion table 27. On the other hand, if it is determined that this is an abnormal address, an error register (not shown) of the host interface block 7 is set, and the host computer 5 refers to the contents of the register to generate an error. I can know.
[0104]
Conversion to the internal address is performed as follows.
[0105]
First, under the control of the microprocessor 6, the upper 15 bits are extracted from the 20-bit host address and divided by “8000”. Then, the flash memory chip to be accessed is specified by the quotient (0 to 3) obtained by the division, and the block is specified by the remainder (0 to 7999). In this example, since the upper 15 bits of the host address are “00000011110100B”, the quotient is “00000B (0)” and the remainder is “0111110100B (500)”. As a result, the selected flash memory chip becomes the flash memory chip 2-0, and the logical block address becomes the logical block address # 500.
[0106]
Next, under the control of the microprocessor 6, the flag corresponding to the physical block address storage area # 500 is read from the table # 0 in the address conversion table 27 based on the logical block address # 500. In this example, the flag is “0”, and it is detected that there is no block corresponding to the host addresses # 0 and # 1.
[0107]
In response to this, queue # 0 (or queue # 0) that is a queue for flash memory chip 2-0 among queues # 0 to # 7 constituting erased block queue 30 under the control of microprocessor 6. The physical block address stored in 1) is read. Here, for example, it is assumed that the physical block address stored in the queue # 0 is “0000000000000100B (4)”. As described above, the physical block addresses stored in the queue # 0 of the erased block queue 30 are erased blocks included in the flash memory chip 2-0, that is, all the flashes constituting the user area 25 and the redundant area 26. This is the physical block address (13 bits) of the block in which the memory cell 16 is in the erased state.
[0108]
When the physical block address “0000000000100B (4)” stored in the queue # 0 is read, it is stored in the physical block address storage area # 500 in the table # 0 and corresponds to the physical block address storage area # 500. The start page “00011 (3)” is stored in the start page storage area # 500. Further, the corresponding flag is rewritten to “1”. Under the control of the microprocessor 6, the selected chip number, the physical block address, and the lower 5 bits of the host addresses # 0 and # 1 are combined in this order. The combined address becomes an internal address. In this case, the selected chip number is “00B”, the read queue content is “0000000000000B”, and the lower 5 bits of the host addresses # 0 and # 1 are “00001B” and “00010B”, respectively. Therefore, the obtained internal addresses # 0 and # 1 are “00000000000010000001B” and “00000000000010000010B”, respectively.
[0109]
Thus, the conversion from the host address # 0, # 1 to the internal address # 0, # 1 is completed. The internal address specifies a flash memory chip by upper 2 bits, specifies a block in the flash memory chip by 13 bits consisting of upper 3 bits to upper 15 bits, and specifies a page in the block by lower 5 bits. Therefore, the page # 1 of the block # 4 in the flash memory chip 2-0 is accessed by the internal address # 0, and the page # 1 in the flash memory chip 2-0 is accessed by the internal address # 1. It becomes page # 2 of block # 4.
[0110]
When the generation of the internal address is completed in this way, settings are made for a register (not shown) included in the flash sequencer block 12 under the control of the microprocessor 6. Such setting is performed as follows.
[0111]
First, under the control of the microprocessor 6, an internal write command, which is a kind of internal command, is set in a predetermined register (not shown) in the flash sequencer block 12. Further, under the control of the microprocessor 6, the generated internal addresses # 0 and # 1 are set in predetermined registers (not shown) in the flash sequencer block 12.
[0112]
When the setting for various registers (not shown) included in the flash sequencer block 12 is completed in this way, a series of write operations by the flash sequencer block 12 is executed. In this example, a series of write operations by the flash sequencer block 12 is performed by writing various redundant data to page # 0 of block # 4 in the flash memory chip 2-0, user data and various redundant data for page # 1 of the same block. Data is written, user data and various redundant data are written to page # 2 of the same block, various redundant data are written to page # 3 of the same block, and various redundant data are written to page # 31 of the same block.
[0113]
First, the writing process for page # 0 of block # 4 will be described.
[0114]
In this operation, the flash sequencer block 12 is based on the upper 2 bits of the internal address # 0 stored in a predetermined register, and the flash memory to which the page to be accessed belongs among the flash memory chips 2-0 to 2-3. The flash memory interface block 10 is instructed to activate a chip selection signal corresponding to the chip. In this case, since the upper 2 bits of the internal address are “00B (0)”, the flash memory chip to which the page to be accessed belongs is the flash memory chip 2-0, and the chip selection signal # 0 is activated. . Thereby, the flash memory chip 2-0 is in a state where data can be written. On the other hand, the chip selection signals # 1 to # 3 are kept inactive.
[0115]
Next, the flash sequencer block 12 generates a write address in which the lower 5 bits of the internal address # 0 are set to “00000B”, and the lower 18 bits “000000000010000000B” together with the internal write command stored in a predetermined register. The flash memory interface block 10 is instructed to supply the data to 15. The 18-bit internal address and internal read command supplied to the bus 15 are commonly supplied to the flash memory chips 2-0 to 2-3, but the chip selection signal # 0 is activated as described above. Since the chip selection signals # 1 to # 3 are inactive, the internal address and internal read command supplied to the bus 15 are valid only for the flash memory chip 2-0.
[0116]
As a result, the flash memory chip 2-0 is allowed to accept data to be written to page # 0 of block # 4.
[0117]
Next, data to be written to page # 0 of block # 4 is supplied to the bus 15 by the flash sequencer block 12 via the flash memory interface block 10. Here, the data to be written to page # 0 of block # 4 is the corresponding logical block address 29, CRC 31, start page flag 32, start page data 33 and other additional information, all of which are stored in the redundant area 26. Data to be written. In this case, the corresponding logical block address 29 is “000011110100B (500)”, the CRC 31 is a code corresponding to “000011110100B (500)”, the start page flag 32 is “10”, and the start page data 33 is “ 00001 (3) ". No data is written in the other part of the page # 0, that is, the entire part of the user area 25 and the error collection code 28 and other parts of the redundant area 26. However, since writing of data to each page is performed in batches in units of pages, actually, write processing is not performed on the portion where the data is not written, and write data consisting of “all 1” is written. Will be written.
[0118]
The corresponding logical block address 29, CRC 31, start page flag 32, start page data 33 and other additional information stored in the redundant area 26 supplied to the bus 15 are also sent to the flash memory chips 2-0 to 2-3. Although supplied in common, as described above, since the chip selection signal # 0 is in the active state, it is effective only for the flash memory chip 2-0.
[0119]
In this way, the flash memory chip 2-0 in a state where the acceptance of write data is permitted is stored in the corresponding logical block address 29, CRC 31, start page flag 32, start page data 33, and redundant area 26. When the additional information is transferred, the corresponding logical block address 29, CRC 31, start page flag 32, start page data 33, and other additional information stored in the redundant area 26 are stored in the flash memory chip 2-0. Is temporarily stored in a register (not shown).
[0120]
Next, the flash sequencer block 12 issues an internal write command stored in a predetermined register (not shown) to the flash memory chip 2-0. In response to this, the flash memory chip 2-0 receives the corresponding logical block address 29, CRC 31, start page flag 32, start page data 33 and other additional information stored in the redundant area 26 stored in the register. Write to a predetermined position of page # 0 of block # 4 (flash programming).
[0121]
Thereby, the writing process for page # 0 of block # 4 is completed.
[0122]
When the writing process for page # 0 in block # 4 is completed, the writing process for page # 1 in block # 4 is then executed.
[0123]
In the writing process for page # 1 in block # 4, the chip selection signal # 0 is activated in the same manner as described above. Next, the flash sequencer block 12 instructs the flash memory interface block 10 to supply the lower 18 bits “00000000000000010001B” of the internal address # 0 to the bus 15 together with the internal write command stored in a predetermined register. As described above, since the chip selection signal # 0 is in the active state, the internal address and the internal read command supplied to the bus 15 are valid only for the flash memory chip 2-0.
[0124]
As a result, the flash memory chip 2-0 is allowed to accept data to be written to page # 1 of block # 4.
[0125]
Next, data to be written to page # 1 of block # 4 is supplied to the bus 15 by the flash sequencer block 12 via the flash memory interface block 10. Here, data to be written to page # 1 of block # 4 includes user data corresponding to host address # 0, error collection code 28 corresponding to the user data, corresponding logical block address 29, CRC 31, and start page flag 32. , Start page data 33 and other additional information stored in the redundant area 26. Among these, the corresponding logical block address 29, CRC 31, start page flag 32, and start page data 33 have the same contents as these data for page # 0.
[0126]
Similar to the above, these data are temporarily stored in a register (not shown) provided in the flash memory chip 2-0, and in response to the issuance of an internal write command, predetermined data in page # 1 of block # 4 is stored. Is written at the position of. That is, user data corresponding to the host address # 0 is stored in the user area 25 of the page # 1, and the error correction code 28, the corresponding logical block address 29, the CRC 31, the start page flag 32, and the start area are stored in the redundant area 26. The page data 33 and other additional information are stored.
[0127]
This completes the writing process for page # 1 in block # 4.
[0128]
When the writing process for page # 1 in block # 4 is completed, the writing process for page # 2 in block # 4 is then executed.
[0129]
The writing process for page # 2 in block # 4 is performed using internal address # 1, and the procedure is the same as the writing process for page # 1 in block # 4. As a result, the user data corresponding to the host address # 1 is stored in the user area 25 of page # 2, and the error correction code 28, the corresponding logical block address 29, the CRC 31, the start page flag 32, The start page data 33 and other additional information are stored.
[0130]
This completes the writing process for page # 2 of block # 4.
[0131]
When the writing process for page # 2 in block # 4 is completed, the writing process for page # 3 in block # 4 is then executed.
[0132]
The writing process for page # 3 in block # 4 is the same as the writing process for page # 0 in block # 4 described above, except that the start page flag 32 and start page data 33 are not written. As a result, the corresponding logical block address 29 and CRC 31 are stored in the redundant area 26 of page # 3.
[0133]
This completes the writing process for page # 3 of block # 4.
[0134]
When the writing process for page # 3 in block # 4 is completed, the writing process for page # 31 in block # 4 is then executed.
[0135]
The writing process for page # 31 of block # 4 is the same as the writing process for page # 3 of block # 4 described above. As a result, the corresponding logical block address 29 and CRC 31 are stored in the redundant area 26 of page # 31.
[0136]
Thereby, a series of write processing is completed.
[0137]
FIG. 8 is a schematic diagram showing the contents of block # 4 in a state where the series of write processing is completed.
[0138]
In FIG. 8, with respect to the user area 25, the portion where user data is stored is hatched, and for the redundant area 26, only the corresponding logical block address 29, the start page flag 32, and the start page data 33 are shown. The error collection code 28, CRC 31, and other additional information are omitted.
[0139]
As shown in FIG. 8, since user data is stored only in pages # 1 and # 2 of block # 4 and no user data is stored in other pages, the start page in the block is “3”. It can be seen that this value is stored as start page data 33 of page # 0. For this reason, the controller 3 can know that pages # 3 to # 31 of this block are empty pages, and then the host computer 5 writes data to pages # 3 to # 31 of block # 4. Even if requested, it is possible to directly write data to pages # 3 to # 31 without performing inter-block transfer.
[0140]
In the above example, the start page flag 32 and the start page data 33 are also written in pages other than the page # 0 that is the first page (pages # 1 and # 2 in which user data is written). It can be omitted.
[0141]
Write operation 2 (when adding data to a used block and writing)
When data is added and written to a block in which data is already stored (used block), additional data is written to the block by referring to the corresponding start page storage area in the address conversion table 27. It is determined whether or not it is possible.
[0142]
In this determination, first, the start page relating to the block is specified. As described above, there are a method of specifying the start page by searching for the start page and a method of specifying directly from the start page stored in the start page storage area in the address conversion table 27.
[0143]
The identification of the start page by the former method is executed when the start page exists but the controller 3 is activated and data has not yet been written to the block. That is, when the address conversion table 27 is created, the corresponding logical block address 29 included in page # 0 (or pages # 1 to # 3) of the block indicates a valid logical block address, and the start When the page flag is “1x”, the corresponding start page storage area in the address conversion table 27 is set to “00001B”. In this case, the controller 3 performs the start page search to start the block concerned. The page can be specified.
[0144]
On the other hand, the specification of the start page by the latter method is executed when data is written to the block at least once after the controller 3 is activated as described in the write operation 1 above. That is, when data is written to the block at least once, the start page is written in the corresponding start page storage area in the address conversion table 27 as described above. In this case, the controller 3 It is possible to specify the start page related to the block by referring to the start page storage area.
[0145]
When the start page is specified by any of the methods in this manner, the start page is then compared with the first page of the page to be written, so that additional data can be written. Is finally determined. This determination can be made by additionally writing data if the 5-bit value indicating the first page of the page to be written is the same as or exceeding the 5-bit value indicating the start page. If the 5-bit value indicating the first page of the page to be written is less than the 5-bit value indicating the start page, additional data cannot be written.
[0146]
If it is determined that additional data cannot be written as a result of this determination, inter-block transfer is performed as usual.
[0147]
On the other hand, if it is determined as a result of this determination that additional writing of data is possible, additional data writing processing, which will be described in detail below, is performed.
[0148]
When an additional data writing process is performed, the process to be performed differs depending on whether or not the first page of the page in which user data is to be written matches the start page.
[0149]
First, when the top page of a page to which user data is to be written matches the start page, that is, when user data is written to the start page, a page that becomes a new start page by the writing process Are written in the redundant area 26 of each page where user data is to be written as start page data 33.
[0150]
On the other hand, if the first page of the page to be written does not match the start page, that is, if user data is not written to the start page, the page that becomes the new start page by the writing process Are written as start page data 33 in the redundant area 26 of the current start page and each page to be written.
[0151]
Further, when additional writing of data is performed, the page number to be a new start page is written in the redundant area 26 of the current start page by the writing process. However, if the start page does not exist as a result of the writing process, that is, if page # 31 is included in the page to which user data is to be written, the start page flag 32 of the redundant area 26 of page # 0. Is rewritten to “0x”.
[0152]
Here, the page that becomes a new start page is a page next to the last page of the page to be written.
[0153]
The above-described data writing process for the empty block will be described in more detail with a specific example.
[0154]
First, the case where the first page of the page to which user data is to be written matches the start page will be described.
[0155]
When the first page of the page where user data is to be written matches the start page
Here, in a state immediately after the above-described write operation 1 is completed, an external write command that is a kind of external command and two host addresses “0000001111010000011B” from the host computer 5 via the bus 14, the connector 4, and the bus 13. ”(Host address # 0) and“ 00000011111000010000B ”(host address # 1) and data to be written to these host addresses will be described as an example.
[0156]
The basic operation of the controller 3 when the host addresses # 0 and # 1 and the external write command are supplied to the controller 3 is as described above, and the description of the overlapping parts is omitted.
[0157]
Conversion to the internal address is performed as follows.
[0158]
First, under the control of the microprocessor 6, the upper 15 bits are extracted from the 20-bit host address and divided by “8000”. Then, the flash memory chip to be accessed is specified by the quotient (0 to 3) obtained by the division, and the logical block address is specified by the remainder (0 to 7999).
In this example, since the upper 15 bits of the host address are “00000011110100B”, the quotient is “00000B (0)” and the remainder is “0111110100B (500)”. As a result, the selected flash memory chip becomes the flash memory chip 2-0, and the logical block address becomes the logical block address # 500.
[0159]
Next, under the control of the microprocessor 6, the flag corresponding to the physical block address storage area # 500 is read from the table # 0 in the address conversion table 27 based on the logical block address # 500. In this example, the flag is “1”, and it is detected that there are blocks corresponding to the host addresses # 0 and # 1. In response to this, the contents stored in the physical block address storage area # 500 are read out. In this example, the content of the physical block address storage area # 500 is “000000000000100B”, and accordingly, the block corresponding to the host addresses # 0 and # 1 is the block # 4 in the flash memory chip 2-0. Is detected.
[0160]
Next, under the control of the microprocessor 6, the start page storage area # 500 is selected from the table # 0 in the address conversion table 27 based on the logical block address # 500, and the contents stored therein are read out. It is. In this example, the content of the start page storage area # 500 is “00011B (3)”.
[0161]
When the start page is read in this way, the comparison with the first page of the page to be written is performed under the control of the microprocessor 6. In this case, since the first page of the page to be written is indicated by the host address # 0, the value “00011 (3)” of the start page and the value “00011 (3) of the lower 5 bits of the host address # 0 ) ”Will be compared. In this way, in this example, since the value “00011 (3)” of the lower 5 bits of the host address # 0 matches the value “00011 (3)” of the start page, additional data can be written. It is judged that.
[0162]
Further, under the control of the microprocessor 6, data is generated by adding 1 to the lower 5 bits of the host address # 1 indicating the last page of the page in which user data is to be written, thereby generating a new start page. The The start page value is temporarily held in the ECC block 11 as start page data. In this case, since the lower 5 bits of the host address # 1 are “00100 (4)”, the start page data stored in the ECC block 11 is “00101 (5)”.
[0163]
Under the control of the microprocessor 6, the selected chip number, the physical block address, and the lower 5 bits of the host addresses # 0 and # 1 are combined in this order. The combined address becomes an internal address. In this case, the selected chip number is “00B”, the physical block address is “000000000000100B”, and the lower 5 bits of the host addresses # 0 and # 1 are “00011B” and “00100B”, respectively. The obtained internal addresses # 0 and # 1 are “00000000000010000011B” and “00000000000010000100B”, respectively.
[0164]
Further, the start page “00101 (5)” is overwritten in the start page storage area # 500 corresponding to the physical block address storage area # 500.
[0165]
Thus, the conversion from the host address # 0, # 1 to the internal address # 0, # 1 is completed. As a result, page # 3 of block # 4 in flash memory chip 2-0 is accessed by internal address # 0, and block # 4 in flash memory chip 2-0 is accessed by internal address # 1. 4 page # 4.
[0166]
Thereafter, when setting to a register (not shown) included in the flash sequencer block 12 is completed, a series of write operations by the flash sequencer block 12 is executed. In this example, a series of write operations by the flash sequencer block 12 is performed by writing user data and various redundant data to page # 3 of block # 4 in the flash memory chip 2-0 and user data for page # 4 of the same block. And various redundant data are written in order.
[0167]
First, the writing process for page # 3 of block # 4 will be described.
[0168]
Note that page # 3 of block # 4 has already been written to the corresponding logical block address 29 in the write operation 1, but all the flash memory cells 16 constituting the user area 25 are in the erased state (logical value). = 1), user data can be written.
[0169]
In the writing process for page # 3 in block # 4, the flash sequencer block 12 activates the chip selection signal # 0 based on the upper 2 bits of the internal address # 0 stored in a predetermined register. Thereby, the flash memory chip 2-0 is in a state where data can be written. On the other hand, the chip selection signals # 1 to # 3 are kept inactive.
[0170]
Next, the flash sequencer block 12 instructs the flash memory interface block 10 to supply the lower 18 bits “000000000000010011B” of the internal address # 0 to the bus 15 together with the internal write command stored in a predetermined register. As described above, since the chip selection signal # 0 is in the active state, the internal address and the internal read command supplied to the bus 15 are valid only for the flash memory chip 2-0.
[0171]
As a result, the flash memory chip 2-0 is allowed to accept data to be written to page # 3 of block # 4.
[0172]
Next, data to be written to page # 3 of block # 4 is supplied to the bus 15 by the flash sequencer block 12 via the flash memory interface block 10. Here, data to be written to page # 3 of block # 4 includes user data corresponding to host address # 0, error collection code 28 corresponding to the user data, start page flag 32, start page data 33, and redundant area. 26 is other additional information stored in H.26.
[0173]
Similar to the above, these data are temporarily stored in a register (not shown) provided in the flash memory chip 2-0, and in response to the issuance of an internal write command, predetermined data in page # 3 of block # 4 is stored. Is written at the position of. That is, user data corresponding to the host address # 0 is stored in the user area 25 of page # 3, and the error collection code 28, the start page flag 32, the start page data 33, and other additional information are stored in the redundant area 26. Is stored.
[0174]
This completes the writing process for page # 3 of block # 4.
[0175]
When the writing process for page # 3 in block # 4 is completed, the writing process for page # 4 in block # 4 is then executed.
[0176]
The writing process for page # 4 in block # 4 is performed using internal address # 1, and the procedure is the same as the writing process for page # 3 in block # 4. As a result, the user data corresponding to the host address # 1 is stored in the user area 25 of page # 4, and the error collection code 28, the start page flag 32, the start page data 33, and other additions are stored in the redundant area 26. Information is stored.
[0177]
Thereby, a series of write processing is completed.
[0178]
FIG. 9 is a schematic diagram showing the contents of block # 4 in a state where the series of writing processes is completed.
[0179]
In FIG. 9, the user area 25 is hatched in the portion where user data is stored, and the redundant area 26 is shown only with the corresponding logical block address 29, the start page flag 32, and the start page data 33. The error collection code 28, CRC 31, and other additional information are omitted.
[0180]
As shown in FIG. 9, since user data is stored only in pages # 1 to # 4 of block # 4 and no user data is stored in other pages, the start page in the block is “5”. It can be seen that this value is stored as start page data 33 of page # 3. For this reason, the controller 3 can know that the pages # 5 to # 31 of this block are empty pages by the start page search, and then the pages # 5 to # 31 of the block # 4 from the host computer 5. Even when data writing is requested, the data can be directly written to the pages # 5 to # 31 without performing inter-block transfer.
[0181]
In the above example, the start page data 33 is written to pages (page # 4) other than the previous start page (page # 3) among the pages # 3 and # 4 to be written. May be omitted.
[0182]
Further, in the above example, the corresponding logical block address 29 and CRC 31 are not written in pages # 3 and # 4 to be written, but they may be written in page # 4. However, these data written in page # 4 are not used.
[0183]
In the above example, the start page is obtained directly from the start page storage area # 500. However, after the write operation 1 is performed, the controller 3 is reset so that the contents of the SRAM work area 8 are temporarily stored. If it is erased, the start page cannot be obtained directly from the start page storage area # 500. In this case, since the contents of the start page storage area # 500 become “00001B” due to the creation of the address conversion table 27 executed when the controller 3 is reset, it is necessary to obtain the start page by the above-described start page search. .
[0184]
Next, a case where the first page of the page where user data is to be written does not match the start page will be described.
[0185]
When the first page of the page where user data is to be written does not match the start page
Here, in a state immediately after the above-described write operation 1 is completed, an external write command as a kind of external command and a host address “0000001111010000101B” (from the host computer 5 via the bus 14, the connector 4, and the bus 13) ( A case where the host address # 0) and data to be written to the host address are supplied to the flash memory system 1 will be described as an example.
[0186]
First, the basic operation of the controller 3 when the host address # 0 and the external write command are supplied to the controller 3 is as described above, and the description of the overlapping parts is omitted.
[0187]
In this example, the start page value “00011B (3)” stored in the start page storage area # 500 is compared with the first page of the page in which user data is to be written. In this case, since the first page of the page to which user data is to be written is indicated by the host address # 0, the start page value “00011 (3)” and the lower 5 bits of the host address # 0 “00101 ( 5) "will be compared. In this way, in this example, since the value “00101 (5)” of the lower 5 bits of the host address # 0 exceeds the value “00011 (3)” of the start page, additional data can be written. It is judged that there is.
[0188]
Further, under the control of the microprocessor 6, data is generated by adding 1 to the lower 5 bits of the host address # 0 indicating the last page of the page in which user data is to be written, thereby generating a new start page. . The start page value is temporarily held in the ECC block 11 as start page data. In this case, since the lower 5 bits of the host address # 0 are “00101 (5)”, the start page data stored in the ECC block 11 is “00110 (6)”.
[0189]
The procedure for converting the host address to the internal address is as described above, and the internal address # 0 obtained is “00000000000010000101B”.
[0190]
Further, the start page “00110 (6)” is overwritten in the start page storage area # 500 corresponding to the physical block address storage area # 500.
[0191]
Thus, the conversion from the host address # 0 to the internal address # 0 is completed. As a result, the page # 5 of the block # 4 in the flash memory chip 2-0 is accessed by the internal address # 0.
[0192]
Thereafter, when setting to a register (not shown) included in the flash sequencer block 12 is completed, a series of write operations by the flash sequencer block 12 is executed. In this example, a series of write operations by the flash sequencer block 12 is performed by writing various redundant data to page # 3 of block # 4 in the flash memory chip 2-0, user data and various redundant data for page # 5 of the same block. It is executed in the order of data writing.
[0193]
First, the writing process for page # 3 of block # 4 will be described.
[0194]
Note that the page # 3 of the block # 4 has already been written to the corresponding logical block address 29 in the write operation 1, but the flash memory cells 16 constituting the start page flag 32 and the start page data 33 are Since all are kept in the erased state (logical value = 1), the start page flag 32 and the start page data 33 can be written.
[0195]
In the writing process for page # 3 in block # 4, the flash sequencer block 12 activates the chip selection signal # 0 based on the upper 2 bits of the internal address # 0 stored in a predetermined register. Thereby, the flash memory chip 2-0 is in a state where data can be written. On the other hand, the chip selection signals # 1 to # 3 are kept inactive.
[0196]
Next, the flash sequencer block 12 generates a write address with the lower 5 bits of the internal address # 0 as the previous start page “00011B”, and the lower 18 bits “000000000000010011B” are stored in the internal register. The flash memory interface block 10 is instructed to be supplied to the bus 15 together with the command. As described above, since the chip selection signal # 0 is in the active state, the internal address and the internal read command supplied to the bus 15 are valid only for the flash memory chip 2-0.
[0197]
As a result, the flash memory chip 2-0 is allowed to accept data to be written to page # 3 of block # 4.
[0198]
Next, data to be written to page # 3 of block # 4 is supplied to the bus 15 by the flash sequencer block 12 via the flash memory interface block 10. Here, the data to be written to the page # 3 of the block # 4 is the start page flag 32 and the start page data 33.
[0199]
Similar to the above, such data is temporarily stored in a register (not shown) provided in the flash memory chip 2-0, and in response to the issuance of an internal write command, predetermined data in page # 3 of block # 4 is stored. Is written at the position of. That is, the start page flag 32 and the start page data 33 are stored in the redundant area 26 of page # 3.
[0200]
This completes the writing process for page # 3 of block # 4.
[0201]
When the writing process for page # 3 in block # 4 is completed, the writing process for page # 5 in block # 4 is then executed.
[0202]
The writing process for page # 5 of block # 4 is performed using internal address # 0, and the procedure is as already described repeatedly. As a result, user data corresponding to the host address # 0 is stored in the user area 25 of page # 5, and the error collection code 28, the start page data 33, and other additional information are stored in the redundant area 26. .
[0203]
Thereby, a series of write processing is completed.
[0204]
FIG. 10 is a schematic diagram showing the contents of block # 4 in a state where the series of write processing is completed.
[0205]
In FIG. 10, the user area 25 is hatched in the portion where user data is stored, and the redundant area 26 is shown only with the corresponding logical block address 29, the start page flag 32, and the start page data 33. The error collection code 28, CRC 31, and other additional information are omitted.
[0206]
As shown in FIG. 10, since user data is stored only in pages # 1, # 2, and # 5 of block # 4 and user data is not stored in other pages, the start page in the block Is “6”, and it can be seen that this value is stored as the start page data 33 of page # 3. Therefore, the controller 3 can know that the pages # 6 to # 31 of this block are empty pages by the start page search, and then the pages # 6 to # 31 of the block # 4 from the host computer 5. Even when data writing is requested, the data can be directly written to pages # 6 to # 31 without performing inter-block transfer.
[0207]
In the above example, the start page data 33 is also written to the page # 5 to be written, but this may be omitted.
[0208]
Further, in the above example, the corresponding logical block address 29 and CRC 31 are not written to the page # 5 to be written, but these may be written. However, these are not used as described above.
[0209]
In the above example, the start page is obtained directly from the start page storage area # 500. However, after the write operation 1 is performed, the controller 3 is reset so that the contents of the SRAM work area 8 are temporarily stored. If it is erased, it is necessary to obtain the start page by the above-described start page search.
[0210]
In the above example, the page in which user data is additionally written is page # 5 and the new start page is page # 6. However, the page is added to the page in which user data is additionally written. If # 30 is included and the new start page becomes page # 31, the start page flag 32 of the current start page (page # 3) is set to “0”. This indicates that the start page is not page # 3 but page # 31, and this can be detected by start page search.
[0211]
Write operation 3 (when writing data to the last page # 31)
When writing data to the last page # 31, the start page of the first page # 0 of the block regardless of whether the block is an empty block or a block in which data is already stored (used block) “0” is stored in the flag 32, and “00000B” is stored in the corresponding start page storage area of the address conversion table 27. This indicates that additional writing of data to the block is not possible.
[0212]
The above-described data writing process for the empty block will be described in more detail with a specific example.
[0213]
Here, in a state immediately after the above-described write operation 1 is completed, an external write command, which is a kind of external command, and a host address “00000011111101111111B” (from the host computer 5 via the bus 14, the connector 4 and the bus 13). A case where the host address # 0) and data to be written to the host address are supplied to the flash memory system 1 will be described as an example.
[0214]
First, the basic operation of the controller 3 when the host address # 0 and the external write command are supplied to the controller 3 is as described above, and the description of the overlapping parts is omitted.
[0215]
In this example, the start page value “00011B (3)” stored in the start page storage area # 500 is compared with the first page of the page in which user data is to be written. In this case, since the first page of the page to which user data is to be written is indicated by the host address # 0, the start page value “00011 (3)” and the lower 5 bits of the host address # 0 value “11111 ( 31) ". As described above, in this example, since the value “11111 (31)” of the lower 5 bits of the host address # 0 exceeds the value “00011 (3)” of the start page, additional data can be written. It is judged that there is.
[0216]
The procedure for converting the host address to the internal address is as described above, and the internal address # 0 obtained is “0000000000000001111111B”.
[0217]
Further, in response to the value of the lower 5 bits of the host address # 0 being “11111 (31)”, the value “00000 (0) is stored in the start page storage area # 500 corresponding to the physical block address storage area # 500. ) "Is overwritten.
[0218]
Thus, the conversion from the host address # 0 to the internal address # 0 is completed. As a result, the page # 31 of the block # 4 in the flash memory chip 2-0 is accessed by the internal address # 0.
[0219]
Thereafter, when setting to a register (not shown) included in the flash sequencer block 12 is completed, a series of write operations by the flash sequencer block 12 is executed. In this example, a series of write operations by the flash sequencer block 12 is performed by writing various redundant data to page # 0 of block # 4 in the flash memory chip 2-0, user data and various redundant data for page # 31 of the same block. It is executed in the order of data writing.
[0220]
First, the writing process for page # 0 of block # 4 will be described.
[0221]
Note that the page # 0 of the block # 4 has already been written to the corresponding logical block address 29 in the write operation 1, but the flash memory cell 16 constituting the upper bits of the start page flag 32 is in the erased state. Since (logical value = 1) is maintained, the start page flag can be written.
[0222]
In the writing process for page # 0 of block # 4, the flash sequencer block 12 activates the chip selection signal # 0 based on the upper 2 bits of the internal address # 0 stored in a predetermined register. Thereby, the flash memory chip 2-0 is in a state where data can be written. On the other hand, the chip selection signals # 1 to # 3 are kept inactive.
[0223]
Next, the flash sequencer block 12 generates a write address in which the lower 5 bits of the internal address # 0 are set to “00000B”, and the lower 18 bits “000000000010000000B” together with the internal write command stored in a predetermined register on the bus 15. To the flash memory interface block 10. As described above, since the chip selection signal # 0 is in the active state, the internal address and the internal read command supplied to the bus 15 are valid only for the flash memory chip 2-0.
[0224]
As a result, the flash memory chip 2-0 is allowed to accept data to be written to page # 0 of block # 4.
[0225]
Next, data to be written to page # 0 of block # 4 is supplied to the bus 15 by the flash sequencer block 12 via the flash memory interface block 10. Here, the data to be written to page # 0 of block # 4 is the start page flag 32.
[0226]
Similar to the above, such data is temporarily stored in a register (not shown) provided in the flash memory chip 2-0, and in response to the issuance of an internal write command, predetermined data in page # 0 of block # 4 is stored. Is written at the position of. That is, the start page flag 32 having a value “00” is stored in the redundant area 26 of the page # 0.
[0227]
Thereby, the writing process for page # 0 of block # 4 is completed.
[0228]
When the writing process for page # 0 in block # 4 is completed, the writing process for page # 31 in block # 4 is then executed.
[0229]
The writing process for page # 31 of block # 4 is performed using the internal address # 0, and the procedure is as already described repeatedly. As a result, user data corresponding to the host address # 0 is stored in the user area 25 of the page # 31, and the error collection code 28 and other additional information are stored in the redundant area 26.
[0230]
Thereby, a series of write processing is completed.
[0231]
FIG. 11 is a schematic diagram showing the contents of block # 4 in a state where the series of write processing is completed.
[0232]
In FIG. 11, the user area 25 is hatched in the portion where user data is stored, and the redundant area 26 is shown only with the corresponding logical block address 29, the start page flag 32, and the start page data 33. The error collection code 28, CRC 31 and other additional information are omitted.
[0233]
As shown in FIG. 11, since user data is stored in the last page # 31 of block # 4, there is no start page in the block. For this purpose, the value of the start page flag 32 of the first page # 0 is set to “00”, and the content of the start data storage area # 500 corresponding to the block is set to “00000B”. For this reason, the controller 3 can know that there is no start page in this block, and if the host computer 5 subsequently requests writing of data to any page of the block # 4, the block 3 Transfer is performed.
[0234]
In the above example, the start page is obtained directly from the start page storage area # 500. However, after the write operation 1 is performed, the contents of the SRAM work area 8 are temporarily stored when the controller 3 is reset. If it is erased, it is necessary to obtain the start page by the above-described start page search.
[0235]
As described above, in the flash memory system 1 according to the present embodiment, when data is written to an empty block, the page to which user data is to be written and the page to which user data is to be written are related. Since the corresponding logical block address 29 and CRC 31 are stored in the redundant area 26 of pages # 0 to # 3 and # 31 of the block, an error has occurred in the corresponding logical block address 29 included in the first page (page # 0). Even in this case, it is possible to reliably specify the logical block address corresponding to the block. In addition, since the corresponding logical block address 29 and CRC 31 are not stored in the redundant area 26 of the block that is not the page to which user data is to be written and is not the pages # 0 to # 3 and # 31, it is wasted due to unnecessary writing processing Writing time does not occur. Therefore, a series of processes necessary for data writing can be performed at higher speed.
[0236]
In the present invention, since the concept of a start page is used and it is guaranteed that a page after the start page is always an empty page among a plurality of pages constituting each block, data has already been written. Even if data write to a certain block is requested, if this is a data write request to a page after the start page, data is directly written to the block without performing inter-block transfer. It becomes possible. Therefore, a series of processes necessary for data writing can be performed at higher speed.
[0237]
Moreover, in the flash memory system 1 according to the present embodiment, the start page data 33 is stored in the redundant area 26 of each page, and the start page is expressed by a link using the start page data 33. When creating the conversion table 27, it is only necessary to read the first page (page # 0) of each block. Since such a reading process is a process normally performed at the time of initial setting (reset) of the controller 3, the time required for the initial setting operation is not increased by applying the present invention.
[0238]
In the flash memory system 1 according to the present embodiment, the start page of the block in which data has been once written is stored in the corresponding start page storage area. Is performed, the start page can be obtained very quickly.
[0239]
The present invention can be realized as a PC card based on a unified standard published by PCMCIA (Personal Computer Memory Card International Association). Furthermore, in recent years, with the development of high integration technology of semiconductor devices, more compact memory cards such as “CompactFlash (registered trademark of SanDisk Corporation)” proposed by CFA (Compact Flash Association), MultiMediaCard Association, etc. The present invention can be applied to “MMC (MultiMediaCard)” proposed by Sony Corporation, “Memory Stick (trademark of Sony Corporation)” proposed by Sony Corporation, and the like.
[0240]
The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the invention described in the claims, and these are also included in the scope of the present invention. Needless to say.
[0241]
For example, in the flash memory system 1 according to the above embodiment, when data is written to an empty block, it is stored in the redundant area 26 of pages # 0 to # 3 of the block regardless of the page to which user data is to be written. The corresponding logical block address 29 and the CRC 31 are stored, but the target to write the corresponding logical block address 29 and the CRC 31 is not limited to the pages # 0 to # 3 regardless of the page to which the user data is to be written. Any continuous page including page # 0 may be used. For example, pages # 0 to # 2 may be used. Also in this case, when an error in the corresponding logical block address 29 is detected in the last page (excluding page # 31) in which the corresponding logical block address 29 and CRC 31 are written, the block is handled as a defective block. become.
[0242]
In the flash memory system 1 according to the above embodiment, the start page data 33 is stored in the redundant area 26 of each page, and the start page is expressed by a link using the start page data 33. The start page representation method is not limited to this, and the start page may be represented by other methods. For example, for each block, information on all the empty pages may be developed in the address conversion table 27, and additional data may be written based on this information. In this case, unlike the flash memory system 1 according to the above embodiment, since the information about all the empty pages is used, additional writing of data is performed more effectively, and the frequency of transfer between blocks is further increased. Can be reduced. However, in this case, since it takes a long time to develop the information regarding all the empty pages in the address conversion table 27, the initial setting operation of the controller 3 is delayed.
[0243]
In the flash memory system 1 according to the above embodiment, the 2-bit start page flag 32 is used. However, the start page flag 32 is set to 1 bit, and in page # 0, does the start page exist in the block? May be used to display whether or not the corresponding start page is valid on pages # 1 to # 30.
[0244]
Further, in the flash memory system 1 according to the above embodiment, in the start page search, if the referenced start page flag 32 is “x0”, the search is terminated and the page is set as the start page. The start page data 33 is referred to, and if the referenced start page data 33 is “11111 (31)”, the search may be terminated and the page may be used as the start page. In this case, at least for the page whose start page data 33 is “11111 (31)”, the start page data “11111 (31)” indicates the end of the start page search, or the start page is the page. It is necessary to distinguish whether it indicates # 31 using the start page flag 32 or the like.
[0245]
In the flash memory system 1 according to the above embodiment, in the start page search, there is no restriction on the page to which the reference destination start page flag 32 belongs, but the page number of the page to which the reference destination start page flag 32 belongs. Is smaller than the page number of the page to which the reference source start page flag 32 belongs, it may be determined that there is an error in the corresponding start page data 33 and error processing may be performed.
[0246]
Furthermore, in the flash memory system 1 according to the above embodiment, the start page search has no limit on the number of references, but this is limited to a predetermined number (for example, 30 times), and if this is exceeded, Alternatively, it may be determined that there is an error in at least one start page data 33 and error processing may be performed.
[0247]
Further, in the flash memory system 1 according to the above embodiment, each block is configured by 32 pages, but the number of pages configuring each block is not limited to 32, and other numbers, for example, It may be 16 or 64. The present invention can obtain a more remarkable effect as the number of pages constituting each block increases.
[0248]
Furthermore, in the flash memory system 1 according to the above embodiment, when data is written to an empty block, even if the page to which user data is to be written is other than pages # 0 to # 3 and # 31, the redundancy is provided. The corresponding logical block address 29 and CRC 31 are stored in the area 26, but they may be omitted.
[0249]
Further, in the flash memory system 1 according to the above embodiment, the address conversion table 27 related to all physical blocks in which data is stored is expanded on the SRAM work area 8. In the present invention, all these physical blocks are stored. It is not essential to expand the address conversion table related to the block, and only a part of them may be expanded. In this case, the storage capacity required for the SRAM work area 8 can be reduced. However, when only the address translation table related to some physical blocks is expanded in this way, it is necessary to update the address translation table every time access to a physical block not included in the address translation table is requested. .
[0250]
In the above embodiment, the flash memory system 1 has a card shape, and the four flash memory chips 2-0 to 2-3 and the controller 3 are integrated in one card. The flash memory system according to the present invention is not limited to a card shape, and may be another shape, for example, a stick shape.
[0251]
Furthermore, in the above embodiment, the flash memory system 1 is configured by integrating the four flash memory chips 2-0 to 2-3 and the controller 3 in one card. 2-0 to 2-3 and the controller 3 do not have to be integrated in the same casing, and may be packaged in separate casings. In this case, the housing in which the flash memory chips 2-0 to 2-3 are packaged and the housing in which the controller 3 is packaged have connectors for realizing electrical and mechanical connections with the other. With such a connector, the housing in which the flash memory chips 2-0 to 2-3 are packaged is detachably attached to the housing in which the controller 3 is packaged. Furthermore, the flash memory chips 2-0 to 2-3 do not have to be integrated in the same casing, and may be packaged in separate casings.
[0252]
In the flash memory system 1 according to the above embodiment, each of the flash memory chips 2-0 to 2-3 is a semiconductor chip having a storage capacity of 128 Mbytes (1 Gbit). The storage capacity of −0 to 2-3 is not limited to 128 Mbytes (1 Gbit), and may be a different capacity, for example, 32 Mbytes (256 Mbits).
[0253]
Further, in the flash memory system 1 according to the above embodiment, 512 bytes are set as one page, which is the minimum access unit. However, the minimum access unit is not limited to 512 bytes, and has a different capacity. Also good.
[0254]
In the flash memory system 1 according to the above embodiment, each flash memory cell 16 configuring the flash memory chips 2-0 to 2-3 holds 1-bit data. By controlling the amount of electrons to be injected in a plurality of stages, data of 2 bits or more may be held.
[0255]
In the flash memory system 1 according to the above embodiment, the erased block queue 30 is configured by assigning two queues to the flash memory chips 2-0 to 2-3, respectively. The number of queues assigned to the flash memory chips 2-0 to 2-3 is not limited to two, but may be other numbers, for example, one or eight.
[0256]
Further, in the flash memory system 1 according to the above embodiment, a NAND flash memory chip is used as the flash memory chip 2, but the flash memory that can be controlled by the present invention is not limited to the NAND type. It is also possible to control other types, for example, AND type flash memories.
[0257]
Furthermore, in the present invention, means does not necessarily mean a physical means, but includes cases where the functions of each means are realized by software. Further, the function of one means may be realized by two or more physical means, or the functions of two or more means may be realized by one physical means.
[0258]
【The invention's effect】
As described above, according to the present invention, even if the corresponding logical address is not written correctly or the value of the already written corresponding logical address has changed for some reason, the logical address and the physical address It is possible to provide a memory controller, a flash memory system, and a flash memory control method capable of recognizing a correct correspondence relationship with an address.
[Brief description of the drawings]
FIG. 1 is a block diagram schematically showing a flash memory system 1 according to a preferred embodiment of the present invention.
FIG. 2 is a cross-sectional view schematically showing the structure of each flash memory cell 16 constituting the flash memory chips 2-0 to 2-3.
FIG. 3 is a cross-sectional view schematically showing a flash memory cell 16 in a write state.
FIG. 4 is a diagram schematically showing a structure of an address space of the flash memory chip 2-0.
FIG. 5 is a diagram schematically showing a data structure of a redundant area 26;
FIG. 6 is a schematic diagram showing a data structure of an address conversion table 27 stored in the SRAM work area 8;
7 is a schematic diagram showing a data structure of an erased block queue 30 stored in the SRAM work area 8. FIG.
FIG. 8 is a schematic diagram illustrating a state in which data is written in pages # 1 and # 2 of block # 4.
FIG. 9 is a schematic diagram illustrating a state in which data is written in pages # 1 to # 4 of block # 4.
FIG. 10 is a schematic diagram illustrating a state in which data is written in pages # 1, # 2, and # 5 of block # 4.
FIG. 11 is a schematic diagram illustrating a state in which data is written to pages # 1, # 2, and # 31 of block # 4.
[Explanation of symbols]
1 Flash memory system
2-0 to 2-3 flash memory chip
3 Controller
4 Connector
5 Host computer
6 Microprocessor
7 Host interface block
8 SRAM work area
9 buffers
10 Flash memory interface block
11 ECC block
12 Flash sequencer block
13-15 Bus
16 Flash memory cell
17 P-type semiconductor substrate
18 Source diffusion region
19 Drain diffusion region
20 Tunnel oxide film
21 Floating gate electrode
22 Insulating film
23 Control gate electrode
24 channels
25 User area
26 Redundant area
27 Address conversion table
28 Error collection code
29 Corresponding logical block address
30 Erased block queue
31 Cyclic redundancy bit for logical block address
32 Start page flag
33 Start page data

Claims (10)

A memory controller for accessing a memory composed of a plurality of blocks each including a plurality of pages based on a block address and a page address, in response to a request for writing user data specifying a host address from a host computer Address generating means for generating the block address and the page address based on the host address ; additional information generating means for generating additional information corresponding to the block address; a page specified by the page address and the first page without writing the block address and the additional information in any neither page of a predetermined plurality of pages continuous comprising, at least, writing hand writing the block address and the additional information with respect to said predetermined plurality of pages Memory controller with a door.   The memory controller according to claim 1, wherein the additional information is information capable of detecting an error included in the block address.   3. The memory controller according to claim 1, wherein the predetermined plurality of pages are at least four consecutive pages. Read means for reading the block address and the additional information written in the first page, and an error for determining whether or not the block address read based on the read additional information contains an error Detecting means, and in response to the error detecting means determining that the read block address contains an error, the reading means writes to the next page of the first page 4. The memory controller according to claim 1, wherein the read block address and the additional information are read out. 5. The memory according to claim 1, wherein the writing unit writes the block address and the additional information to a page specified by the page address and the predetermined plurality of pages. 6. controller. A memory controller for accessing a memory composed of a plurality of blocks each including a plurality of pages based on a host address supplied from a host computer, wherein the address generation means generates a logical block address and a page address based on the host address If, in response to said determining means for physical block address to determine whether there corresponding to the logical block address, a physical block address corresponding to the logical block address by the determining means determines that there is no Empty block selecting means for selecting an empty block from the plurality of blocks, additional information generating means for generating additional information capable of detecting an error in the logical block address, and an empty block selected by the empty block selecting means. Configure multiple In the page, at least the predetermined plurality of pages without writing the logical block address and the additional information in a page that is not any of the continuous predetermined plurality of pages including the page specified by the page address and the first page. A memory controller comprising: a writing means for writing the logical block address and the additional information to a page. The determination unit further includes a table creating unit that identifies an error-free logical block address based on the additional information among the logical block addresses written in the predetermined plurality of pages, and creates an address conversion table based on the specified logical block address. The memory controller according to claim 6, wherein the determination is performed by referring to the address conversion table. A flash memory including a plurality of blocks each including a plurality of pages; and a memory controller that accesses the flash memory based on a host address supplied from a host computer, the controller including a block address based on the host address Address generating means for generating a page address, additional information generating means for generating additional information corresponding to the block address in response to a request for writing user data from the host computer, and the page address. The block address and the additional information are not written to a page that is not one of the consecutive predetermined pages including the specified page and the first page, and at least the block address for the predetermined plurality of pages. And a flash memory system comprising: a writing means for writing the additional information. In response to a request from the host computer to write user data specifying a host address, an address generation step for generating a block address and a page address based on the host address, and additional information corresponding to the block address A step of generating additional information , and at least the predetermined address without writing the block address and the additional information in a page that is not any of a plurality of consecutive predetermined pages including the page specified by the page address and the first page. And a write step for writing the block address and the additional information to a plurality of pages. 10. The flash memory control method according to claim 9, further comprising a read step of reading the block address written by the write step until an error-free block address is obtained for the predetermined plurality of pages. .

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