JP3834074B2 - Method for forming ohmic contacts in complementary semiconductor devices - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates generally to semiconductor devices, and more particularly to complementary semiconductor devices.
[0002]
[Prior art]
Complementary semiconductor devices, particularly III-V complementary heterostructure field effect transistors (CHFETs) or complementary heterostructure insulated gate field effect transistors (CHIGFETs) are extremely useful in low power, low voltage, high speed applications I know that. For example, US Pat. No. 4,729,000 “Low Power AlGaAs / GaAs Complementary FETs Incorporating InGaAs N-channel Gates,” Abrokwah and US Pat. No. 4,814,851 “High Transconductance Complementary (Al, Ga) As / GaAs. Heterostructure
See Insulated Gate Field-Effect Transistors, "Abrokwah et al. In the prior art, complementary gallium arsenide (GaAs) heterostructure devices using self-aligned ion implantation technology have been disclosed. Therefore, in devices such as CMOS, which use a wide band gap insulator such as aluminum gallium arsenide (AlGaAs) or aluminum indium arsenide (AlInAs) to seal high mobility two-dimensional electron or hole gas in the channel. A two-dimensional gas is formed in proximity to the heterojunction of a wide bandgap material insulator and a narrow bandgap material channel, a common channel material being pseudocrystalline In _X Ga _1-X As. However, in the prior art, the ohmic contact used to electrically connect the active region of the device There are a number of disadvantages for the other metallization.
[0003]
[Problems to be solved by the invention]
That the devices are complementary means that they include N-type and P-type devices on the same substrate. The general ohmic contact metallization of the prior art is different for N-type and P-type devices. In the case of the N type, gold germanium nickel (AuGeNi) is used. In the case of the P type, gold zinc nickel (AuZnNi) or gold zinc gold (AuZnAu) is used. Both ohmic contacts utilize Au metallization to reduce resistance, resulting in some drawbacks. Au-based ohmic contacts cannot be etched. Therefore, it must be formed on the device by a lift-off process. As is well known in the art, the lift-off method involves a relatively low yield and poor patterning, which limits the shape of the device to relatively large dimensions. The large dimensions reduce the maximum number of devices that can be installed in a given space.
[0004]
Also, conventional Au-based ohmic contacts have the disadvantage that they are not compatible with the latest VLSI aluminum metallization utilized in multilayer integrated circuit interconnects. This incompatibility is due to the fact that Au-based ohmic contacts cannot provide stable ohmic contacts in the temperature range required for Al multilayer technology. Specifically, a typical Al-based interconnect process is performed at about 500 ° C. or higher, but Au-based ohmic contact cannot provide a stable ohmic contact at about 470 ° C. or higher. This limits the commercial use of complementary devices with conventional Au-based ohmic contacts. Furthermore, over time, Au tends to react with Al, creating a problem called purple plaque, which ultimately causes device failure.
[0005]
Another drawback of conventional ohmic contacts is that the complex reaction between Au and GaAs makes the contact structure unsuitable.
[0006]
In addition, the conventional ohmic contact has a distinct disadvantage in that two different materials are used for N-type and P-type devices. As is well known, the use of discrete materials increases the complexity of device processing, which leads to higher costs, increased cycle times, increased safety risks, reduced yields, and the like.
[0007]
It is therefore suitable for III-V complementary devices that can be used in both N-type and P-type devices and is compatible with the latest VLSI multilayer aluminum interconnects and avoids all the above-mentioned problems of the prior art. Ohmic contact is required. It is further desirable to provide a complementary heterostructure field effect device that utilizes such ohmic contacts.
[0008]
[Means for Solving the Problems]
The scope of the present invention includes III-V complementary semiconductor devices using compatible ohmic contacts. Specifically, the preferred embodiment includes an N-channel device that includes an N-type device gate . The N-channel device includes a first heterostructure isolation region under the N-type device gate and a first heterostructure channel region under the first heterostructure isolation region. In addition, N-type source and N-type drain regions are provided on the sides of the N-type device gate . The N-type source region and the N-type drain region extend to the first heterostructure channel region. A first ohmic region of a first material that provides a substantially stable ohmic contact in the temperature range of 500-600 ° C. is in contact with the N-type source region, and a similar second ohmic region is in contact with the N-type drain region. To do.
[0009]
In addition, this preferred embodiment includes a P-channel device having a P-type device gate . The P-channel device includes a second heterostructure isolation region under the P-type device gate and a second heterostructure channel region under the second heterostructure isolation region. P-type source and drain regions are provided on the sides of the P-type device gate . The P-type drain and P-type source regions extend to the second heterostructure channel. The third ohmic region made of the first material is in contact with the P-type source region, and the fourth ohmic region made of the first material is in contact with the P-type drain region .
[0010]
Furthermore, the scope of the present invention includes methods of manufacturing complementary heterostructure devices. A heterostructure channel region is formed. The heterostructure insulating region is formed on the channel region. An N-type device gate and a P-type device gate are formed on the heterostructure insulating region. N-type source and N-type drain regions are formed on either side of the N-type device gate and extend to the channel region. P-type source and P-type drain regions are formed on both sides of the P-type device gate and extend to the channel region. The first, second, third and fourth ohmic regions made of materials suitable for providing ohmic contact in the temperature range of 500-600 ° C. are an N-type source region, an N-type drain region and a P-type source, respectively. Formed to contact the region and the P-type drain region . Complementary devices are interconnected with standard VLSI aluminum interconnect metallization using methods well known in the silicon integrated circuit industry.
[0011]
【Example】
In general, the preferred embodiment of the present invention is a complementary GaAs heterostructure field effect transistor that overcomes the shortcomings of the prior art and establishes manufacturable devices and methods compatible with the latest VLSI interconnect technology. . This preferred embodiment is constituted by the same ohmic contact material, which is nickel germanium tungsten (NiGeW), which is the ohmic contact for both N-type and P-type devices.
[0012]
NiGeW has been found to be suitable as a contact to the N-type region. The use of NiGeW as an ohmic contact is shown, for example, in co-pending applications US patent application Ser. Nos. 07 / 902,244 and 07 / 902,245. However, a typical complementary GaAs heterostructure device has an insulating layer made of a material such as AlGaAs having a high Al concentration. If this insulating layer is P-doped to a level of about 10 ¹⁸ / cc, as is the case with conventional inter-type devices, NiGeW is generally unsuitable. Such a NiGeW contact to a P-type device is inappropriate because Ge is an N-type impurity that cancels out. Therefore, for example, in the prior art, AuZnNi or AuZnAu is used as an ohmic contact to the P-type region, and Zn is doped at a high concentration.
[0013]
However, the present invention utilizes an N-type NiGeW ohmic contact that is also common to the P-type. In particular, the preferred embodiment utilizes a high co-implant of suitable implant material to achieve low contact resistance for complementary structure P-type devices, A shallow high doping concentration is achieved in the P-type contact region. The contact is suitable for AlGaAs / GaAs heterostructures where the Al content can be increased as required.
[0014]
This novel non-obvious ohmic contact can be etched, such as by the method disclosed in co-pending US patent application Ser. No. 07 / 092,244. Therefore, the lift-off method is not necessary. Therefore, a high yield and a reduction in device shape are possible.
[0015]
Furthermore, the preferred devices manufactured according to the present invention are compatible with the latest Al-based VLSI interconnect methods. Also, the ohmic contact of the present invention is as smooth as a mirror, reflective and free of bumps. In addition, the same ohmic material can be used throughout the complementary device, which provides significant advantages over the prior art. Therefore, the process is greatly simplified. The present invention can be applied to optical devices such as digital and analog III-V semiconductors, complementary circuits including FETs, HBTs, semiconductor LEDs, and lasers. Therefore, it has a wide range of uses for communication, computation and display.
[0016]
FIG. 1 is a cross-sectional view showing an epitaxial semiconductor structure of a preferred embodiment of the present invention. A GaAs substrate 10 is provided. The GaAs substrate 10 is a high resistance material, preferably a type of material grown by the LEC (liquid encapsulated Czocrolski) method. The GaAs substrate 10 is preferably about 25 mils thick and has a sheet resistance of about 10 ⁹ to 10 ¹⁰ ohms / square. An undoped GaAs buffer layer 12 is epitaxially grown on the GaAs LEC substrate 10 by methods well known in the art. The GaAs buffer layer 12 is preferably about 2,000 mm thick. The GaAs buffer layer 12 provides a clean crystal lattice for forming the active layer of the device. In the GaAs buffer layer 12, a very narrow delta doping layer 14 is inserted. The delta doping layer 14 is preferably made of silicon (Si) and has a carrier concentration of 2-4 × 10 ¹¹ cm ⁻² . In the preferred embodiment, the delta doping layer 14 is provided approximately 30 mm from the top surface of the GaAs buffer layer 12. Doping layer 14 serves to provide some of the carriers to the N-channel device and adjust the threshold voltage of both the N-channel and P-channel devices.
[0017]
The FET channel layer 16 is formed on the GaAs buffer layer 12. The channel layer 16 is preferably made of undoped InGaAs having a molar ratio of 20% In and 80% Ga. In the preferred embodiment, the channel layer 16 is about 130 inches thick.
[0018]
An insulating layer 18 is epitaxially grown on the channel layer 16. Preferably, this insulating layer 18 is composed of undoped AlGaAs. A preferred molar ratio is 75% Al, 25% Ga. This layer has a thickness of about 250 mm.
[0019]
An undoped GaAs cap layer 20 is grown on the insulating layer to a thickness of about 30 mm. This GaAs cap layer is for preventing the AlGaAs insulating layer 18 from being oxidized.
[0020]
Accordingly, the epitaxial semiconductor structure of FIG. 1 provides a heterostructure for forming a suitable complementary heterostructure field effect transistor device. As is apparent, this heterostructure is composed of GaAs / InGaAs / AlGaAs.
[0021]
2-9 illustrate the preferred method of the present invention for fabricating a preferred complementary heterostructure field effect transistor.
[0022]
In FIG. 2, an optional field insulator 30 is provided to protect the substrate material. A window is opened in the field insulator by known lithographic and reactive ion etching (RIE) methods. These windows provide access to the active device areas 32, 33.
[0023]
In FIG. 3, an N-type device gate 40 and a P-type device gate 42 are formed in regions 32 and 33, respectively. Specifically, in a preferred embodiment, about 3,000 to 4,000 liters of TiWN layer is deposited by reactive RF sputtering. This TiWN functions as a Schottky contact gate of the field effect device. The gates 40 and 42 are a mixture of SF ₆ , CHF ₃ and He, and are formed by the RIE method.
[0024]
FIG. 4 shows the formation of a pair of sidewall spacers 50, 52 on either side of the gates 40,42. Providing side walls 50, 52 is preferred but not necessary. Sidewalls 50 and 52 serve to align the source and drain regions at a later stage in order to improve the overall device performance parameters. In the preferred embodiment, the sidewalls 50, 52 are made of SiON or SiN / SiO ₂ and have a total thickness of about 4,000 mm. The side walls 50 and 52 are formed by a general processing method. A high pressure anisotropic RIE process is used for etching. The resulting side walls 50, 52 have a size of about 3,000 cm on either side of each gate by RIE.
[0025]
FIG. 5 shows the deposition of a protective SiN layer 60 covering field insulator region 30, active device regions 32 and 33, gates 40 and 42 and spacers 50 and 52. The SiN layer 60 serves to protect the wafer surface from subsequent processing steps. Layer 60 is preferably deposited to a thickness of about 500 mm by standard CVD methods.
[0026]
FIG. 6 illustrates forming an N-type source region 70 and an N-type drain region 72 in the active device region 32 adjacent to the N-type device gate 40 . Regions 70 and 72 are formed by a well-known processing method using Si implantation to obtain a sheet resistance of about 350 ohms / square. The implantation is performed through the SiN layer 60. Each of the N-type source region 70 and the N-type drain region 72 preferably extends about 2,000 mm to the inside of the substrate, and extends at least to the channel layer 16, preferably to the inside of the buffer layer 12. Alternatively, in order to improve the access series resistance of the N-channel FET, a lightly doped region may be provided directly self-aligned with the N-type device gate 40 using a lightly doped Si implant prior to sidewall formation. Good.
[0027]
FIG. 7 illustrates forming a P-type source region 80 and a P-type drain region 82 in the active region 33 adjacent to the P-type device gate 42 . P-type regions 80 , 82 are formed utilizing simultaneous implantation of fluorine (F) and beryllium (Be) to provide a sheet resistance of about 1,000-2,000 ohms / square. Each of the P-type source region 80 and the P-type drain region 82 preferably extends about 2,000 mm to the inside of the substrate, and extends at least to the channel layer 16, preferably to the inside of the buffer layer 12.
[0028]
FIG. 8 shows that these regions 80 and 82 are further doped to make P-type source region 80 and P-type drain region 82 compatible for the ohmic contact used in the preferred embodiment of the present invention. . Specifically, NiGeW is typically used only as an N-type ohmic contact metal because it contains Ge, which is an N-type dopant for GaAs. However, the present invention also utilizes NiGeW as a P-type ohmic contact. Therefore, at the stage shown in FIG. 8, the P-type source region 80 and the P-type drain region 82 are provided with shallow high-concentration P-type regions 81 and 83 , respectively, so that further high-concentration doping is performed. It is preferred that a sheet resistance of 250 to 400 ohm / square is thereby obtained.
[0029]
An optimized P-type dopant distribution can be achieved using co-implantation of F and Be, As and Be, P and Be, N and Be, or Kr and Be. This co-implantation improves Be activation and reduces Be diffusivity. In the case of F and Be, the peak doping of 5 × 10 ¹⁹ cc ⁻¹ is a fast annealing temperature of 700 ° to 850 ° C. as described below, with an implantation concentration of 10 ¹⁴ cm ⁻² or more and an energy of 50 keV or less. Achieved by: Therefore, P-type contact can be obtained even when N-type ohmic metal is used.
[0030]
Although not shown, the next step in the preferred method is a rapid thermal anneal used to activate P-type and N-type sources and drains . The annealing conditions are preferably temperatures from 700 ° C to 850 ° C, minimize the generation of slip-lines in large wafers, and P-type HFET sub-thresholds.
intended to reduce current).
[0031]
FIG. 9 shows the formation of an oxygen isolation (ISO) region 90 in the epitaxial substrate between the N-channel device and the P-channel device. The ISO region 90 serves to insulate each device. It will be appreciated that the N-type and P-type devices shown are two of many identical devices formed on a particular die. Accordingly, region 90 is shown at both ends of the figure to show separation from nearby devices not shown. ISO utilizes a rapid thermal annealing method, which is preferably performed at 550 ° C. for 6 seconds.
[0032]
FIG. 9 shows an additional insulator cap 100 that covers the entire device. The cap 100 is provided for protection in subsequent processing steps. Insulator cap 100 is formed to a thickness of about 3,500 mm using conventional processing methods.
[0033]
FIG. 10 illustrates the ohmic contact of the preferred embodiment of the present invention. Although not shown, insulator layer 100 and insulator layer 60 provide access for ohmic contact deposition to provide N-type source, N-type drain, P-type source and P-type drain regions 70, 72, Etching is removed in the region above 80 and 82 . Ni layer 120, Ge layer 122 and W layer 124 are sputter deposited over the entire device to define the contact area. For convenience of explanation, an ohmic contact to the N-type source region 70 is represented as an ohmic region 117. Similarly, ohmic contact to P-type source region 80 is represented as ohmic region 119. These illustrate all ohmic contacts.
[0034]
The ohmic regions 117 and 119 as an example are formed as follows. In embodiments that use the lift-off method to define the contact area, a thin layer of metal is required. In this case, the Ni layer 120 is 100 to 300 mm, and the Ge layer 122 is 100 to 300 mm. Finally, the W layer 124 is deposited to a thickness of about 1,000 mm.
[0035]
Note that it is also desirable to utilize etching to define the contact area. If the contact is defined by an etching method, for example, W and Ge are well known solvents such as RIE of W and Ge, buffered oxide etchant (BOE) or hydrochloric acid (HCl) for nickel. Appropriate thickness can be achieved. Suitable methods are disclosed in co-pending US patent application Ser. No. 07 / 902,244, although other methods can be used.
[0036]
For N-channel regions, ohmic contact materials are effective in Si-doped N-type source and drain regions as long as the sheet resistance is 1,000 ohms / square or less. The ohmic contact is sputter deposited onto the implanted and annealed semiconductor after pre-cleaning with BOE and HCl using wet etching.
[0037]
When sintered in the temperature range of 500 ° C. to 600 ° C., stable NiGe and NiAs compounds form the interface between the ohmic metal and the semiconductor material. NiAs compounds can be formed at low temperatures and interspersed within the NiGe matrix. Both of these compounds form a low barrier to the semiconductor and allow tunnel conduction. In order to utilize NiGeW ohmic contacts in P-type devices, a high concentration of P-type doping is applied to the P-type III-V heterostructure by shallow ion implantation as described in FIG. This causes the NiGeW metal to contact the heavily doped P-type region despite the N-type Ge dopant diffusing into the semiconductor.
[0038]
The W layer 124 which is a refractory metal may be another stable refractory metal such as WN, TiW or TiWN. The refractory cap provides a barrier to As diffusion into the Al metallization used in VLSI interconnects as described above.
[0039]
FIG. 11 shows P-type Al _{. 75} Ga _{. 25} As / In _{. 20} Ga _. Figure 2 shows the typical contact resistance of NiGeW ohmic contact in ₈₀ As structure. The resistance is shown relative to the sheet resistance of the co-implanted F / Be P regions 81,83. Contact resistance values of 0.22 to 0.85 ohm-mm can be achieved by changing the surface concentration of P-type doping. Thus, the present invention shows that the same NiGeW ohmic contact previously used only for N-type contacts can be usefully utilized in complementary III-V devices that also require P-type contacts .
[0040]
FIG. 12 shows the advantage over temperature of ohmic contact according to the present invention. This graph shows that NiGew ohmic contacts maintain effective ohmic contact resistance in the temperature range of 500-600 ° C, whereas conventional Au-based ohmic contacts rapidly degrade even below 500 ° C. Modern aluminum VLSI interconnect processes are performed at temperatures above 500 ° C. Therefore, the conventional Au ohmic contact cannot be used, but the ohmic contact according to the present invention can be used.
[0041]
By now it should be appreciated that a novel non-obvious complementary semiconductor device and method of manufacturing the same have been provided. This device is particularly advantageous when used in the latest VLSI aluminum interconnect methods. Furthermore, providing the same form of ohmic contact in both N-type and P-type devices greatly simplifies the process.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a portion of a substrate of a preferred embodiment of the present invention.
FIG. 2 is a cross-sectional view illustrating a preferred method of the present invention immediately after placing an optional field insulator.
FIG. 3 is a cross-sectional view illustrating the preferred method of the present invention immediately after the device gate is formed.
FIG. 4 is a cross-sectional view illustrating the preferred method of the present invention immediately after optional gate sidewalls are formed.
FIG. 5 is a cross-sectional view illustrating a preferred method of the present invention immediately after a field insulator layer is formed.
FIG. 6 is a cross-sectional view illustrating the preferred method of the present invention immediately after the N-type source and N-type drain regions are formed.
FIG. 7 is a cross-sectional view illustrating a preferred method of the present invention immediately after formation of a P-type source and P-type drain region .
FIG. 8 is a cross-sectional view illustrating a preferred method of the present invention immediately after the P-type source and P-type drain regions are further doped.
FIG. 9 is a cross-sectional view illustrating a preferred method of the present invention immediately after an insulating region is formed.
FIG. 10 is a cross-sectional view illustrating a preferred method of the present invention immediately after an ohmic contact is formed.
FIG. 11 is a graph showing a relationship between a general ohmic contact resistance value and a P-type region sheet resistance value.
FIG. 12 is a graph showing ohmic contact resistance as a function of temperature and comparing a conventional ohmic contact with a preferred ohmic contact.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 GaAs substrate 12 GaAs buffer layer 14 Delta doping layer 16 FET channel layer 18 Insulating layer 20 GaAs cap layer 30 Field insulator 32, 33 Active device region 40 N type device gate 42 P type device gate 50, 52 Side wall spacer 60 Protective SiN layer 70 N-type source region 72 N-type drain region 80 P-type source region 81, 83 P-type region 82 P-type drain region 90 Oxygen isolation (ISO) region 100 Dielectric cap 117,119 Ohm region 120 Ni layer 122 Ge Layer 124 W layer

Claims (4)

A method of forming an ohmic contact to a complementary semiconductor device comprising:
Forming an N-type region (70) in an epitaxial structure of gallium arsenide;
Forming a P-type region (80) in the epitaxial structure of gallium arsenide;
Doping the P-type region with a large amount of impurities by co-implanting fluorine and beryllium into the P-type region to produce a sheet resistance in the range of 250-400 ohms / square;
Activating the N-type region and the P-type region by thermal annealing;
Depositing nickel on the N-type region and the P-type region and depositing germanium on the nickel ; and depositing tungsten on the deposited nickel and germanium;
A method comprising the steps of: A method of forming an ohmic contact to a complementary semiconductor device comprising:
Forming an elongated N-type region (70) in the III-V semiconductor structure;
Forming an elongated P-type region (80) in the III-V semiconductor structure;
Doping the P-type region with a large amount of impurities by co-implanting fluorine and beryllium into the P-type region to produce a sheet resistance in the range of 250-400 ohms / square;
Forming a first ohmic region (117) comprising nickel, germanium formed on the nickel, and tungsten formed on the germanium in ohmic contact with the N-type region; and Forming a second ohmic region (119) consisting of nickel, germanium formed on the nickel, and tungsten formed on the germanium in ohmic contact;
A method comprising the steps of: A method of fabricating a III-V complementary heterostructure device having non-gold ohmic contacts comprising:
Forming a heterostructure channel region (16);
Forming a heterostructure insulating region (18) on the heterostructure channel region;
Forming an N device gate (40) and a P device gate (42) on the heterostructure insulating region (18);
Forming an N source region (70) on the first side of the N device gate (40) extending to the heterostructure channel region (16);
Forming an N drain region (72) extending to the heterostructure channel region (16) on a second side of the N device gate (40);
Forming a P source region (80) extending to the heterostructure channel region (16) on a first side surface of the P device gate (42), wherein the P source region contains fluorine and beryllium together; Doping a large amount of impurities by implantation to produce a sheet resistance in the range of 250-400 ohms / square;
Forming a P drain region (82) extending to the heterostructure channel region (16) on a second side surface of the P device gate (42), wherein the P drain region comprises fluorine and beryllium. Doping a large amount of impurities by implantation to produce a sheet resistance in the range of 250-400 ohms / square; and said N source region (70), N drain region (72), P source region (80) And P drain region (82), respectively, to form first, second, third and fourth ohmic regions (117, 119) made of nickel, germanium and tungsten, said germanium being said nickel And the tungsten is formed on the germanium;
A method comprising the steps of: A method of fabricating a III-V complementary heterostructure device having non-gold ohmic contacts comprising:
An N-type device comprising an N-type region and a first ohmic region (117) consisting of nickel, germanium formed on the nickel and tungsten formed on the germanium, in ohmic contact with the N-type region ; A P-type device comprising a P-type region and a second ohmic region (119) consisting of nickel, germanium formed on the nickel and tungsten formed on the germanium in ohmic contact with the P-type region ; Providing a complementary field effect device wherein the P-type region is doped with a large amount of impurities by co-implanting fluorine and beryllium to produce a sheet resistance in the range of 250-400 ohms / square;
A method comprising the steps of:

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