JP3793542B2 - Semiconductor memory device - Google Patents

Description

Industrial application fields

  The present invention relates to a semiconductor memory device using a flash memory, and more particularly to writing data continuously in a semiconductor disk device using a flash memory.

  In the present invention, for example, a plurality of flash EEPROMs that can be read and written in units of words with a plurality of bits as one word and that can be electrically erased in units of chips or in units of a plurality of words are mounted. 1 word of data is written into an arbitrary flash memory mounted on the writing device, and the flash memory in which the writing has been performed can write the next 1 word of data for a certain period of time. In the meantime, one word of data is written in a flash memory different from the flash memory in which writing is performed, which is mounted on the device.

  FIG. 8 shows timing waveforms for data writing in a flash memory in which writing and erasing are performed using the command control method according to the prior art. In the figure, Vcc is a power supply voltage of the flash memory, and +5 V is always applied. Vpp is a write power supply, and a potential higher than the power supply voltage Vcc is applied when data is written to the flash memory. The address designates a data write area of the flash memory in units of bytes. OE is an output enable signal, which is set to Low when reading data from the flash memory, and set to High at other times. CE is a chip enable signal, and is set to Low when reading and writing commands and data to the flash memory. The CE of this flash memory also serves as a write enable signal. When Vpp is at a high potential and OE is High, data is written at the rising edge of OE. I / O7 and I / O0 to I / O6 are data lines. Next, an operation when writing 1-byte data in the flash memory is shown. First, the command on the data line is written to the flash memory at the rising edge of CE. This command is a write setup command for notifying the flash memory of the start of writing one word of data. After writing this command, the data on the data line is written to the flash memory at the rising edge of CE. The CE Low period when writing this command and data is a minimum of 50 nanoseconds. However, actually, writing to the memory chip has started inside the flash memory, and the next data cannot be written until the internal writing is completed. Here, several tens of microseconds are required until the writing in the flash memory is completed, and a considerable time is required as compared with the writing time of the command and one word of data. Then, status polling is available as means for checking that the writing in the flash memory chip has been completed after the time of several tens of microseconds. This sets CE and OE to Low and reads the status from the I / O 7 to determine the end of writing in the memory chip.

  The above technique requires a considerable amount of time when writing a plurality of words of data continuously. Writing commands and data of one word takes several tens of nanoseconds to several hundred nanoseconds. However, a time of several microseconds to several tens of microseconds is required from the writing of one word data to the completion of the writing in the flash memory chip, and the flash memory cannot be accessed during this time. Therefore, the total time for writing one word of data is considerably slower than the reading time. In addition, when data of a plurality of words is written continuously, the writing time increases in proportion to the number of words to be written. For example, when a semiconductor disk device is constructed using a flash memory, data of several kilowords to several tens of kilowords or more is continuously written. Then, since the writing time increases in proportion to the data to be written, the transfer of writing is delayed as a whole system.

  An object of the present invention is to provide a semiconductor memory device in which a data writing time is shortened.

The present invention
Multiple flash memories that can write data in page units,
A controller that writes data from the system to the plurality of flash memories in response to a write request from an external system;
A semiconductor memory device comprising:
In response to one write request from the system, the control unit is configured so that data for a plurality of sectors accompanying one write request from the system is distributed to each flash memory in units of sectors. Generate the physical address of each flash memory from the logical sector number to manage,
While the one flash memory is writing the data for one page of the data distributed for the one flash memory, the control unit distributes the data distributed for the other one flash memory. The other one page of data and a write request for the other one page of data are given to the other one flash memory,
A semiconductor memory device is provided.
Also,
Buffer memory,
Multiple flash memories that can write data in page units,
A controller that writes data from the system to the plurality of flash memories via the buffer memory in response to a write request from an external system;
A semiconductor memory device comprising:
In response to one write request from the system, the control unit refers to a table so that data for a plurality of sectors accompanying one write request from the system is distributed to each flash memory in units of sectors. Then, the physical address of each flash memory is generated from the logical sector number managed by the system,
The control unit is distributed for the other one flash memory while one flash memory is writing data for one page of the data distributed for the one flash memory. The other one page of data is read from the buffer memory, and the other one page of data read and the write request for the other one page of data are sent to the other one. Give to the flash memory,
A semiconductor memory device is provided.

  Since the present invention is configured as described above, it is possible to provide a semiconductor memory device in which the data writing time is shortened.

Action

  In a semiconductor memory device in which a plurality of flash memories are mounted and data is stored in the flash memory, the control unit sends a write instruction to the flash memory, and the flash memory to which the write instruction is sent sends the next write instruction. Until it can be accepted, a write instruction is sent to a flash memory different from the flash memory in which the write is being performed.

  In this embodiment, in the case of continuous data writing, control is performed so that data is not continuously written in the same flash memory but is written in another flash memory.

  There is a waiting time of several microseconds to several tens of microseconds from writing one word of data to the flash memory until writing the next data. Therefore, when there is continuous write data, one word of data is continuously written to another flash memory during this waiting time. Then, when the waiting time of the first written flash memory has passed, status polling is performed from the first flash memory, and the next one word of data is written. In this manner, writing to another flash memory is performed during the waiting time of the flash memory.

  When the flash memory is used for writing a plurality of continuous data, according to the present embodiment, low-speed writing of the flash memory can be speeded up in total for the apparatus. That is, when a flash memory is used for a semiconductor disk device, a plurality of continuous data is written. However, in the case of continuous data writing, writing to the flash memory is slower than reading, so the total transfer rate is reduced. However, according to the present embodiment, the writing speed of the entire apparatus can be increased even when the writing speed of the flash memory is low.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of a semiconductor disk device using a flash memory. In the figure, reference numeral 1 denotes a standard bus such as a personal computer, through which commands and data are sent and received from the system. The bus is not particularly limited as long as there is a protocol agreement with a system that requires an auxiliary storage device such as a SCSI interface or a local bus of the system. 4 is a plurality of flash memories. A write buffer memory 5 temporarily holds data transferred from the standard bus 1. Since the flash memory is slower in writing than reading, the flash memory temporarily holds the write data transferred from the standard bus 1 and quickly releases the bus right to the system side. The write buffer memory 5 is composed of a static RAM in the drawing. However, it is not limited to a static RAM, and any storage element that can be written at higher speed than the flash memory 4 regardless of volatile or non-volatile may be used. Further, not only the semiconductor disk device but also a part of the data storage area on the system side may be used. The write buffer memory 5 has a capacity of a plurality of sectors in units of 512 bytes which is a sector capacity of a standard disk. Reference numeral 2 denotes a processor. The processor 2 controls the writing of data from the write buffer memory 5 to the flash memory 4, and exchanges and analyzes commands and statuses from the standard bus. 11 is a conversion table for converting a logical sector number that is a sector number managed by the system into a physical sector number that is a sector number of an area to be written to the flash memory (the processor 2 converts the logical sector number accessed for the first time) A static ram (SRAM) storing a table). An address control unit 31 generates a physical address that is an actual address of the flash memory 4 and the write buffer memory 5 and is controlled by the processor 2. Reference numeral 6 denotes a Vpp generation circuit for generating Vpp which is a writing power source for the flash memory, and the power generation is controlled by the processor 2. Reference numeral 71 denotes a memory address bus for the flash memory 4 and the write buffer memory 5, which is output from the address control unit 31. Reference numeral 72 denotes a data bus.

  The write operation controlled by the processor 2 in the semiconductor disk device having the configuration of FIG. 1 is shown in the flowchart of FIG. It is determined whether or not a write request is received from the standard bus 1 (21). When the request is received, the processor 2 starts generating the write power supply Vpp for the Vpp generation circuit 6 (22). Then, the processor 2 converts the logical sector number, which is a sector number managed by the system, passed from the standard bus 1 into a physical sector number which is a sector number of an area to be written to the flash memory (23). At this time, the physical sector number is determined so that the flash memory in which the data of a plurality of sectors transferred from the standard bus 1 are written in units of sectors is a separate chip. For example, one sector of data transferred first is assigned to chip 0 of the flash memory, one sector of data transferred next is assigned to chip 1 of the flash memory, and so on. The determined physical sector number is held in the write management table shown in FIG. This write management table exists in the address control unit 31. In FIG. 3, the data of three sectors transferred from the standard bus 1 are held in the block 1 to the block 3 of the write buffer memory 5, and the data of one sector of each block is stored in the sector of the chip 0 of the flash memory 4, respectively. 3, writing to sector 2 of chip 1 and sector 7 of chip 2.

  When the setting of the write management table is completed, the data of 3 sectors transferred from the standard bus 1 is received from the block 1 to the block 3 of the write buffer memory 5 as specified by the write management table. Thereby, the access right of the standard bus 1 is released so that writing to the flash memory 4 can be processed only in the semiconductor disk device (24).

  Then, the data received in the write buffer memory 5 is written into the flash memory 4. First, when the processor 2 selects the table number 0 of the write management table, the physical addresses of the write buffer memory 5 and the flash memory 4 are output to the memory address bus 71. Therefore, one word data is read from the block 1 of the write buffer memory 5 (26), a write command is written to the chip 0 of the flash memory 4 (27), and the one word data read from the write buffer memory 5 is read into the flash memory 4 (28). Thus, the chip 0 of the flash memory 4 starts writing data internally, but the chip 0 cannot read or write data until the internal writing is completed. It is determined whether there is data to be written to the next chip (29). If there is, data is written to another memory chip. As described in the case of conversion to a physical sector, when writing a continuous sector, each sector is assigned to another chip. The processor 2 designates the table number 1 of the write management table (25), and writes 1-word data read from the block 2 of the write buffer memory 5 to the chip 1 of the flash memory 4 (26, 27, 28). Subsequently, the table number 2 is designated, and 1-word data read from the block 3 of the write buffer memory 5 is written to the chip 2 of the flash memory 4 (26, 27, 28).

  After writing one word of data to each of chip 0, chip 1 and chip 2 of flash memory 4 (29), status polling of chip 0 of flash memory 4 written first is performed (33), and chip of flash memory 4 is written. Check if internal writing is completed. At this time, similarly to the writing, the processor 2 reads the status of the chip 0 of the flash memory 4 by designating the table number 0 of the writing management table. Here, if the writing is not completed in the chip 0 of the flash memory 4, the status polling is repeated. If the writing has been completed, the counter value of the table 0 of the writing management table is incremented (34). Similarly, it is determined whether or not the next table exists in the write management table (35). If there is, the table number 1 is designated, and the status of the chip 1 that has written data after the chip 0 of the flash memory 4 is specified. Perform polling. If the writing in the chip 1 of the flash memory 4 has been completed, the status polling of the chip 2 of the flash memory 4 to which the data has been written is performed (33). If all the chips of the flash memory 4 that have written data have been internally written, the process returns to the beginning of the write sequence.

  Here, it is determined whether the counter has reached 512 bytes. If it has reached, writing of all data from the buffer memory 5 to the flash memory 4 has been completed. If the counter is still 512 bytes or less, the above writing method is repeated until 512 bytes have been written. When the writing of all data from the write buffer memory 5 to the flash memory 4 is completed, the processor 2 causes the Vpp generation circuit 6 to stop generating the write power supply Vpp (37).

  As is apparent from the above embodiment, data of 3 sectors can be written to the flash memory in approximately 1 sector of writing time. In this embodiment, an example of writing in three sectors is shown, but it is obvious that writing data in more sectors than three sectors is the same.

  In the above embodiment, the flash memory to be written on a sector basis is allocated to another chip, but there is a method of dividing 512 bytes in a sector into a plurality of blocks. Writes are assigned to different flash memories in units of the divided blocks. For example, 512 bytes are divided into 16 blocks in units of 32 bytes. Then, 1 to 16 blocks are written to different chips of the flash memory. This is a 32-byte unit, but it may be an arbitrary byte unit such as 16 bytes or 64 bytes.

  In the above embodiment, the flash memory has a certain waiting time from the writing of the write command and one word of data to the writing of the next one word of data. However, a flash memory capable of page writing, that is, a plurality of words of data can be continuously written after a page write command is written, and writing to the memory chip inside the flash memory is completed after the writing of the plurality of words of data. In the same way as in the above embodiment, the flash memory having a certain waiting time until the status polling is performed on a flash memory chip different from the flash memory chip on which the data is written. Write data.

  The same applies to erasure as well as data writing to the flash memory 4. The flash memory 4 is erased in units of chips or in units of blocks each having a plurality of words as one unit. The erasing method starts erasing processing in the flash memory 4 by writing an erasing command simultaneously with designating an address indicating a block to be erased in the flash memory 4. Then, there is a waiting time of a certain time until erasing in the flash memory 4 is completed. In the meantime, access other than status polling cannot be performed on the flash memory 4 performing the erasure process. When the end of internal erasure is confirmed by status polling after a predetermined time has passed, the process proceeds to erasure of the next flash memory. During this fixed period of time, the erase command is written to a flash memory different from the flash memory that is erasing, and multiple flash memories are erased at the same time, thereby speeding up erasure of the entire semiconductor disk device. Realize.

  The erase operation controlled by the processor 2 in the semiconductor disk device having the configuration of FIG. 1 is shown in the flowchart of FIG. Since it is necessary to apply the write power supply Vpp even when the flash memory 4 is erased, the processor 2 activates the generation of the write power supply Vpp to the Vpp generation circuit 6 (41). Then, the processor 2 sets the physical sector number of the flash memory 4 to be erased in the write management table of FIG. 3 (42). At this time, the area to be erased is set to be another memory chip. In this embodiment, the case where the erase unit of the flash memory 4 is one sector will be described. After the sector to be erased is set in the write management table, the erase command is written to each chip of the flash memory 4 indicated by the table while updating the designation of the write management table (43). It is determined whether there is a next erase area (45). When all erase commands have been written, the table designation is updated (46), and status polling is performed from the memory chip in which the erase command is first written (47). 4 Check whether the internal erasure process has been completed. Then, it is determined whether or not the next table is designated (48). When all the flash memories have been erased, the processor 2 causes the Vpp generation circuit 6 to stop generating the write power supply Vpp (49).

  In the above embodiment, the flash memory that performs erasing in units of one sector has been described. However, the erase unit differs depending on the flash memory. Therefore, the setting method of the write management table differs depending on the erase unit of the flash memory. When the flash memory is erased in units of chips, it is sufficient to set only the chip number column of the flash memory in the write management table. Further, in the case of a flash memory that performs erasing in units of a plurality of words, it becomes a set of two columns of the flash memory chip number and sector number of the write management table. However, even a flash memory that erases in units of multiple words is not necessarily erased in units of one sector. When the flash memory erases the capacity of a plurality of sectors as one block, a plurality of sectors are erased by setting the flash memory sector number column in the write management table.

  In the above embodiment, when the write power supply Vpp is necessary for writing and erasing, the write power supply Vpp is applied to all the flash memories 4. However, there is a method in which the write power supply Vpp is applied only to the flash memory for writing. FIG. 5 shows a block diagram of a semiconductor disk device according to the embodiment. In the figure, reference numeral 61 denotes a switch unit for turning on / off the application of the write power supply Vpp from the Vpp generation circuit 6 to the flash memory 4, and is controlled by the processor 2 so that the output of a plurality of write power supplies Vpp can be selected. The rest of the configuration is the same as in FIG. When a write request is received from the standard bus 1, the processor 2 activates the Vpp generation circuit 6 to generate the write power supply Vpp. Thereafter, the logical sector number is converted into a physical sector number, and the physical sector number is held in the write management table of FIG. At this time, the write power supply Vpp to a plurality of or one flash memory 4 to be written is applied by the designation of the Vpp switch unit 61, respectively. It is obvious that the application of the write power supply Vpp by the designation of the Vpp switch unit 61 is performed not only at the time of writing but also when the flash memory 4 requires the write power supply Vpp, such as erasing.

  In the above embodiment, the flash memory is described which requires the write power supply Vpp having a voltage value different from the power supply voltage at the time of writing or erasing. However, FIG. 6 shows a block diagram of a semiconductor disk device equipped with a flash memory having a single power source, that is, a flash memory that does not require a write power source Vpp. The configuration is the same as in FIG. 1, but it is not necessary to mount the Vpp generation circuit 6. In addition, it is clear that the write power supply on / off process is not necessary in the write flowchart of FIG. 2 or the erase flowchart of FIG.

  In the above embodiment, the chip of the flash memory to be written is selected by the chip enable signal CE. However, there is a method for controlling selection of a flash memory to be written by the write enable signal WE instead of the chip enable signal CE. FIG. 7 shows a block diagram of the semiconductor disk measures at that time. In the figure, reference numeral 32 denotes a WE selection unit that selectively supplies the flash memory 4 with a write enable signal WE for writing to the flash memory 4. The rest of the configuration is the same as in FIG. The WE selection unit 32 validates the write enable signal only for the flash memory in which writing has occurred. The write control performed by the processor 2 is the same as the operation shown in the flowchart of FIG.

  Some flash memories 4 do not have a write enable signal WE. When writing data to the flash memory, the writing is controlled by controlling the chip enable signal CE and the write power supply Vpp. Even in such a flash memory, the present invention can be used to speed up writing and erasing.

  As can be seen from the above description, according to the present invention, even if an auxiliary storage device having a large amount of write data uses a flash memory that is slower in writing than read, the entire device can be written at high speed. There is an effect that can be done. In particular, the effect is great when there is continuous writing of a large amount of data. Further, it is possible to erase at a high speed with respect to simultaneous erasure of a plurality of areas.

1 is a block diagram of a semiconductor disk device of an embodiment that performs the operation of the present invention. The flowchart which shows the write-in operation | movement of this invention. A write management table used in the operation of the present invention. 5 is a flowchart showing an erase operation of the present invention. 1 is a block diagram of a semiconductor disk device of an embodiment that performs the operation of the present invention. 1 is a block diagram of a semiconductor disk device of an embodiment that performs the operation of the present invention. 1 is a block diagram of a semiconductor disk device of an embodiment that performs the operation of the present invention. Explanatory drawing of the write timing waveform of 1 word of flash memory.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Standard bus 2 ... Processor 31 ... Address control part 32 ... WE selection part 4 ... Flash memory 5 ... Write buffer memory 6 ... Vpp generation circuit 61 ... Vpp Switch 71 ... Address bus 72 ... Data bus

Claims (7)

And a plurality of flash memory capable of writing data on a page-by-page basis,
A controller that writes data from the system to the plurality of flash memories in response to a write request from an external system;
A semiconductor memory device comprising:
In response to one write request from the system, the control unit is configured so that data for a plurality of sectors accompanying one write request from the system is distributed to each flash memory in units of sectors. Generate the physical address of each flash memory from the logical sector number to manage ,
Wherein, while the one of the flash memory is writing a page of data among the distributed data for that one flash memory, data distributed for other one flash memory The other one page of data and a write request for the other one page of data are given to the other one flash memory.
A semiconductor memory device. The semiconductor memory device according to claim 1, wherein
The controller is
It is determined whether there is data for the other one page to be written to the other one flash memory, and the data for the other one page to be written to the other one flash memory is in some cases, the while one flash memory is writing data of the one page, and a write request for data of one page of data and the other the other one page of the other Give to one flash memory,
A semiconductor memory device. Buffer memory,
And a plurality of flash memory capable of writing data on a page-by-page basis,
A controller that writes data from the system to the plurality of flash memories via the buffer memory in response to a write request from an external system;
A semiconductor memory device comprising:
In response to one write request from the system, the control unit refers to a table so that data for a plurality of sectors accompanying one write request from the system is distributed to each flash memory in units of sectors . Then, the physical address of each flash memory is generated from the logical sector number managed by the system ,
Wherein, while the one of the flash memory is writing a page of data among the distributed data for the flash memory of one said, data distributed for other one flash memory The other one page data is read from the buffer memory, and the read one page data and the write request for the other one page data are sent to the other one page . Give to flash memory,
A semiconductor memory device. The semiconductor memory device according to claim 3,
The control unit determines whether there is data for the one page to be written to the other one flash memory, and determines the other one page to be written to the other one flash memory. If there is data, while the one of the flash memory is writing data of the one page, read the data of the other of one page from the buffer memory, 1 read of the other page The other one flash memory and a write request for the other one page of data,
A semiconductor memory device. The semiconductor memory device according to any one of claims 3 and 4,
A RAM for storing a conversion table for converting the logical sector number into a physical sector number;
The table includes the conversion table ,
A semiconductor memory device. 6. The semiconductor memory device according to claim 5, wherein
The control unit creates a conversion table for the logical sector number accessed for the first time,
A semiconductor memory device. 6. The semiconductor memory device according to claim 5, wherein
The control unit has a management table for setting the physical sector number of the flash memory to which data is to be written,
The table further includes the management table,
In response to one write request from the system, the control unit refers to the conversion table, converts the logical sector number to the physical sector number, sets the physical sector number in the management table, The physical address is generated by designating the physical sector number of the management table.
A semiconductor memory device.

Images