JP3718261B2 - Manufacturing method of semiconductor integrated circuit device - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a method of manufacturing a semiconductor integrated circuit device formed on an SOI (Silicon On Insulator) substrate, and more particularly, to a semiconductor integrated circuit device in which a defective portion of a semiconductor element is repaired by SDIT (Super Device Integration Technology) technology. It is related to effective technology when applied.
[0002]
[Prior art]
An SOI substrate in which a single crystal silicon film is formed on a semiconductor substrate via an insulating layer can reduce the parasitic capacitance of the semiconductor element and improve the resistance to radiation. Research is being conducted.
[0003]
By the way, when an abnormal operation occurs in some of the semiconductor elements formed on the SOI substrate, generally, even if other semiconductor elements are operating normally, all of the semiconductor integrated circuit device is processed as a defective product. .
[0004]
Therefore, the region in which the semiconductor element in which the abnormal operation is confirmed is formed is removed from the first SOI substrate, and the region in which the semiconductor element in which the normal operation is confirmed is newly formed is removed from the second SOI substrate. Examining SDIT (Super Device Integration Technology) technology to improve the manufacturing yield of semiconductor integrated circuit devices by cutting out and embedding in the removed region of the first SOI substrate to repair defective parts of the semiconductor integrated circuit device Has been.
[0005]
The following is not a publicly known technique, but is a technique examined by the present inventor, and its outline is as follows.
[0006]
In the SDIT process, first, after a semiconductor element is formed on a single crystal silicon film having a thickness of 2 to 3 μm constituting the first SOI substrate, a first insulating layer is deposited on the first SOI substrate, A contact hole for connecting a first wiring layer to be formed later is formed in the first insulating layer. Next, a metal film is deposited on the first SOI substrate, and the metal film is processed to form a first wiring layer for connecting between the semiconductor elements or between the semiconductor elements and the peripheral circuit.
[0007]
Next, a second insulating layer is formed over the first SOI substrate. At this time, a silicon oxide film is first deposited by a plasma CVD (Chemical Vapor Deposition) method, and then an organic glass (Spin On Glass; SOG) film is applied on the first SOI substrate, followed by heat treatment. Thus, the SOG film is made inorganic and at the same time the SOG film is flattened.
[0008]
Next, a part of the second insulating layer made of the planarized SOG film and silicon oxide film is sequentially etched to form an opening in a part of the second insulating layer on the first wiring layer. The operation test of the semiconductor element is performed by connecting the terminal of the operation test apparatus to one wiring layer.
[0009]
When an abnormal operation is confirmed in the semiconductor element, a groove is dug around the area where the semiconductor element is formed, and subsequently, the portion above the single crystal silicon film in this area is formed by dry etching and wet etching. 1 from the SOI substrate.
[0010]
Next, also on the second SOI substrate in which the semiconductor element having the same structure is formed by the same process as the semiconductor element formed on the first SOI substrate, the operation test of the semiconductor element is performed using the first wiring layer.
[0011]
Of the semiconductor elements formed on the second SOI substrate, when normal operation is confirmed in the semiconductor element having the same structure as the semiconductor element confirmed to be abnormal in the first SOI substrate, the second SOI substrate starts An upper portion is cut out from the single crystal silicon film in a region where the semiconductor element is formed, and is fitted into the removed region of the first SOI substrate and bonded thereto.
[0012]
Next, a third insulating layer is deposited on the first SOI substrate, a part of the third insulating layer and the second insulating layer are sequentially etched, and a first wiring layer and a second wiring layer formed later are formed. After forming a through hole for connection, a metal film is deposited on the first SOI substrate, and this metal film is processed to form a second wiring layer.
[0013]
[Problems to be solved by the invention]
The present inventor has found the following problems in developing the SDIT technology.
[0014]
That is, after forming a semiconductor element on an SOI substrate, an insulating layer and a wiring layer are formed on the SOI substrate. However, step coverage is required for increasing the density and narrowing of the wiring layer accompanying the miniaturization of the semiconductor element. The wiring layer is likely to be disconnected due to defects, and as a countermeasure against this, the insulating layer needs to be processed flat.
[0015]
The flattening of the insulating layer that cannot be subjected to high-temperature heat treatment deposited on the wiring layer is conventionally performed by applying a heat treatment at about 400 ° C. after applying an SOG film that is an organic silicon compound.
[0016]
However, since the SOG film shrinks in volume during the heat treatment, the single crystal silicon film having a thickness of 2 to 3 μm cut out from the second SOI substrate is warped and peeled off from the first SOI substrate or cracked. May occur.
[0017]
For this reason, even if the SDIT technology is adopted, the defective portion of the semiconductor integrated circuit device cannot be repaired, and therefore the manufacturing yield of the semiconductor integrated circuit device cannot be improved.
[0018]
An object of the present invention is to make effective the improvement of the manufacturing yield of semiconductor integrated circuit devices by the SDIT technology.
[0019]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0020]
[Means for Solving the Problems]
Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
[0021]
That is, according to the method of manufacturing a semiconductor integrated circuit device of the present invention, in a semiconductor integrated circuit device whose defective portion is repaired by the SDIT technology, a planarizing insulating layer provided to insulate a wiring layer on an SOI substrate is formed on a substrate. An insulating material having a thermal expansion coefficient substantially equal to the thermal expansion coefficient (about 0.5 × 10 ⁻⁶ / ° C.) of the single crystal silicon constituting is used.
[0022]
[Action]
According to the above means, since the single crystal silicon film having a thickness of 2 to 3 μm cut from the SOI substrate is not warped by stress, the single crystal silicon film cut from the SOI substrate is not transferred to the implanted SOI substrate. It is not peeled off and cracks are not generated.
[0023]
In general, the stress σ _{f of} a film deposited at a certain temperature T is
σ _f = (α _f −α _s ) · [E _f / (1−ν _f )] · (T _d −T) + σ _i
It is represented by Where α _f and α _s are the thermal expansion coefficients of the deposited film and substrate, E _f and ν _f are the elastic constants and Poisson's ratio of the deposited film, T _d is the deposition temperature, and σ _i is the intrinsic stress. is there.
[0024]
Accordingly, the smaller the difference between the thermal expansion coefficients of the deposited film and the substrate, the smaller the stress of the deposited film with respect to the substrate, and the less likely it is to warp.
[0025]
【Example】
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0026]
The SDIT process which is one embodiment of the present invention will be described with reference to FIGS. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.
[0027]
First, as shown in FIG. 1, a semiconductor element is formed on a first SOI substrate 1A in which a single crystal silicon film 3 having a thickness of 2 to 3 μm is formed on a semiconductor substrate 1 made of single crystal silicon via an insulating layer 2. (Not shown). Next, after a first silicon oxide film 4 and a BPSG (Boron Phosphorous Silicate Glass) film 5 are sequentially deposited on the first SOI substrate 1A by a CVD method, heat treatment is performed at a temperature of 850 to 950 ° C. in a nitrogen gas atmosphere. Then, the surface of the BPSG film 5 is flattened.
[0028]
Next, the BPSG film 5 and the first silicon oxide film 4 are sequentially etched using a photoresist as a mask to form a contact hole (not shown) for connecting the semiconductor element and the first wiring layer 6 to be formed later. .
[0029]
Next, a metal film (aluminum alloy film or tungsten film) is deposited on the first SOI substrate 1A, and this metal film is etched using a photoresist as a mask, so that the semiconductor element or the peripheral circuit is connected between the semiconductor elements. A first wiring layer 6 is formed for connection to (not shown).
[0030]
Next, a second silicon oxide film 7 is deposited thickly on the first SOI substrate 1A by a plasma CVD method. Subsequently, for example, the second silicon oxide film 7 is formed by a CMP (Chemical Mechanical Polishing) method. To flatten. The thermal expansion coefficient of the second silicon oxide film 7 is substantially equal to the thermal expansion coefficient (about 0.5 × 10 ⁻⁶ / ° C.) of the single crystal silicon film 3, and the stress of the second silicon oxide film 7 at room temperature is 0.2 to 5 × 10 ⁹ dyn / cm ² .
[0031]
Next, a part of the second silicon oxide film 7 on the first wiring layer 6 is etched to provide an opening 8. Thereafter, a terminal of the operation test apparatus is connected to the first wiring layer 6 exposed in the opening 8 to perform an operation test of the semiconductor element. When an abnormal operation is confirmed in the semiconductor element in the operation test, a portion above the single crystal silicon film 3 in the region (block A) where the semiconductor element is formed is removed from the first SOI substrate 1A.
[0032]
First, a trench is dug around the block A by dry etching, and then, as shown in FIG. 2, the dry etching and the wet etching are performed from the first SOI substrate 1A to the upper part of the single crystal silicon film 3 of the block A. Remove the part.
[0033]
Next, also in the second SOI substrate 1B in which the semiconductor element having the same structure is formed by the same process as the semiconductor element formed on the first SOI substrate 1A, the first SOI substrate 1A is formed using the first wiring layer. Perform the same test as the operation test performed in.
[0034]
Among the semiconductor elements formed on the second SOI substrate 1B, when normal operation is confirmed in the same semiconductor element as that of which the abnormal operation is confirmed on the first SOI substrate 1A, this semiconductor element is formed. The upper portion of the region (block B) from the single crystal silicon film 3 is cut out from the second SOI substrate 1B.
[0035]
First, as shown in FIG. 3, the support 9 is bonded to the surface of the block B of the second SOI substrate 1B with an epoxy adhesive. Next, the second SOI substrate 1B is etched from the back side, and the semiconductor substrate 1 and the insulating layer 2 are all removed to leave an upper portion from the single crystal silicon film 3, and then regions other than the block B are removed. By doing so, the block B is cut out.
[0036]
Next, for example, gold (Au) is vapor-deposited on the surface of the portion where the block A of the first SOI substrate 1A has been removed and the back surface of the block B cut out from the second SOI substrate 1B, and pressure-bonded in vacuum. As a result, the block B is mounted on the portion of the first SOI substrate 1A from which the block A is removed. Subsequently, the epoxy adhesive is removed with an organic solvent, and the support 9 is separated from the block B.
[0037]
Next, as shown in FIG. 4, after the third silicon oxide film 10 is deposited on the first SOI substrate 1A, the third silicon oxide film 10 and a part of the second silicon oxide film 7 are sequentially etched. Through holes (not shown) for connecting the first wiring layer 6 and the second wiring layer 11 to be formed later are formed. Next, a metal film is deposited on the first SOI substrate 1A, and the second wiring layer 11 is formed by etching the metal film using a photoresist as a mask.
[0038]
Finally, the surface of the first SOI substrate 1A is covered with the passivation film 12 to complete the semiconductor integrated circuit device.
[0039]
The invention made by the inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Not too long.
[0040]
For example, in the above embodiment, the silicon oxide film deposited on the first wiring layer is formed by the plasma CVD method, but may be formed by the photo CVD method or the sputtering method.
[0041]
In the above embodiment, the silicon oxide film deposited on the first wiring layer is planarized by the CMP method, but may be performed by a resist coating etch back method or a sputter etching method.
[0042]
In the above embodiment, after depositing the silicon oxide film on the first wiring layer, the silicon oxide film is flattened by the CMP method. However, the silicon oxide film is formed by the bias sputtering method which can be flattened while depositing the insulating film. A film may be deposited.
[0043]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed by the present application will be briefly described as follows.
[0044]
According to the present invention, the thin single crystal silicon film cut out from the SOI substrate does not peel off from the transplanted SOI substrate and does not cause cracks, so that the reliability of the SDIT technology is improved. Improvement of the manufacturing yield of the semiconductor integrated circuit device can be an effective technique.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a principal part of a semiconductor substrate showing a semiconductor integrated circuit device formed on a first SOI substrate according to an embodiment of the present invention.
FIG. 2 is a fragmentary cross-sectional view of a semiconductor substrate showing a semiconductor integrated circuit device formed on a first SOI substrate according to an embodiment of the present invention;
FIG. 3 is a fragmentary cross-sectional view of a semiconductor substrate showing a semiconductor integrated circuit device formed on a second SOI substrate according to an embodiment of the present invention;
FIG. 4 is a cross-sectional view of a main part of a semiconductor substrate showing a semiconductor integrated circuit device formed on a first SOI substrate according to an embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1A 1st SOI substrate 1B 2nd SOI substrate 2 Insulating layer 3 Single crystal silicon film 4 1st silicon oxide film 5 BPSG film 6 1st wiring layer 7 2nd silicon oxide film 8 Opening 9 Support 10 Third silicon oxide film 11 Second wiring layer 12 Passivation film

Claims (4)

(A) forming a semiconductor element on a first SOI substrate in which a single crystal silicon film is formed over an insulating film on a semiconductor substrate;
(B) forming a first insulating film on the first SOI substrate;
(C) forming a contact hole in the first insulating film for connecting the semiconductor element and a wiring layer to be formed later;
(D) forming a wiring layer on the first insulating film for connecting between the semiconductor elements or between the semiconductor elements and a peripheral circuit;
(E) forming a second insulating film having a thermal expansion coefficient substantially equal to the thermal expansion coefficient of the single crystal silicon film on the first insulating film and the wiring layer;
(F) removing a part of the second insulating film to form an opening;
(G) connecting a terminal of an operation test apparatus to the wiring layer exposed in the opening, and performing an operation test of the semiconductor element;
(H) removing a portion above the single crystal silicon film in a region where a semiconductor element whose abnormal operation has been confirmed in the operation test is formed from the first SOI substrate;
(I) Abnormal operation in the first SOI substrate from the second SOI substrate in which the same structure is formed by the same process as the steps (a) to (f) applied to the first SOI substrate. Cutting the upper part from the single crystal silicon film in the region where the same semiconductor element as the semiconductor element confirmed is formed,
(J) A method for manufacturing a semiconductor integrated circuit device, comprising the step of attaching the portion cut out in the step (i) to the region removed in the step (h). 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the stress of the second insulating film is 0.2 to 5 × 10 ⁹ dyn / cm ² . Production method. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the second insulating film is a silicon oxide film formed by a plasma CVD method, a photo CVD method, a sputtering method, or a bias sputtering method. A method for manufacturing a semiconductor integrated circuit device. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the surface of the second insulating film is planarized by a CMP method.

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