JP3697728B2 - MEMORY ACCESS METHOD, MEMORY CONTROL DEVICE, AND REPRODUCTION DEVICE - Google Patents

Description

[0001]
[Industrial application fields]
  The present invention relates to a data recording / reproducing apparatus called a data streamer, an audio data recording / reproducing apparatus, etc., in which a data block to be written at the same address may be transferred to a memory multiple times. Suitable memory access method,Memory control deviceAnd playback deviceIt is about.
[0002]
[Prior art]
A D-RAM (dynamic RAM) that is easy to increase in capacity and cheaper per bit than an S-RAM (static RAM) is widely used in various systems.
[0003]
As such a D-RAM, for example, in the case of 1M word × 1 bit D-RAM, a 10-bit address terminal is formed, and each address terminal is time-divided with a row address and a column address multiplexed. 2 because it is entered^Ten× 2^Ten= 1048576 (1 Mbit) One of the memory cells can be arbitrarily accessed.
[0004]
The row address is latched from each address terminal to the internal row address buffer by the falling edge of the inverted RAS signal, and the column address is latched from each address terminal to the internal column address buffer by the falling edge of the inverted CAS signal. The
As an access operation, a row address is fetched by an inverted RAS signal, and one or a plurality of column addresses are fetched sequentially by an inverted CAS signal, thereby writing data to a required memory cell specified by the row address and the column address. Read / write is performed.
[0005]
[Problems to be solved by the invention]
By the way, when the row address is accessed by the inverted RAS signal, the sense amplifiers are activated corresponding to all the memory cells for the one row, the refresh is executed, and at the same time, the data of each memory cell is output. Capture to buffer. For this reason, there is a property that a large spike current flows when accessing a row address.
Further, there is a property that system noise increases due to a spike current generated at the time of accessing the D-RAM and a transient of the IC terminal.
For this reason, a system using a D-RAM is required to avoid unnecessary access as much as possible.
[0006]
Here, a rotary head / helical scan type digital tape recorder is considered. In a digital tape recorder, data reproduced from a magnetic tape is temporarily written in a D-RAM for error correction processing.
In such a digital tape recorder, the tape path may be shifted for each mechanism within a regulated range, and the recording / reproducing position on the tape may be shifted. Also, at the beginning and end of the scan on the track on the tape, the head and the tape are unstable, and a data reading error may occur.
[0007]
Therefore, the same data block is written twice in the first and last parts of the scan, and assigned to the same address in the D-RAM at the time of reproduction. Are written to the D-RAM. As a result, even if one of the first and last data blocks cannot be read from the tape, no data is lost.
[0008]
However, if both data blocks are properly read from the tape, the same data is written to the same address twice in the D-RAM. In other words, after a data block that can be read first and has a safe error check is written to a certain address in the D-RAM, the data block to be written to that address is transferred to the D-RAM again. Therefore, an unnecessary rewriting operation of the D-RAM contents is executed between data blocks having the same contents. Such unnecessary access to the D-RAM leads to an increase in power consumption and system noise.
[0009]
A so-called non-tracking type is known as a kind of rotary head / helical scan type digital tape recorder. This is because, instead of performing tracking control at the time of playback to accurately trace the recording track, the playback head traces obliquely with respect to the recording track by scanning at twice the density at the time of recording at the time of playback. However, all data blocks can be read.
The number of times the same data block can be read on the tape by this high-density non-tracking trace is distributed between approximately 1 and 2 times depending on the inclination of the reproduction scan.
[0010]
Here, considering the case where the same data block can be read more than once, the second and subsequent data blocks have the same contents as the data blocks already stored in the first read on the D-RAM. Unnecessary rewriting will be performed with the data. Such unnecessary access to the D-RAM causes an increase in power consumption and system noise.
[0011]
In other words, in a system in which a data block to be written to the same address on the memory may be transferred to the memory multiple times, such as a D-RAM on such a digital tape recorder, useless access In many cases, the operation is executed, and the D-RAM consumes a large current at the time of access. This causes an increase in power consumption and system noise, and a battery-driven system shortens the battery life. There was a problem of being.
[0012]
[Means for Solving the Problems]
In view of these problems, an object of the present invention is to reduce power consumption due to unnecessary access and system noise.
[0013]
  Therefore, a memory access method in the case where a data block as a processing unit is configured by a plurality of words and a data block to be written to the same address on the memory may be transferred to the memory a plurality of times. As follows.
  At the time when the required data block is stored in the storage area that is the address of each data block unit, the storage state is set in which the error flag for at least a predetermined word in the data block is turned off, and each data When a stored data block is no longer needed for a storage area that is an address in block units, a storage state is set in which an error flag for at least a predetermined word in the data block is turned on.
  And the transferred data blockAfter determining the error status for the data block, to the memory of the data block determined to be writable to memory based on the determination resultWhen an error flag is on, the error flag for a given word is checked at the address where the data block is to be written. If the error flag is on, a write access operation is performed and the error flag is off. In this case, the write access operation is not executed.
[0014]
  Further, in a data transfer system in which a data block as a processing unit is configured by a plurality of words and a data block to be written to the same address on the memory may be transferred to the memory a plurality of times. As a memory control device for realizing the access method, an error flag setting means,A determination means;Error flag checking means and access control means are provided.
  The error flag setting means stores at least the predetermined word in the data block when the necessary data block is stored in the storage area serving as the address of each data block. At the time when the stored data block is no longer needed for the storage area serving as the address of each data block unit, at least the predetermined word in the data block is stored with the error flag turned on. It is configured to be in a state.
  The determination unit can determine whether or not writing to the memory is possible based on an error state of the transferred data block.
  The error flag checking means makes it possible to check the error flag for a predetermined word at the address where the data block is to be written in response to the transfer of the data block.
  Access control meansThe determination means determines that writing to the memory is possible, andWhen the error flag checking means detects that the error flag is turned on, it executes a write access operation to the memory for the transferred data block, and when it detects that the error flag is turned off, Write access to memoryBanTo do.
[0015]
[Action]
Once the necessary data block is written, the error flag is turned off for the data block. When a certain data block is transferred to the memory and written, the error flag is confirmed for the data stored at the address to be written. At this time, if the error flag is OFF, the same data as the transferred data has already been stored. That is, the data transfer is the second or later data transfer, and it is not necessary to newly write the data. It can be judged that there is not. Therefore, in this case, unnecessary access operations can be prevented from occurring by not executing the write access.
[0016]
【Example】
Hereinafter, as an embodiment of the present invention, a method for accessing a D-RAM and a memory control device mounted in a recording / reproducing apparatus that uses a magnetic tape as a recording medium and records / reproduces audio data in a non-tracking manner by a rotating head will be described. .
In this case, audio data or the like is stored in the D-RAM for recording / reproduction and error correction. First, the data format will be described.
[0017]
In the case of recording / reproducing on / from a magnetic tape by a non-tracking method, a track TK is formed in an oblique direction on the magnetic tape T by a helical scan method of a head as shown in FIG. On the other hand, as shown by Pa and Pb at the time of reproduction, a higher density scan is performed than at the time of recording, so that all data on the track TK can be read without accurately tracing the track. Further, the read data is rearranged using addresses recorded together with the data, so that an accurate reproduction data stream can be reconstructed.
[0018]
FIG. 4 shows the configuration of the track TK on the magnetic tape in the non-tracking method.
As shown in FIG. 4A, one track is composed of 108 blocks. One block is 288 bits.
The central 92 blocks of the track are used as a main data area, and an inner double recording area of 9 blocks and an outer double recording area of 7 blocks are formed on both sides thereof.
[0019]
In the inner double recording area, data having the same content as the blocks in the main data area 92 blocks away from the position in the outer direction is recorded, and in the outer double recording area, 92 blocks away from the position in the inner direction. Data having the same content as the block in the main data area is recorded. These are made up for each other even if the head hit position is shifted due to the swing of the tape, that is, no unreadable block (data content) is generated for the data as a block recorded in the main data area. I am doing so.
[0020]
For the main data area, the central two blocks are sub-code (AUX), each block on both sides is IBG (Inter-block Gap), and each block on both sides is control code (CTL). . As the control code (CTL), various types of ID information, a song heading signal, and the like are recorded. In consideration of the fact that only a part of the control code (CTL) area can be read at the time of high-speed search or the like, the contents of each block of 8 blocks are the same data. That is, the same content data is repeatedly recorded 8 times at different addresses.
A data area of 40 blocks is formed on both sides of the area to be the control code (CTL).
[0021]
The signal format within one block is as shown in FIG.
First, the first 11 bits are used as a sync pattern, and then the address ADRS is recorded with 13 bits. This address ADRS is composed of a 6-bit track address and a 7-bit block address.
Since the track address and the block address are recorded in each block in this way, the data stream is reconstructed in an appropriate block order by writing to a predetermined address on the D-RAM for each block during reproduction. be able to.
[0022]
That is, in the case of the non-tracking method, the track TK is not necessarily traced accurately, so that all blocks can be read for each track by performing high-density scanning as shown in FIG. The reading order of each block is random. The read block data is temporarily stored in the RAM. At this time, a write address is generated on the RAM using a track address and a block address, and each block data is written. Therefore, at the stage where all blocks have been read for a certain track, the data of that track are arranged on the RAM. Therefore, if the block data is read in order from the RAM, an appropriate data stream is reconstructed.
[0023]
Following the address ADRS, 4 words of P and Q parity (P_OD, Q_OD, P_EV, Q_EV) Is recorded.
Following the parity word, 16-word audio data (L1, R1... L8, R8) is recorded with 12 bits each.
Following the 16-word audio data (L1, R1... L8, R8), two CRC words are recorded with 12 bits each. This CRC word is used for error checking of block unit data.
[0024]
Also, an overwrite protect code (OWP code) is recorded in the CRC word. The OWP code is recorded after arranging the same two words and taking 24-bit CRC and EX-OR. Therefore, at the time of reproduction, the OWP code can be restored by performing EX-OR with the CRC generated from the reproduction data.
[0025]
FIG. 1 shows a reproduction system circuit block for the track data in the above format.
In FIG. 1, 1 is a 4M bit D-RAM.
One track is recorded and reproduced by one rotation of the rotating head by the helical scan of the rotating head. Here, when one track is referred to as “V”, recording data or reproducing data is stored. -The RAM has a storage capacity of 128V.
[0026]
Accordingly, on the D-RAM, first, an address space of 7 bits from V6 to V0 is formed as an address corresponding to a track of 0V to 127V as schematically shown in FIG.
There is an area for 128 blocks in one V address, and addresses of 00h to 7Fh are formed by 7 bits of B0 to B6 as block addresses. (Values with “h” are in hexadecimal notation)
In each block area, word addresses of 0Ch to 1Fh are formed by 4 bits of W0 to W3 corresponding to 16 words of data and 4 words of parity.
As described above, the D-RAM 1 is an 18-bit address space including the track addresses V0 to V6, the block addresses B0 to B7, and the word addresses W0 to W3.
[0027]
The D-RAM 1 is configured to be externally attached to a signal processing IC including the respective units shown in FIG. Although 16 bits are allocated to each word, the D-RAM 1 has a 4-bit width, and one word access is executed by performing four column accesses within one row access. To.
In one word of 16 bits on the D-RAM 1, the first 4 bits are used as an error flag, and 12 bits for the subsequent three accesses are assigned with data, that is, 1 word data shown in FIG.
As an error flag, 1 bit in 4 bits is set to “0” in the case of safe, and “1” is written in the case of an error.
[0028]
The block data read from the tape will be stored in the D-RAM 1. Before the block data write access operation, the processing for the stored D-RAM 1 will be described first.
[0029]
In FIG. 1, reference numeral 18 denotes an interface circuit for the D-RAM 1.
The data block written in the D-RAM 1 is first subjected to error correction processing. The data block read from the D-RAM 1 via the interface circuit 18 is supplied to the error correction / PQ set processing circuit 21 via the data bus 17. The data bus 17 is used for 12-bit data per word and a 1-bit error flag. Reference numeral 20 denotes an error correction / PQ set control circuit that performs correction processing and control of the PQ set.
[0030]
As for the data subjected to the correction processing, the error flag is turned off (“0”) for the correction OK data on the D-RAM 1, and the error flag is turned on (“1”) for the data that could not be corrected. The
After the correction process, data read from the D-RAM 1 at a constant cycle is taken into the DA data latch circuit 22. A DA output / error set address generation circuit 19 supplies a latch clock to the DA data latch circuit 22.
[0031]
The DA data latch circuit 22 is supplied with audio data compressed to a 12-bit width, and this data is decompressed to 18 bits by the decompression circuit 23.
If the error flag is turned on for one word of data latched in the DA data latch circuit 22, that is, if it cannot be corrected by the correction process, the interpolation circuit 24 performs the interpolation process. . The analog audio signal is output from the D / A converter 25 and output from the terminal 26 as a reproduced audio signal.
[0032]
Here, with respect to the memory area that has been used up for the D-RAM 1, processing for setting the error flag to “1” is performed prior to writing of block data read from the tape next time.
That is, as an error flag set to the memory area where the data that has been output to the D / A converter 25 side has been stored, the DA output / error set address generation circuit 19 supplies the data to the D / A converter 25 side. In the slot immediately after the data read access slot from the periodic D-RAM 1, the error flag = 1 is written to the same address.
[0033]
Similarly, for the P and Q parity words, processing for setting the error flag to “1” is performed in the memory area that is no longer needed prior to the writing of block data read from the tape next time.
That is, the error correction / PQ set control circuit 20 writes the error flag = 1 at the same address on the D-RAM 1 for the P and Q parity words after the correction processing.
[0034]
As described above, in the D-RAM 1, an error flag is set for word data that has been used. When the data read from the tape is accessed for writing to the D-RAM 1, the error flag is referred to. Hereinafter, this operation will be described.
[0035]
In FIG. 1, reference numeral 2 denotes a rotary head portion, and helical scan reproduction is performed by the A head and the B head. The A head and the B head are disposed so as to face each other at approximately 180 °. The signals read by the A and B heads are amplified by the head amplifier 3 and then supplied to the PLL circuit 5 via the waveform equalizer 4. In the PLL circuit 5, a reproduction clock is generated from the reproduction data, and in the demodulation circuit 6, data is demodulated using the reproduction clock, and a synchronization signal (SYNC) and NRZ demodulated data are output.
[0036]
With respect to the reproduction data for each block, the synchronization signal (SYNC) and the NRZ demodulated data are supplied to the CRC processing unit 9, and the CRC check of the NRZ demodulated data is performed with reference to the timing of the synchronization signal (SYNC). If the check is OK for the data block, a safe signal (SAFE) is supplied to the reproduction control circuit 10. The reproduction control circuit 10 then synchronizes the data blocks that are safe for the CRC check, and executes processing such as writing to the D-RAM 1, error correction, and D / A output.
[0037]
Reference numeral 7 denotes a delay circuit. If the CRC check is not safe for one block of data read from the tape, the data is not written to the D-RAM 1. Waiting for a period to perform. The delay circuit 7 can be constituted by a shift register, or a memory and a counter.
[0038]
A serial / parallel converter 8 converts each block of serially transferred word data into parallel data as shown in FIG.
For one block of data output from the serial / parallel converter 8, each word (12 bits) is sequentially latched by the data latch circuit 11 as shown in FIG.
The block address is latched by the block address latch circuit 12 as shown in FIG. In this case, the address to be latched is the 13-bit address (track address 6 bits + block address 7 bits) of each block shown in FIG.
[0039]
As shown in FIG. 5, the track address is 7 bits on the D-RAM 1, but one bit V0 is a bit corresponding to the azimuth of the A / B head, and the block address latch circuit 12 Added to the output. As a result, a 14-bit address is formed and supplied to the address conversion circuit 18.
A latch clock is supplied from the reproduction control circuit 10 to the data latch circuit 11 and the block address latch circuit 12 (FIGS. 2B and 2D).
[0040]
Reference numeral 13 denotes a word counter, which is a 5-bit counter. At the timing when the CRC check becomes safe, that is, the latch timing of the block address latch circuit 12 (FIG. 2B), the initial value 0Bh is loaded as shown in FIG. Thereafter, the count is incremented at every latch timing (FIG. 2D) to the data latch circuit 11. As can be seen from FIGS. 2E and 2F, when the counter value is 0Ch to 0Fh, it becomes the address of the P and Q parity words, and when the counter value is 10h to 1Fh, it becomes the address of the L and R data words. . When 1Fh is exceeded, it becomes 00h and the counting operation is stopped.
Since one word consists of 12 bits, the reproduction control circuit 10 has a 12-bit counter, and the latch clock (= count clock of the word counter) of FIG. ).
[0041]
Reference numeral 14 denotes a read word conversion unit which converts the value immediately before the counter value for writing the first word of the block into a certain word address. That is, since the existing word addresses are 0Ch to 1Fh, the value (0Bh) immediately before the counter value (0Ch) for writing the first word is converted into a certain value of 0Ch to 1Fh. In this embodiment, as shown in FIGS. 2F and 2G, 0Bh is converted to 1Bh which is a word address corresponding to data R6.
[0042]
As shown in FIG. 6, for the word addresses 0Ch to 0Fh, the 5-bit values of W4 to W0 are “011 **”. For the word addresses 10h to 1Fh, the 5-bit values W4 to W0 are “1 ***”.
Here, “0Bh” is “01011”, and when W4 is set to “1”, “11011”, that is, “1Bh” is obtained.
Therefore, when W2 = 0, the conversion may be performed according to the rule that W4 is “1”. When W2 = 0, it is also present in the word addresses 10h to 1Fh, but in this case there is no problem because the value of W4 is always “1”.
That is, the read word conversion unit 13 performs a logic conversion process of (W4) OR (inversion W2) on the W4 output.
[0043]
The address conversion circuit 15 is supplied with a 14-bit block address (and track address) and a 5-bit word address.
The address conversion circuit 15 converts the block address in the double recording area at both ends of the track from the block address on the latched tape into the same block address as the original block, and D in accordance with the interleave series based on the word address. Convert to a real address on RAM1.
In addition, CTL blocks that are not interleaved are also converted to the same real address in all eight blocks.
[0044]
The address conversion circuit 15 converts the actual address of the word into 4 bits, and 18 bits are output to the address bus 16 together with the 7-bit track address and the 7-bit block address.
[0045]
The address output to the address bus 16 and the word data output to the data bus 17 are supplied to the D-RAM 1 via the interface circuit 18 to execute write access. Conventionally, FIG. As shown in (h), P at each timing of the word addresses 0Ch to 1Fh._ODEach word up to R8 has been written in the D-RAM1. That is, 20 row accesses were executed per block.
[0046]
However, in this embodiment, the reproduction control circuit 10 takes in the count value of the word counter 13, and at the timing when the count value is set to “0Bh”, as shown in FIG. 2 (i) or (j), A read request is issued.
At this time, the count value “0Bh” of the word counter 13 is converted to “1Bh” and supplied to the address conversion circuit 15 as described above. The block address is a block address subjected to interleaving corresponding to the word address “1Bh”.
[0047]
That is, in response to a read request to the D-RAM 1 at the timing when the count value is set to “0Bh”, data stored as the word address “1Bh” at the block address to be written for the current data block is read. That is, the state of the error flag at the block address to be written is read.
The read error flag is latched in the error flag latch circuit 27, and the error flag state is detected by the reproduction control circuit 10.
[0048]
Here, when the error flag is “1”, the data stored in the block address is already D / A converted and output, and then the data block (CRC safe and This is a case where the data of the data block is not stored.
Therefore, the reproduction control circuit 10 continues to operate the word counter 13 and writes words corresponding to 0C to 1F to the D-RAM 1 as shown in FIG. At this time, “0” is written for each word as an error flag.
[0049]
On the other hand, when the error flag read by the read request to the D-RAM 1 at the timing when the count value is set to “0Bh” and latched in the error flag latch circuit 27 is “0”, the block address is already set. Is a case where a data block which has become CRC safe is written.
In this case, since it is not necessary to write the current data block to the D-RAM 1, writing to the D-RAM 1 of words corresponding to 0C to 1F is prohibited as shown in FIG.
[0050]
As the write prohibition process, the count operation of the word counter 13 may be stopped, or the write prohibition may be performed without generating a write request while continuing the count operation.
The error flag latch circuit 27 is not always necessary. For example, the reproduction control circuit 10 may directly take in an error flag and determine whether to continue / stop the count operation of the word counter 13 according to the error flag.
[0051]
With the above processing, in this embodiment, the access operation to the D-RAM 1 is 21 times as shown in FIG. 2 (i) when necessary, and when it is unnecessary, that is, when the data block has already been written. Since no write access is performed, only read access for error flag check is performed once as shown in FIG.
In the conventional example, the data block read from the tape is always written in the D-RAM 1, and therefore, all the read blocks are accessed 20 times as shown in FIG. 2 (h). Is executed.
[0052]
Here, it is assumed that a data block (data block that has become CRC safe) that is twice the average of the number of block addresses on the D-RAM 1 has been transferred. That is, it is assumed that the same safe block is transferred to the D-RAM 1 twice. Then, conventionally, 40 accesses are performed for the block, whereas in this embodiment, (21 × 1 + 1 × 1) = 22, ie, 22 accesses. In other words, the number of accesses is 0.55 times the conventional number, which is significantly reduced.
[0053]
Therefore, in this embodiment, the power consumption required for accessing the D-RAM 1 can be reduced, and the current for charging / discharging the capacity of the terminal connected to the D-RAM 1 and the substrate pattern can be reduced. As a result, power saving as a whole system is promoted. For example, in the case of battery driving, the battery life can be extended.
Furthermore, since the number of accesses is reduced, system noise due to spike current at the time of access can be reduced.
[0054]
By the way, various IDs, music cueing signals, and the like are recorded in the CTL block. The system controller of the digital audio tape recorder of the embodiment communicates via the interface circuit 18 and is stored on the D-RAM 1. The CTL contents are read / written.
[0055]
However, if the error flag of the area where the CTL block is stored is not set by hardware, writing of new data is prohibited, so that it is necessary to write error flag = 1 from the system controller.
At this time, if the error flag is written for all the words, the error flag for each word becomes effective, but the number of communication by software increases. Therefore, an error flag is written only for a specific word, that is, an R6 word having a word address = 1Bh.
Then, writing of new data to the D-RAM 1 is permitted, and the error determination of the entire CTL block can be performed by the error flag of this word.
[0056]
As another embodiment, in order to improve the error rate in a digital tape recorder, it is conceivable to provide two sets of A / B azimuth reproducing heads and reproduce a track at a density four times that at the time of recording.
In this case, a double azimuth A / B head and another pair of A '/ B' heads are arranged at positions almost opposite to each other by 180 ° on the drum, and are switched by a 4-input head amplifier to form two channels. Two systems of write circuits up to the D-RAM 1 shown in FIG.
In such a configuration, the number of times the same data block on the tape can be read is distributed between approximately 2 to 4 times.
[0057]
Suppose that an average of four times as many data blocks (data blocks that have become CRC safe) with respect to the number of block addresses on the D-RAM 1 have been transferred. That is, it is assumed that the same block that has become safe is transferred to the D-RAM 1 four times. Then, conventionally, 80 accesses are executed for the block, whereas in this embodiment, (21 × 1 + 1 × 3) = 24, that is, 24 accesses. In other words, the number of accesses is 0.3 times that of the conventional 80 times, which is significantly reduced. That is, the effect of reducing power consumption and system noise according to the present invention is greater.
[0058]
Various configurations other than those shown in FIG. 1 are possible for realizing the present invention. The present invention is not limited to digital audio tape recorders and can be employed in various devices.
[0059]
【The invention's effect】
As described above, according to the present invention, a data block as a processing unit is configured by a plurality of words, and a data block to be written to the same address on the memory may be transferred to the memory a plurality of times. In a certain system, once a necessary data block is once written in a memory, an error flag is turned off for the data block, and an error flag is turned on for a data block that is no longer needed. When a certain data block is transferred to the memory and written, the error flag is checked for the data stored at the address to be written. If the error flag is off, the data is transferred. The write access is not executed on the assumption that the same data as the data is already stored.
As a result, unnecessary access operations can be eliminated, and the number of accesses can be reduced. Thus, the effects of reducing power consumption and system noise can be obtained. In the case of a battery-driven system, the battery life can be extended.
[Brief description of the drawings]
FIG. 1 is a block diagram of an embodiment of the present invention.
FIG. 2 is a waveform diagram for explaining the operation of the embodiment.
FIG. 3 is an explanatory diagram of a non-tracking recording / reproducing operation.
FIG. 4 is an explanatory diagram of a track data format of a non-tracking method.
FIG. 5 is an explanatory diagram of addresses of a D-RAM installed in the embodiment.
FIG. 6 is an explanatory diagram of word address conversion processing in the embodiment.
[Explanation of symbols]
1 D-RAM
2 Rotating head
6 Demodulator circuit
7 Delay circuit
8 Serial / parallel converter
9 CRC processing section
10 Playback control circuit
11 Data latch circuit
12 Block address latch circuit
13 word counter
14 Read word converter
15 Address conversion circuit
16 Address bus
17 Data bus
18 Interface circuit
19 DA output / error set address generation circuit
20 Error correction / PQ set control circuit
21 Error correction / PQ set processing circuit
22 DA data latch circuit
23 Decompression circuit
24 Interpolator
25 D / A converter
27 Error flag latch circuit

Claims (3)

As a memory access method when a data block as a processing unit is configured with a plurality of words and a data block to be written to the same address on the memory may be transferred to the memory multiple times,
With respect to the storage area serving as the address of each data block, at the time when the necessary data block is stored, at least a predetermined word in the data block is in a storage state in which the error flag is turned off,
In addition, at the time when the stored data block is no longer necessary for the storage area serving as the address of each data block unit, the storage state where the error flag for at least a predetermined word in the data block is turned on,
After determining the error status for the transferred data block, when writing to the memory of the data block determined to be writable to the memory based on the determination result , the data block should be written. The error flag for the predetermined word at the address is inspected, and if the error flag is on, the write access operation is executed, and if the error flag is off, the write access operation is not executed. Memory access method. A memory control device in a data transfer system in which a data block as a processing unit is configured by a plurality of words and a data block to be written to the same address on the memory may be transferred to the memory a plurality of times As
For the storage area that is the address of each data block unit, at the time when the necessary data block is stored, at least a predetermined word in the data block is in a storage state in which the error flag is turned off, and each When a stored data block is no longer needed for a storage area serving as an address in units of data blocks, a storage state in which an error flag for at least a predetermined word in the data block is turned on can be set. Error flag setting means,
Determining means for determining whether or not writing to the memory is possible based on an error state of the transferred data block;
An error flag checking means for checking an error flag for the predetermined word at an address where the data block is to be written in response to the transfer of the data block;
The determination means determines that writing to the memory is possible, and if the error flag checking means detects that the error flag is turned on, it executes a write access operation to the memory for the transferred data block, An access control means for prohibiting a write access operation to the memory for the transferred data block when the flag is detected to be off;
A memory control device comprising: A recording medium on which a data block having an address as a processing unit is recorded in a plurality of words, and a plurality of data blocks having the same address is recorded on the recording medium, and the data block is reproduced from the recording medium In the playback device,
Reproducing means for reproducing a data block from the recording medium;
Determining means for determining an error state of the reproduced data block;
Storage means for storing the data block;
Holding means for holding an error flag in units of data blocks stored in the storage means;
Setting means for setting a predetermined error flag held in the holding means;
Determination means for determining a set state of the error flag held in the holding means;
Output means for reading out and outputting the data blocks stored in the storage means;
When the data block stored in the storage means is output by the output means and becomes unnecessary, the setting means is controlled so that the error flag held in the holding means is set, and the reproducing means is When the determination means determines that the data block reproduced in this way can be stored in the storage means, and the error flag held in the holding means is set. If it is determined by the determination means, the reproduced data block is stored in the storage means, the error flag held in the holding means is reset, and the data block reproduced by the reproduction means is Even if it is determined by the determination means that the storage means can be stored, if the determination means determines that the error flag held in the holding means is reset, the reproduction is performed. Control means for prohibiting storage of the data block in the storage means;
A playback device comprising:

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