JP3658089B2 - Liquid crystal display panel and liquid crystal display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a liquid crystal display panel and a liquid crystal display device.
[0002]
[Prior art]
An active matrix liquid crystal display panel using a thin film transistor (TFT) includes a TFT substrate on which a TFT is formed, a counter substrate facing the TFT substrate, and a liquid crystal material sandwiched between the two substrates.
[0003]
On the opposing surface of the TFT substrate, there are provided a plurality of data bus lines arranged in parallel to each other and a plurality of gate bus lines arranged so as to intersect with each other and in parallel to each other. A scanning signal is applied to the gate bus line, and an image signal is applied to the data bus line. A transparent pixel electrode is disposed in a region surrounded by the gate bus line and the data bus line.
[0004]
Each pixel electrode is connected to one data bus line by a TFT provided for each pixel electrode. The gate electrode of each TFT is connected to one gate bus line, and the conduction state is controlled by a scanning signal applied to the gate bus line.
[0005]
A transparent common electrode common to all pixels is provided on the opposite surface of the opposite substrate. In addition, in order to prevent the generation of photoexcitation current excited in the TFT by light incident from the counter substrate side, and to shield the leakage light from between the data bus line, the gate bus line and the pixel electrode, A light shielding film is disposed in a predetermined region on the facing surface.
[0006]
By accurately aligning the area (opening) of the counter substrate that is not covered with the light-shielding film and the transparent pixel electrode of the TFT substrate, only the light incident on the area where the transparent pixel electrode is formed is transmitted. It is possible to block the light incident on the other area. Actually, the light-shielding film and the transparent pixel electrode are designed to overlap with each other with a width of about several μm to 7 μm in order to provide an alignment margin between the counter substrate and the TFT substrate.
[0007]
Since it is necessary to provide an alignment margin, the aperture ratio of the liquid crystal display panel is lowered. In a projection type liquid crystal display panel in which the area of one pixel is smaller than that of a direct view type liquid crystal display panel, a decrease in aperture ratio becomes a particularly serious problem. Increasing the luminance of the light source can compensate for a decrease in the aperture ratio, but problems such as the size of the light source and a rise in the temperature of the liquid crystal display panel occur.
[0008]
In order to increase the aperture ratio of the liquid crystal display panel, a configuration has been proposed in which the outer edge portion of the transparent pixel electrode is disposed so as to overlap the bus line. With this configuration, there is no leakage light from between the transparent electrode and the bus line, so there is no need to provide a light-shielding film in this portion. For this reason, it is possible to prevent a decrease in the aperture ratio due to the overlap between the light shielding film and the transparent pixel electrode.
[0009]
[Problems to be solved by the invention]
When the outer edge portion of the transparent pixel electrode and the data bus line are arranged so as to overlap each other, the parasitic capacitance between the transparent pixel electrode and the data bus line is increased. Due to this parasitic capacitance, the potential of the transparent pixel electrode varies under the influence of the voltage change of the data bus line. If the fluctuation of the potential of the transparent pixel electrode exceeds one gradation, crosstalk occurs.
[0013]
  The object of the present invention is toOfAn object of the present invention is to provide a liquid crystal display panel capable of increasing the aperture ratio while suppressing generation.
[0014]
[Means for Solving the Problems]
According to an aspect of the present invention, the first and second substrates arranged opposite to each other with the opposing surfaces facing each other, the common electrode formed on the opposing surface of the second substrate, and the first A plurality of gate bus lines formed on the opposing surface of the substrate and arranged in parallel to each other, and formed on the opposing surface of the first substrate and extending in a direction intersecting with the gate bus lines, A plurality of data bus lines arranged in parallel to each other, and each region formed on the opposing surface of the first substrate and surrounded by the two gate bus lines and the two data bus lines adjacent to each other. The pixel electrodes are arranged correspondingly, and are arranged so that the outer edge of each pixel electrode overlaps at least one of the data bus lines on both sides thereof, and one pixel electrode and two adjacent data buses Capacitance between the line_DSA total capacitance between one pixel electrode and two adjacent gate bus lines, two data bus lines, and the common electrode is represented by C_PXWhen
[0015]
[Expression 4]
8C_DS<C_PX
And a switching element formed on the opposing surface of the first substrate, provided corresponding to the pixel electrode, and connecting the corresponding pixel electrode and one data bus line In addition, a liquid crystal display panel having the switching element whose conduction state is controlled by one gate bus line is provided.
[0016]
Capacitance C_DSIs 8 times the capacitance C_PXIn the case of 16 gradation display, the fluctuation width of the pixel voltage of the non-scanning pixel when the voltage of the data bus line fluctuates from the center to the end of the voltage fluctuation range in one gradation is displayed. It can be suppressed below the corresponding voltage width.
[0017]
According to another aspect of the present invention, the first and second substrates arranged opposite to each other with the opposing surfaces facing each other, a common electrode formed on the opposing surface of the second substrate, and the first A plurality of gate bus lines formed on the opposite surface of the substrate and arranged in parallel to each other, formed on the opposite surface of the first substrate, and extending in a direction intersecting the gate bus line, A plurality of data bus lines arranged in parallel to each other and each region formed on the opposing surface of the first substrate and surrounded by two adjacent gate bus lines and two data bus lines The pixel electrode is arranged corresponding to the pixel electrode, and the pixel electrode is arranged so that an outer edge portion of each pixel electrode overlaps at least one of the data bus lines on both sides of the pixel electrode. Switching element formed on the surface A switching element that is provided corresponding to the pixel electrode, connects the corresponding pixel electrode and one data bus line, and the conduction state is controlled by one gate bus line. A liquid crystal display panel and a drive circuit for driving the liquid crystal display panel so that the number of gradations is n, between one pixel electrode and two adjacent data bus lines The capacitance of C_DSA total capacitance between one pixel electrode and two adjacent gate bus lines, two data bus lines, and the common electrode is represented by C_PXWhen
[0018]
[Equation 5]
nC_DS<2C_PX
Is provided.
[0019]
Capacitance C_DSN times the capacitance C_PXWhen the gray scale display is performed, the fluctuation range of the pixel voltage of the non-scanning pixel when the voltage of the data bus line fluctuates from the center to the end of the voltage fluctuation range is displayed. The voltage width corresponding to the gradation can be suppressed.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
With reference to FIG. 1 and FIG. 2, the problem of the prior art and the solution of the problem according to the embodiment of the present invention will be described.
[0024]
FIG. 1A shows an equivalent circuit and a driving circuit for one pixel of an active matrix liquid crystal display panel using TFTs. TFTs 3 are arranged at intersections between a plurality of data bus lines 1 arranged in parallel to each other and a plurality of gate bus lines 2 orthogonal thereto. Each data bus line 1 is supplied with an image signal from the driving circuit 5, and the gate bus line 2 is supplied with a scanning signal from the driving circuit 5. The drain terminal 3D of the TFT 3 is connected to one data bus line 1, the gate terminal 3G is connected to one gate bus line 2, and the source terminal 3S is connected to the pixel electrode 4.
[0025]
Parasitic capacitance between the pixel electrode 4 and the data bus line 1 on both sides thereof is represented by C_DSThe parasitic capacitance between the gate bus line 2 for controlling the TFT 3 connected to the pixel electrode 4 and the pixel electrode 4 is represented by C_GS, The auxiliary capacitance between the other gate bus line 2 and the pixel electrode 4 is C_SAnd The capacitance between each pixel electrode 4 and the common electrode facing the liquid crystal layer across the liquid crystal layer is represented by C_LCAnd As will be described later, the auxiliary capacity C_SIs designed to be as large as possible.
[0026]
FIG. 1B shows the voltage dependence of the light transmittance of the liquid crystal display panel. The horizontal axis represents the voltage (pixel voltage) between the pixel electrode and the common electrode, and the vertical axis represents the light transmittance. Pixel voltage is V_off, The transmittance is high (white display) and the voltage is V_onIn this case, the transmittance is low (black display). Voltage V_onAnd V_offBy dividing the voltage range of the difference ΔV with respect to n equally and applying a voltage corresponding to each dividing point, display of n gradations can be performed. Voltage V_offAnd V_onAverage voltage V_mid, The light transmittance is an average value of the white display state and the black display state, and gray is displayed.
[0027]
FIG. 1C shows an example of temporal changes in voltages of the data bus line 1, the gate bus line 2, and the pixel electrode 4. Solid line V in the figure_DAnd V_GIs a voltage applied to one data bus line 1 and gate bus line 2 corresponding to the pixel of interest, and a broken line V_SRepresents the voltage of the pixel electrode 4.
[0028]
Time t₁, A pulse voltage is applied to the gate bus line 2, and the pixel of interest is scanned. Voltage V_GThe TFT is in a conductive state during the period when is high. When grayed out, the time t₁Voltage V_DV_midTo be equal to Time t₁Since the TFT 3 becomes conductive, the pixel voltage V_SAlso V_midIs equal to
[0029]
Voltage V_GFalls, the TFT 3 becomes non-conductive, and the pixel voltage V_SIdeally, the time t when the scanning of the next frame is started after the elapse of one frame period T.₂Maintain a constant voltage until However, in practice, the parasitic capacitance C_DSAffected by the pixel voltage V_SVaries as described below.
[0030]
When the scanning of the pixel of interest ends, the voltage V_DChanges corresponding to the display state of the pixel to be scanned next. For example, when the pixel to be scanned next is displayed in black, the voltage V as shown in FIG._DV_midTo V_offTo lower. Voltage V_DDecreases, the parasitic capacitance C_DSAffected by the pixel voltage V_SAlso decreases. In this way, the pixel voltage V in accordance with the voltage change of the data bus line 1 disposed adjacent to the pixel electrode._SFluctuates and crosstalk occurs.
[0031]
In the case of frame inversion driving, the scanning start time t of the next frame₂Just before the voltage V_D-V_midEqual to At this time, the voltage V_DCorresponding to the change in pixel voltage V_SAlso decreases. Since the period after this voltage drop is very small compared to one frame period T, the display quality is not greatly affected.
[0032]
In order to suppress the occurrence of crosstalk, the variation width ΔV of the pixel voltage at the end of scanning_SIs preferably reduced. In addition, as shown in FIG._SIs V_midWhen changing in the vicinity, the change rate of the transmittance becomes the largest. For this reason, the pixel voltage V_SIs V_midCrosstalk is likely to occur in pixels substantially equal to Pixel voltage V_SIs almost V_midIn order to suppress the occurrence of crosstalk in a pixel equal to the voltage V of the data bus line 1 after the scanning of the pixel is completed._DIs V_midTo V_offOr V_onThe pixel voltage V when changing with a width of ΔV / 2 until_SFluctuation range ΔV_SIs preferably smaller than the voltage width for one gradation. That is, the pixel voltage V_SFluctuation range ΔV_SThe
[0033]
[Expression 7]
ΔV_S<ΔV / n (1)
It is preferable that Here, n is the number of gradations.
[0034]
Pixel voltage V_SFluctuation range ΔV_SIs
[0035]
[Equation 8]
ΔV_S= (C_DS/ C_PX) (ΔV / 2) (2)
It can be expressed. Where C_PXIs the total capacitance C of the pixel electrode 4_DS+ C_GS+ C_LC+ C_SIt is.
[0036]
From equations (1) and (2)
[0037]
[Equation 9]
nC_DS<2C_PX                                    ... (3)
Is guided.
[0038]
For example, 8C_DS<C_PXBy satisfying the above, it is possible to effectively suppress the crosstalk in the liquid crystal display panel displaying 16 gradations. 32C_DS<C_PXBy satisfying the above, it is possible to effectively suppress the crosstalk in the 64-tone display liquid crystal display panel. 128C_DS<C_PXBy satisfying the above, it is possible to effectively suppress the crosstalk in the 256 gradation display liquid crystal display panel.
[0039]
In FIG. 1C, the influence on the display quality due to the parasitic capacitance between the pixel electrode and the data bus line has been described. Next, the influence on the display quality due to the parasitic capacitance between the pixel electrode and the gate bus line will be described.
[0040]
FIG. 2A illustrates an example of a change over time of voltages applied to the data bus line 1, the gate bus line 2, and the pixel electrode 4 illustrated in FIG. Solid line V in the figure_GRepresents the voltage of the gate bus line 1, and the solid line V_D(on) and V_D(off) represents the voltage of the data bus line 1 corresponding to the pixels in the black display state and the white display state, respectively, and the broken line V_S(on) and V_S(off) represents the pixel voltage of the pixel in the black display state and the white display state, respectively.
[0041]
Time u₁Scanning is completed and the voltage V_GFalls, the parasitic capacitance C shown in FIG._GSAffected by the pixel voltage V_S(on) and V_S(off) decreases. One frame period T has passed and time u₂Similarly, the pixel voltage V_S(on) and V_S(off) decreases. In the case of FIG. 1C, the pixel voltage V_SRegardless of positive or negative, the pixel voltage V at the end of scanning_SChanges in a direction to decrease its absolute value. On the other hand, in the case of FIG._SWhen is positive, the absolute value is decreased, and when it is negative, the absolute value is increased.
[0042]
Pixel voltage V_SChange width ΔV_SIs
[0043]
[Expression 10]
ΔV_S= (C_GS/ C_PX) ΔV_G                      ... (4)
It is expressed. Where ΔV_GIs a voltage corresponding to the pulse height of the pulse voltage applied to the gate bus line 2. That is, ΔV_GCorresponds to the difference between the gate voltage for turning on the TFT 13 and the gate voltage for turning off the TFT 13.
[0044]
  Pixel is in black display state (V_S= V_S(on)) and white display state (V_S= V_S(off)), since the dielectric constant of the liquid crystal layer differs, the capacitance C across the liquid crystal layer_LCIs also different. Therefore, the total capacity of the pixel electrode in the black display stateC _PX2 Total capacity of pixel electrode in white and white display stateC _PX1 Are different from each other. From equation (4)
[0045]
## EQU11 ##
  ΔV_S(on) = (C_GS/C _PX2 ) ΔV_G
ΔV_S(off) = (C_GS/C _PX1 ) ΔV_G... (5)
Is derived. Where ΔV_S(on) and ΔV_S(off) is the pixel voltage V of the pixel in the black display state and the white display state, respectively._SThe fluctuation range.
[0046]
As shown in the equation (5), the pixel voltage V is applied to the black display pixel and the white display pixel._SThe fluctuation range is different from each other. Therefore, the pixel voltage V of the pixel in the black display state_S(on) amplitude center value V_C(on) and pixel voltage V of the white display pixel_S(off) amplitude center value V_C(off) is different from each other.
[0047]
The common electrode potential is the center value V_C(on) and V_C(off), the pixel voltage V V_SDC component remains. This direct current component causes screen burn-in.
[0048]
FIG. 2B shows a voltage change when a DC component elimination circuit for removing a DC component is added to the drive circuit 5 of FIG. 1A in both the black display state and the white display state pixels. An example is shown. The difference from FIG. 2A is that the voltage V applied to the data bus line 1 is different._DIn addition, a DC bias voltage corresponding to each of the black display and white display states is applied.
[0049]
That is, the voltage V_D(on) includes ΔV_SDC bias voltage equivalent to (on), voltage V_D(off) includes ΔV_SA DC bias voltage corresponding to (off) is given in advance. For this reason, the pixel voltage V_S(on) amplitude center value and V_SThe center value of the amplitude of (off) can be matched. This DC bias voltage is given by a DC component elimination circuit in the drive circuit 5.
[0050]
Thus, by applying a DC bias voltage corresponding to the display state to the voltage applied to the data bus line 1 in advance, the DC component of the voltage applied to the liquid crystal layer can be removed. However, in order to obtain a sufficient DC component removal effect by applying a DC bias voltage corresponding to the display state of the pixel by the DC component elimination circuit, the pixel voltage V_SVariation ΔV_S(on) and ΔV_SThe difference from (off) is preferably less than 1V.
[0051]
That is, from equation (5),
[0052]
[Expression 12]
((1 /C _PX1 )-(1 /C _PX2 ) ・ C_GS・ ΔV_G<1 ... (6)
It is preferable that
[0053]
From the equations (3) and (6), the parasitic capacitance C between the pixel electrode and each bus line._DSAnd C_GSTo reduce the total capacity C_PXIt can be seen that it is preferable to increase. Total capacity C_PXAs one method for increasing the capacitance, the capacitance C shown in FIG._SA method of increasing the size is adopted.
[0054]
FIG. 2C shows the capacitance C._SPixel voltage V due to the influence of_SShows fluctuations. Solid line V_DIs the voltage applied to the data bus line, broken line V_SIs pixel G₁Pixel voltage V_SIndicates. Pulse G₁~ G_ThreeAre pixels G arranged continuously along the data bus line.₁~ G_ThreeThese pulses correspond to the scanning signals. As described in FIGS. 2A and 2B, the pulse G₁Falls, the parasitic capacitance C shown in FIG._GSAffected by the pixel voltage V_SDecreases.
[0055]
Pulse G₂Capacitance C at the rise and fall of_SAffected by the pixel voltage V_SRises and falls. Capacitance C_SThe effect of the pulse G₂Occurs at both the rise and fall of the pulse G₂The pixel voltage V before and after being affected by_SHardly fluctuates. Therefore, the capacitance C_SEven if the voltage is positively increased, the pixel voltage V_SHas little effect on Capacitance C_STo increase the pixel voltage V_SRather than the deterioration of display quality due to fluctuations, the total capacity C in equations (3) and (6)_PXThe effect of improving the display quality due to the increase of is large.
[0056]
Next, the configuration of the liquid crystal display panel according to the embodiment of the present invention for satisfying the expressions (3) and (6) will be described with reference to FIG.
[0057]
FIG. 3A is a plan view schematically showing a liquid crystal display panel according to the embodiment.
As shown in FIG. 3A, a plurality of data bus lines 11 arranged in parallel with each other extend in the vertical direction in the figure, and a plurality of gate bus lines 12 arranged in parallel with each other in the horizontal direction in the figure. Extend. A TFT 13 is provided corresponding to the intersection of the data bus line 11 and the gate bus line 12. The drain region 13 </ b> D of the TFT 13 is connected to the corresponding data bus line 11, and the gate electrode 13 </ b> G is continuous with the corresponding gate bus line 12.
[0058]
A pixel electrode 14 is arranged corresponding to a region surrounded by two data bus lines 11 and two gate bus lines 12 adjacent to each other. The pixel electrode 14 is connected to the source region 13S of the corresponding TFT 13. Of the outer edge portion of the pixel electrode 14, portions other than the portion facing the TFT 13 overlap the bus lines 12 and 13. A light shielding film 16 is disposed corresponding to the region where the TFT 13 is disposed. The entire rectangular area surrounded by the two gate bus lines 12 and the two data bus lines 11 adjacent to each other is completely covered with either the light shielding film 16 or the pixel electrode 14.
[0059]
FIG. 3B is a cross-sectional view taken along one-dot chain line B3-B3 in FIG. Glass substrates 20 and 30 are arranged in parallel to each other. On the opposing surface of the glass substrate 20, a gate electrode 13G made of chromium (Cr) is formed. The gate electrode 13G is formed, for example, by depositing a Cr film over the entire region on the opposing surface of the glass substrate 20 by sputtering and then patterning the Cr film. By patterning the Cr film, the gate bus line 12 continuing to the gate electrode 13G shown in FIG.
[0060]
On the opposing surface of the glass substrate 20, a gate insulating film 21 made of SiN and having a thickness of about 330 nm is formed so as to cover the gate electrode 13G. The gate insulating film 21 is formed by, for example, chemical vapor deposition (CVD). An amorphous silicon film 13C having a thickness of about 150 nm is formed in a region where a TFT is to be formed in a region on the surface of the gate insulating film 21.
[0061]
A source electrode 13S and a drain electrode 13D each having a three-layer structure of Ti / Al / Ti are formed in regions corresponding to the source and drain in the region on the surface of the amorphous silicon film 13C. The thickness of the lower Ti layer is about 20 nm, the thickness of the Al layer is about 50 nm, and the thickness of the upper Ti layer is about 80 nm. The drain electrode 13D is formed simultaneously with the data bus line 11 continuous with the drain electrode 13D shown in FIG.
[0062]
The amorphous silicon film 13C is deposited, for example, by using SiH as a source gas._FourThe patterning is performed by etching using a plasma asher using the resist pattern as a mask. The Ti layer and the Al layer are deposited by sputtering, and the patterning is performed by etching using a resist pattern as a mask and wet processing.
[0063]
An interlayer insulating film 22 having a thickness of about 2 μm is formed on the surface of the gate insulating film 21 so as to cover the TFT 13. The interlayer insulating film 22 is formed, for example, by spin coating an acrylic resin LC-201 manufactured by Sanyo Chemical. The relative dielectric constant of the acrylic resin LC-201 is about 3. The surface of the interlayer insulating film 22 becomes almost flat.
[0064]
A plurality of transparent pixel electrodes 14 made of indium tin oxide (ITO) are formed on the surface of the interlayer insulating film 22. Each transparent pixel electrode 14 is connected to the source electrode 13 </ b> S of the TFT 13 through a contact hole formed in the interlayer insulating film 22. An alignment film 23 is formed on the entire surface so as to cover the transparent pixel electrode 14.
[0065]
On the opposite surface of the glass substrate 30, a light shielding film 16 made of Cr and having a thickness of about 120 nm is formed corresponding to the region where the TFT 13 is formed. The light shielding film 16 is formed by depositing a Cr film on the entire surface by sputtering, for example, and then patterning by etching using a wet process.
[0066]
A transparent common electrode 31 made of ITO is formed on the entire surface so as to cover the light shielding film 16, and an alignment film 32 is formed on the surface. A liquid crystal material 40 is sandwiched between the alignment films 23 and 32.
[0067]
The width of the data bus line 11 shown in FIG. 3A is 6 μm, the width of the gate bus line 12 is 15 μm, the pitch of both bus lines is 100 μm, the pixel electrode 14 and the data bus lines 11 on both sides thereof and the corresponding gate buses. The overlapping width with the line 12 is 2 μm, and the area of the rectangular area surrounded by the data bus line 11 and the gate bus line 12 is shielded by the light shielding film 16 is about 1400 μm.²It was.
[0068]
Note that the overlapping width of the pixel electrode 14 and the gate bus line 12 corresponding to the adjacent pixel is increased in order to increase the capacitance. Further, by arranging an auxiliary electrode connected to the pixel electrode 14 at the interface between the gate insulating film 21 and the interlayer insulating film 22 shown in FIG. 3B, a substantial distance between the pixel electrode 14 and the gate bus line. Is shortened.
[0069]
At this time, the parasitic capacitance C shown in FIG._GSIs 27.8 fF, parasitic capacitance C_DSIs 6.2 fF, capacitance C_SIs 245fF, voltage V_offCapacitance C when applied_LC(off) is 150.8 fF, voltage V_onCapacitance C when applied_LC(on) was 307.8 fF. When these numerical values are applied to the equation (3), the inequality is established when the number of gradations n is 138 or less. In other words, it is possible to display a maximum of 138 gradations while suppressing the occurrence of crosstalk.
[0070]
When these numerical values are applied to the equation (6), ΔV_GThe inequality holds when 5 is below 57.8V. That is, the voltage difference ΔV between the gate bus line voltage during scanning and the non-scanning gate bus line voltage._GIs driven to be 57.8 V or less, the equation (6) is satisfied. Since the difference between the on level and the off level of the gate voltage of a normal TFT is 57.8 V or less, the liquid crystal display panel shown in FIG. 3 satisfies Expression (6).
[0071]
As shown in FIG. 3B, by forming an interlayer insulating film 22 having a relative dielectric constant of 3 and a thickness of about 2 μm between the pixel electrode 14 and the data bus line 11 and the gate bus line 12, the pixel electrode It is possible to reduce the parasitic capacitance between the bus line 14 and the bus lines 11 and 12 disposed adjacent thereto. By reducing the parasitic capacitance, as described in FIGS. 1 and 2, the expressions (3) and (6) are satisfied, and the occurrence of crosstalk and screen burn-in can be suppressed.
[0072]
In order to obtain a sufficient effect of reducing the parasitic capacitance, the relative dielectric constant of the interlayer insulating film disposed between the pixel electrode 14 and the bus lines 11 and 12 is 3.5 or less and the film thickness is 1.5 μm. The above is preferable. In the above embodiment, the case where an acrylic resin is used as the interlayer insulating film 22 has been described. However, other materials may be used as long as the relative dielectric constant and the film thickness are within these ranges. For example, a photosensitive resin used in a semiconductor process may be used. When a photosensitive resin is used, patterning can be easily performed by exposure and development.
[0073]
Next, another effect of the liquid crystal display panel shown in FIG. 3 will be described with reference to FIG.
FIG. 4A is a schematic cross-sectional view for illustrating the relative positional relationship between the pixel electrode 14 and the gate bus line 12. Each component is denoted by the same reference numeral as the corresponding component in FIG. Note that description of a gate insulating film and the like is omitted for simplification.
[0074]
When a potential difference is generated between the pixel electrode 14 and the gate bus line 12, an electric field E is generated between the vicinity of the end of the pixel electrode 14 and the gate bus line 12. This electric field E hardly penetrates into the liquid crystal layer.
[0075]
FIG. 4B shows the case of a conventional liquid crystal display panel. Instead of the interlayer insulating film 22 in FIG. 4A, a thinner interlayer insulating film 22a is formed. The pixel electrode 14 is arranged so that its outer edge does not overlap the gate bus line 12. In this case, an electric field E is generated in the lateral direction between the end of the pixel electrode 14 and the gate bus line 12.
[0076]
A part of the lateral electric field E enters the liquid crystal layer. Under the influence of the transverse electric field E that has entered the liquid crystal layer, the alignment of the liquid crystal molecules is disturbed, and the disorder of the alignment causes the display quality to deteriorate. On the other hand, in the case of FIG. 4A, since a horizontal electric field is not generated in the liquid crystal layer, display quality deterioration due to the horizontal electric field can be prevented.
[0077]
In the case of FIG. 4B, unevenness is formed on the substrate facing surface in the vicinity of the gate bus line 12. This unevenness causes the arrangement of liquid crystal molecules to be disturbed. On the other hand, in the case of FIG. 4A, since the surface of the interlayer insulating film 22 is substantially flat, it is possible to prevent the disorder of the alignment of the liquid crystal molecules due to the unevenness of the surface facing the substrate.
[0078]
Although FIG. 3 illustrates the case where the light shielding film is provided on the counter substrate side, it may be provided on the TFT substrate side.
[0079]
FIG. 5 is a cross-sectional view of a liquid crystal display panel in which a light shielding film is provided on the TFT substrate side. A black resin 41 is formed so as to cover the TFT 13. The black resin 41 is disposed in a region substantially similar to the light shielding film 16 illustrated in FIG. A light shielding film is not formed on the counter substrate side. Other configurations are similar to those in the case of FIG.
[0080]
When the black resin is formed on the TFT substrate side, it is not necessary to align the TFT substrate and the counter substrate with high accuracy. For this reason, the overlapping portion between the light shielding film 16 and the pixel electrode 14 shown in FIG. 3A can be reduced, and the aperture ratio can be further increased.
[0081]
3 and 4 show the case where the outer edge of the pixel electrode 14 is overlapped with both the data bus line 11 and the gate bus line 12 around the pixel electrode 14, but the pixel electrode 14 may overlap with only one bus line. Further, the data bus line 11 on both sides of the pixel electrode 14 may be configured to overlap with only one data bus line. In this case, a light shielding film is disposed in a region corresponding to a gap between the pixel electrode 14 and the gate bus line and the data bus line that do not overlap with the pixel electrode 14.
[0082]
Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.
[0083]
  As described above, according to the present invention, when the pixel electrode and the bus line are arranged so as to overlap each other and the aperture ratio is increased, an increase in parasitic capacitance between the pixel electrode and the bus line is suppressed, and the crossOfGeneration can be reduced.
[Brief description of the drawings]
FIG. 1 is an equivalent circuit of a pixel of a liquid crystal display panel, a graph showing voltage dependence of light transmittance, a data bus line, a gate bus line, and a pixel electrode for explaining a problem solving method according to an embodiment of the present invention; It is a graph which shows an example of the time change of the voltage of.
FIG. 2 is a graph illustrating an example of a temporal change in voltages of a data bus line, a gate bus line, and a pixel electrode of a liquid crystal display panel for explaining a problem solving method according to an embodiment of the present invention.
3A and 3B are a plan view and a cross-sectional view schematically showing a liquid crystal display panel according to an embodiment of the present invention.
4 is a cross-sectional view schematically showing a TFT substrate for explaining the effect of the liquid crystal display panel shown in FIG.
FIGS. 5A and 5B are a plan view and a cross-sectional view schematically showing a liquid crystal display panel according to a modification of the embodiment of the present invention. FIGS.
[Explanation of symbols]
1,11 Data bus line
2,12 Gate bus line
3, 13 TFT
4,14 Pixel electrode
5 Drive circuit
16 Shading film
20, 30 Glass substrate
21 Gate insulation film
22 Interlayer insulation film
23, 32 Alignment film
31 Common electrode
40 Liquid crystal materials
41 Black resin

Claims (7)

First and second substrates arranged opposite to each other with their opposing surfaces facing each other;
A common electrode formed on the opposing surface of the second substrate;
A plurality of gate bus lines formed on opposite surfaces of the first substrate and arranged in parallel to each other;
A plurality of data bus lines formed on the opposing surface of the first substrate, extending in a direction intersecting with the gate bus lines, and arranged in parallel to each other;
A pixel electrode formed on the opposing surface of the first substrate and disposed corresponding to each region surrounded by two gate bus lines and two data bus lines adjacent to each other, The outer edge portion of the pixel electrode is arranged so as to overlap at least one of the data bus lines on both sides thereof, and the capacitance between one pixel electrode and two adjacent data bus lines is represented by C _DS , 1 When the total capacitance between one pixel electrode and two adjacent gate bus lines, two data bus lines, and the common electrode is C _PX ,

Wherein the pixel electrode holds,
A switching element formed on the opposite surface of the first substrate, provided corresponding to the pixel electrode, connecting the corresponding pixel electrode and one data bus line, and one gate bus A liquid crystal display panel comprising: the switching element whose conduction state is controlled by a line.   And a light-shielding film formed on an opposing surface of at least one of the first and second substrates and disposed in a region where the switching element is disposed, and the light-shielding film includes the pixel electrode. The liquid crystal display panel according to claim 1, wherein the liquid crystal display panel is not disposed in an overlapping area between the data bus line and the data bus line. First and second substrates arranged opposite to each other with their opposing surfaces facing each other;
A common electrode formed on the opposing surface of the second substrate;
A plurality of gate bus lines formed on opposite surfaces of the first substrate and arranged in parallel to each other;
A plurality of data bus lines formed on the opposing surface of the first substrate, extending in a direction intersecting with the gate bus lines, and arranged in parallel to each other;
A pixel electrode formed on the opposing surface of the first substrate and disposed corresponding to each region surrounded by two gate bus lines and two data bus lines adjacent to each other, The pixel electrode disposed so that an outer edge of the pixel electrode overlaps at least one of the data bus lines on both sides thereof;
A switching element formed on the opposite surface of the first substrate, provided corresponding to the pixel electrode, connecting the corresponding pixel electrode and one data bus line, and one gate bus A liquid crystal display panel comprising the switching element whose conduction state is controlled by a line;
A driving circuit for driving the liquid crystal display panel so that the number of gradations is n;
The capacitance between one pixel electrode and two adjacent data bus lines is represented by C _DS , one pixel electrode and two adjacent gate bus lines, two data bus lines, and the common When the total capacitance between the electrodes is C _PX ,

Is a liquid crystal display device. Further, formed on the opposite surface of the first substrate, covers the gate bus line, the data bus line, and the switching element, and has a film thickness of 1.5 μm or more on the gate bus line and the data bus line, a relative dielectric. the liquid crystal display panel according to any one of claims 1 to 3 rate has an interlayer insulating film is 3.5 or less. The liquid crystal display panel according to claim 4 , wherein the interlayer insulating film is formed of an acrylic resin or a photosensitive resin. First and second substrates arranged opposite to each other with their opposing surfaces facing each other;
A common electrode formed on the opposing surface of the second substrate;
A plurality of gate bus lines formed on opposite surfaces of the first substrate and arranged in parallel to each other;
A plurality of data bus lines formed on the opposing surface of the first substrate, extending in a direction intersecting with the gate bus lines, and arranged in parallel to each other;
A pixel electrode formed on the opposing surface of the first substrate and disposed corresponding to each region surrounded by two gate bus lines and two data bus lines adjacent to each other, The outer edge portion of the pixel electrode is arranged so as to overlap at least one of the data bus lines on both sides thereof, and the capacitance between one pixel electrode and two adjacent data bus lines is represented by C _DS , 1 One of the pixel electrode and the two gate bus lines adjacent thereto, when the two data bus lines, and the total capacitance of between the common electrode and the C _PX, the pixel 8C _DS <C _PX is true Electrodes,
A switching element formed on the opposite surface of the first substrate, provided corresponding to the pixel electrode, connecting the corresponding pixel electrode and one data bus line, and one gate bus The switching element whose conduction state is controlled by a line;
A liquid crystal layer sandwiched between the first and second substrates, wherein a refractive index changes according to a change in voltage between the pixel electrode and the common electrode, and a high refractive index state and a low refractive index; A liquid crystal layer having a state and an intermediate refractive index state,
A gate bus line for controlling the switching element connected to one pixel electrode and the pixel electrode, the outer edge of each pixel electrode being arranged to overlap the gate bus line for controlling the switching element connected to the pixel electrode C _GS , the total capacitance between one pixel electrode and two adjacent gate bus lines, two data bus lines, and the common electrode, The capacitance in the high refractive index state is C _PX1 , the capacitance in the low refractive index state is C _PX2 , the gate bus line voltage for making the switching element conductive, and the gate bus line voltage for making the switching element nonconductive. when the absolute value of the difference of the a [Delta] V _G,
| (1 / C _PX1 ) − (1 / C _PX2 ) | · C _GS · ΔV _G <1
A liquid crystal display panel. First and second substrates arranged opposite to each other with their opposing surfaces facing each other;
A common electrode formed on the opposing surface of the second substrate;
A plurality of gate bus lines formed on opposite surfaces of the first substrate and arranged in parallel to each other;
A plurality of data bus lines formed on the opposing surface of the first substrate, extending in a direction intersecting with the gate bus lines, and arranged in parallel to each other;
A pixel electrode formed on the opposing surface of the first substrate and disposed corresponding to each region surrounded by two gate bus lines and two data bus lines adjacent to each other, The pixel electrode disposed so that an outer edge of the pixel electrode overlaps at least one of the data bus lines on both sides thereof;
A switching element formed on the opposite surface of the first substrate, provided corresponding to the pixel electrode, connecting the corresponding pixel electrode and one data bus line, and one gate bus The switching element whose conduction state is controlled by a line;
A liquid crystal layer sandwiched between the first and second substrates, wherein a refractive index changes according to a change in voltage between the pixel electrode and the common electrode, and a high refractive index state and a low refractive index; A liquid crystal display panel comprising the liquid crystal layer having a state and an intermediate refractive index state;
A driving circuit for driving the liquid crystal display panel so that the number of gradations is n;
The capacitance between one pixel electrode and two adjacent data bus lines is represented by C _DS , one pixel electrode and two adjacent gate bus lines, two data bus lines, and the common When the total capacitance between the electrodes is C _PX , nC _DS <2C _PX holds,
A gate bus line for controlling the switching element connected to one pixel electrode and the pixel electrode, the outer edge of each pixel electrode being arranged to overlap the gate bus line for controlling the switching element connected to the pixel electrode C _GS , the total capacitance between one pixel electrode and two adjacent gate bus lines, two data bus lines, and the common electrode, The capacitance in the high refractive index state is C _PX1 , the capacitance in the low refractive index state is C _PX2 , the gate bus line voltage for making the switching element conductive, and the gate bus line voltage for making the switching element nonconductive. when the absolute value of the difference of the a [Delta] V _G,
| (1 / C _PX1 ) − (1 / C _PX2 ) | · C _GS · ΔV _G <1
Is a liquid crystal display device.

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