JP3528674B2 - Image signal processing circuit, electro-optical device, image display device, and image signal supply method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal processing circuit for driving an electro-optical device adopting an active matrix driving method by driving a transistor such as a thin film transistor, and an electro-optical device having such an image signal processing circuit. The present invention relates to an image display device and an image signal supply method.

[0002]

2. Description of the Related Art A drive circuit of an electro-optical device includes a data line drive circuit and a scan line for supplying an image signal and a scan signal to a data line and a scan line wired in an image display area of a display panel at a predetermined timing. It is configured to include a drive circuit, a sampling circuit, and the like.

In such a drive circuit, when the dot-sequential drive system is adopted, one image signal supply line and each data line are provided with a plurality of sampling switches provided corresponding to each data line. Each of them is connected through, and each sampling switch is controlled by a sampling signal sequentially supplied from the data line driving circuit corresponding to each data line,
Thereby, the image signal is supplied to each data line in a dot-sequential manner.

The video transfer frequency in an electro-optical device such as a liquid crystal device tends to become higher and higher due to the recent demand for higher quality display images. When the video transfer frequency is increased in this way, the sampling capability of the above-described sampling switch becomes insufficient, and the delay time in each thin film transistor forming the drive circuit adversely affects the quality of the displayed image. For example, the image signal for the previous data line is written to the next data line, which causes a problem that ghost or crosstalk occurs. However, if the performance itself of the sampling switch and each thin film transistor is improved to cope with this, the cost will be significantly increased.

For this reason, a serial-parallel conversion circuit for preliminarily serial-parallel converting an image signal to divide it into a plurality of parallel image signals is provided in the preceding stage of the drive circuit, and on a plurality of image signal supply lines provided in the electro-optical device. And a plurality of image signals are simultaneously sampled in the sampling circuit to obtain a plurality of image signals (for example, 6
A technique for simultaneously supplying an image signal to two (2, 24, etc.) data lines has been developed. According to this technique, the sampling time of each sampling switch can be increased by about N times according to the number N of data lines driven simultaneously.
The drive frequency of the drive circuit can be reduced to substantially 1 / N. That is, as described above, it is not necessary to improve the performance itself of the sampling switch and each thin film transistor, and it is possible to cope with an increase in the video transfer frequency.

For example, in the XGA system having a display area of 1024 dots × 768 dots, the video transfer frequency is several tens of M.
Since it is as high as Hz, a process for substantially lowering the drive frequency may be performed using the serial-parallel conversion circuit described above. Further, in the SXGA system having a display area of 1280 dots × 1024 dots, the video transfer frequency rises to about 130 MHz, so the number of image signal supply lines provided in the electro-optical device is increased compared to that in the XGA system. It is considered that the electro-optical device is driven at substantially the same frequency as the XGA driving frequency.

[0007]

However, when the video transfer frequency becomes 130 MHz, the operating frequency of the serial-parallel conversion circuit becomes high, and the ICs constituting the serial-parallel conversion circuit become X.
It becomes difficult to manufacture using the same process as the GA method.

In the electro-optical device, it is sometimes desired to reverse the screen display vertically and horizontally. In such a case, it is necessary to reverse the scanning order of each data line and each scanning line. Therefore, when reducing the operating frequency of the serial-parallel conversion circuit, it is necessary to consider this point as well. .

The present invention has been made in view of the above circumstances, and a first object of the present invention is to provide an image processing circuit which can be operated at a low operating frequency even when the video transfer frequency is high, and an electric circuit using the image processing circuit. An object is to provide an optical device, an image display device, and an image signal supply method. A second object is to further provide an image processing circuit capable of reversing the image display direction, an electro-optical device using the same, an image display device and an image signal supply method.

[0010]

In order to achieve the above object, the image processing circuit of the present invention uses N (where N = J × K,
J and K are natural numbers of 2 or more) and are used in an image display device capable of changing the display direction of an image by supplying parallel image signals to two image signal supply lines ,
An image signal of the J system, which is obtained by parallelizing the input image signal by time-expanding it to J times, is output, and the image of the J system is displayed when the control signal indicates the forward direction and the reverse direction. Distributing means for reversing the order of the signals and the J-system image signals are provided in correspondence with the J-system image signals, and the K-system image signals are output in parallel while the one-system image signal is time-expanded K times. , J processing means for reversing the order of the image signals of the K system depending on whether the control signal indicates a forward direction or a reverse direction;
Image signal supply means for supplying J × K image signals output from each processing means to each of the N image signal supply lines according to a corresponding dot order.

According to the present invention, the input image signal is serial-parallel converted by the distributing means to generate the J-system image signal. Further, since the J processing means are for converting the image signal to serial-parallel conversion to generate K image signals, it is necessary to use slow-moving elements as the elements constituting the J processing means. You can
Further, since the image signal supply means supplies the K image signals output from the processing means to the N image signal supply lines in accordance with the corresponding dot order, serial-parallel conversion is separately performed in the J system. Even if is performed, a predetermined image is correctly displayed on a predetermined dot on the screen finally displayed.

The image processing circuit of the present invention is 2N (N is 2 or more).
It is possible to change the display direction of the image by supplying parallel image signals to the (natural number above) image signal supply lines.
A first image signal corresponding to an odd dot and a second image signal corresponding to an even dot, which are used for an image display device, are divided into a first image signal corresponding to an odd dot and a first image signal while time-expanding the input image signal twice. And the first output parallelized from the second output terminal
Of the image signal and the second image signal, and the image signal output from the first output terminal and the second image signal depending on whether the control signal indicates a forward direction or a reverse direction. And an image signal output from the output terminal of the output device is replaced with a distribution means, and the image signal supplied from the first output terminal is time-expanded by N times, and N parallel image signals of N are output. First processing means for reversing the order of the image signals output from the N output terminals while outputting from the output terminals of the control signals and when the control signal indicates the forward direction and the reverse direction. When the image signal supplied from the second output terminal is time-expanded N times and the parallelized N image signals are output from the N output terminals and the control signal indicates the forward direction. And in the opposite direction And second processing means for reversing the order of the image signal outputted from said N output terminals in the case,
The N image signals output from the first processing means and the N image signals output from the second processing means,
Image signal supply means for respectively supplying to the 2N image signal supply lines in accordance with the corresponding dot order.

According to this invention, the input image signal is serial-parallel converted by the distributing means to generate the first image signal and the second image signal. Since the first and second processing means further serial-parallel convert the first or second image signal, their operating frequencies are compared with the case where the input image signal is serial-parallel converted to the 2N system. And becomes 1/2. Therefore, the first
Further, as an element forming the second processing means, an element having a slow operation speed can be used. Further, the image signal supply means outputs N from each of the first and second processing means.
Since each image signal is supplied to each of the 2N image signal supply lines according to the corresponding dot order, even if serial-parallel conversion is separately performed in two systems, a predetermined dot is displayed on the screen finally displayed. Therefore, the predetermined image display is correctly performed. Further, when the control signal indicates the reverse direction, the first and second image signals output from the distribution means are exchanged, and the order of N image signals output from the first and second processing means, respectively. Will be reversed. Therefore, when the control signal indicates the forward direction, the first image signal is output to the first image signal supply line, and the second image signal is output to the second image signal supply line. Similarly, the second N-th image signal supply line
Assuming that the Nth image signal is output, the second Nth image signal is output to the first image signal supply line when the control signal indicates the reverse direction, and the second image signal supply line is output. Then, the 2N-1th image signal is output to, and similarly, the 1st image signal is output to the 2Nth image signal supply line. Therefore, the order of the image signals supplied to the respective image signal supply lines can be reversed. This makes it possible to correctly display a desired image even if the scanning direction of the data lines is reversed when the serial-parallel conversion is performed separately for the two systems.

In the image processing circuit of the present invention, if the first image signal and the second image signal are digital signals, the first processing means performs the digital processing to perform the first processing. Serial-parallel conversion is performed on the image signal of one system supplied from the output terminal of the system to generate a digital image signal parallelized to N systems and output from the N output terminals, and the control signal is in the forward direction. To reverse the order of the digital image signals output from the N output terminals depending on whether to instruct
Serial-parallel conversion unit and N D / A conversion units for converting N digital image signals from digital signals to analog signals, and the second processing unit performs the second processing by digital processing. Serial-parallel conversion is applied to the image signal of one system supplied from the output terminal of
A digital image signal parallelized to the system is generated and output from N output terminals, and output from the N output terminals depending on whether the control signal indicates a forward direction or a reverse direction. A second serial-parallel converter that reverses the order of the digital image signals to be processed, and N D / A converters that convert the digital image signals of N systems from digital signals to analog signals may be provided. Good.
According to this configuration, the first image signal and the second image signal are serial-parallel converted by digital processing.
Further, in this case, the order of the image signals supplied to the respective image signal supply lines can be reversed depending on whether the control signal indicates the forward direction or the reverse direction. This makes it possible to correctly display a desired image even if the scanning direction of the data lines is reversed when the serial-parallel conversion is performed separately for the two systems.

In the image processing circuit of the present invention, if the first image signal and the second image signal are digital signals, an N-phase sampling pulse is generated and the control signal is forwarded. A pulse generator that reverses the order of the N-phase sampling pulses depending on whether a direction is designated or a reverse direction is designated; and the first processing means is a digital signal supplied from the first output terminal. D / for converting image signals from digital signals to analog signals
The second processing means includes an A conversion unit and N sample and hold units that sample and hold an analog image signal in accordance with the N-phase sampling pulses.
A D / A converter that converts the image signal supplied from the second output terminal from a digital signal to an analog signal, and N sample and hold units that sample and hold the analog image signal according to the N-phase sampling pulse. May be provided. According to this configuration, the first image signal and the second image signal are serial-parallel converted by analog processing. Further, in this case, the phase of the sampling pulse supplied to each sample-hold unit is opposite between when the control signal indicates the forward direction and when the control signal indicates the reverse direction. The order of the image signals supplied can be reversed. This makes it possible to correctly display a desired image even if the scanning direction of the data lines is reversed when the serial-parallel conversion is performed separately for the two systems.

In the image processing circuit of the present invention, if the first image signal and the second image signal are digital signals, m (where N = n × m, n, m is 2). A pulse generator that generates the sampling pulse of the above natural number) phase and reverses the order of the sampling pulse of the m-phase when the control signal indicates the forward direction and the reverse direction; The first processing means performs digital processing to perform serial-parallel conversion on the image signals of one system supplied from the first output terminal to generate digital image signals parallelized to n systems to generate n number of digital image signals. The first digital image signal output from the n output terminals is reversed while the control signal indicates the forward direction and the reverse direction. Real-parallel conversion section, n D / A conversion sections for converting n systems of digital image signals from digital signals to analog signals, and m pieces of sample / hold analog image signals according to the m-phase sampling pulses. And a second sample processing unit, wherein the second processing unit performs the second processing by digital processing.
1-system image signals supplied from the output terminals are subjected to serial-parallel conversion to generate digital image signals parallelized to n systems and output from the n output terminals, and the control signal is forwarded. A second serial-parallel conversion unit that reverses the order of the digital image signals output from the n output terminals depending on whether the digital signal is output from the digital signal. It may be provided with n D / A conversion units for converting into analog signals and m sample and hold units for sampling and holding the analog image signals in accordance with the m-phase sampling pulses. According to this configuration, the first image signal and the second image signal are parallelized into n lines by digital processing and further into m lines by analog processing. In this case, by appropriately setting n and m, the burden of digital processing and the burden of analog processing can be allocated, so that the degree of freedom in constructing the image processing circuit can be greatly expanded. Further, since the order of the image signals in each stage is reversed depending on whether the control signal indicates the forward direction or the reverse direction, the order of the image signals supplied to the respective image signal supply lines can be reversed. it can. This allows
Even if the scanning direction of the data line is reversed when the serial-parallel conversion is performed separately for the two systems, the desired image can be displayed correctly.

Next, in the electro-optical device of the present invention, an electro-optical substance is sandwiched between a pair of substrates, and a plurality of data lines and a plurality of scanning lines intersecting each other on one of the pair of substrates. And N (where N = J × K, J and K are natural numbers of 2 or more) image signal supply lines and the plurality of data lines are connected to each other through switching elements, and the data lines are scanned. Changing the display direction of an image by controlling ON / OFF of the switching element based on a control signal indicating a direction and supplying an image signal parallelized for every N adjacent data lines. In the image processing circuit described above, the switching element is turned on.
Whether the sampling signal for controlling the OFF is generated for each data line group composed of N adjacent data lines and the sampling signal is sequentially supplied to each switching element, and whether the control signal indicates the forward direction. And a data line driving circuit for reversing the order of the sampling signals sequentially supplied to each of the data line groups depending on whether a reverse direction is designated.

According to the present invention, the order of the sampling signals sequentially supplied to each data line group is reversed depending on whether the control signal indicates the forward direction or the reverse direction. If the data line is scanned from left to right by sequentially supplying the sampling signal from the leftmost data line group to the rightmost data line group in the case of the direction, in the opposite direction, the right to left data line is obtained. Can be scanned. As a result, it is possible to display an image with left and right reversed.

Next, the image display device of the present invention displays an image in accordance with an input image signal, and controls the electro-optical device described above and the control signal for instructing the display direction of the image. And a signal generating means. The image display device corresponds to, for example, a projection type projector, a video camera, or the like.

Next, in the image signal supplying method of the present invention, N (where N = J × K, J and K are natural numbers of 2 or more)
It is premised that the image display device can change the display direction of the image by supplying the parallel image signal to the image signal supply line of the book. An image signal of the converted J system is generated, and the order of the J image signals to be distributed to the J processing systems is reversed depending on whether the control signal indicates the forward direction or the reverse direction. In the first step and each processing system, K image signals are generated by parallelizing the supplied image signal by time-expanding K times, and the control signal indicates the forward direction or the backward direction. The second step of reversing the order of each of the K image signals and the J × K image signals output from the processing systems according to the corresponding dot order. Provide each for the image signal supply line Characterized in that it comprises a third step of. According to the present invention, the operating frequency of the processing system can be reduced, and even if the J-system performs serial-parallel conversion separately, a predetermined image can be displayed on a predetermined dot on a screen finally displayed. It can be displayed correctly.

Further, according to the image signal supplying method of the present invention, the image signals are supplied in parallel to the 2N (N is a natural number of 2 or more) image signal supplying lines, so that the image Is used in an image display device whose display direction can be changed, and on the assumption that 2N image signals parallel to 2N image signal supply lines are supplied, the input image signal is doubled in time. When the first image signal corresponding to odd-numbered dots and the second image signal corresponding to even-numbered dots are separated, and the control signal indicates the forward direction, the first image signal is changed to the first image signal.
Output to the second processing system and the second image signal to the second processing system, and when the control signal indicates the reverse direction, the second image signal is output to the first processing system. And a first step of outputting the first image signal to a second processing system, and the first processing system,
The supplied image signal is expanded N times to be parallelized while generating N image signals. In the second processing system, the supplied image signal is expanded N times to be parallelized N times. A second step of generating N image signals and reversing the order of the N image signals depending on whether the control signal indicates a forward direction or a reverse direction; and the first processing system. Third step of supplying N image signals output from the second processing system and N image signals output from the second processing system to the 2N image signal supply lines according to a corresponding dot order. And is provided. According to the present invention, the operating frequencies of the first and second processing systems can be reduced, and even if serial-parallel conversion is performed separately for the two systems, a predetermined screen is displayed on the screen. It is possible to correctly display a predetermined image on the dots.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

<1. First Embodiment> First, a liquid crystal display device using an image processing circuit according to the present invention will be described as a first embodiment.

FIG. 1 is a block diagram showing the overall configuration of this liquid crystal display device. As shown in this figure, the liquid crystal display device is roughly composed of an image processing unit 100A and a liquid crystal panel 200.

<1-1: Liquid Crystal Panel> Next, the structure of the liquid crystal panel 200 will be described. The liquid crystal panel 200 is
For example, the thin film transistor array substrate 1 made of a quartz substrate or hard glass is provided. A plurality of pixel portions are provided in a matrix on the thin film transistor array substrate 1, and a plurality of data lines 35 (source electrode lines) arranged in the X direction and extending in the Y direction are arranged in the pixel array. A plurality of scanning lines 31 (gate electrode lines) arranged in the Y direction and extending in the X direction are arranged.

Further, each pixel portion is provided corresponding to the intersection of each data line 35 and each scanning line 31, and is connected to the thin film transistor 30 connected to the data line 35 and the scanning line 31, and the thin film transistor 30. It is composed of a pixel electrode 11 and a storage capacitor 12. Here, the data lines 35 are adjacent to each other.
A data line group is formed every four lines. As will be described later, the image signal is set in units of data line groups, and
5 are supplied at the same time.

Further, the thin film transistor 30 has the data line 3
5 is connected between the pixel electrode 11 and the pixel electrode 11, and the image signal supplied to the data line 35 is applied to the pixel electrode 11 and the storage capacitor 12 during a conductive period. At this time, the conductive state or the non-conductive state of the thin film transistor 30 is controlled according to the scanning signal supplied via the scanning line 31 to which the gate electrode is connected.

Further, on the thin film transistor array substrate 1, a capacitance line 31 ′ (storage capacitance electrode) which is a wiring for the storage capacitance 12 for holding the voltage applied to the pixel electrode 11 for a long time is connected to the scanning line 31. The storage capacitors 12 formed in parallel are formed between the pixel electrodes 11 and the capacitance lines 31 '.

In addition, on the thin film transistor array substrate 1, a plurality of data lines 35 are formed by sampling an image signal.
The sampling circuit 210, the data line driving circuit 220, and the scanning line driving circuit 230, which are respectively supplied to the above, are formed by using P-channel thin film transistors and N-channel thin film transistors as circuit elements.

Next, the sampling circuit 210 supplies 24 image signals V1 to V24 converted into parallel format by a serial-parallel conversion circuit described later to each data line 35 at a predetermined timing in synchronization with the scanning signal. In order to do so, it is a circuit that samples the image signals V1 to V24. The sampling circuit 210 includes a sampling thin film transistor 211 that constitutes an analog switch.
Is provided for each data line 35. Image signal supply lines L1 to L24 are provided on the source electrodes of the thin film transistors 211.
The respective image signals V1 to V24 are input via the, the sampling signal line 216 is connected to the gate electrode, and the data line 35 is connected to the drain electrode.

Next, the data line drive circuit 220 has a so-called bidirectional shift register. The shift register generates sampling signals S1, S2, ... Sn having a predetermined pulse width and a predetermined timing on the basis of a power supply voltage, an X shift clock or an X shift start pulse included in a clock signal, and a control signal, and outputs the sampling signals S1, S2 ,. The signals are sequentially output to the sampling signal line 216 of the sampling circuit 210. Further, the bidirectional shift register can reverse the transfer direction according to the transfer direction control signal C included in the control signal. Therefore, the data line drive circuit 220 fixes the transfer direction to the forward direction or the reverse direction, so that the sampling signals S1, S from the sampling signal line 216 at the left end to the sampling signal line 216 at the right end are sampled.
, ... Sn can be sequentially supplied, or the sampling signals S1, S2, ... Sn can be sequentially supplied from the sampling signal line 216 at the right end to the sampling signal line 216 at the left end.

Next, the scanning line drive circuit 230 has a bidirectional shift register like the data line drive circuit 220, and has a power supply voltage, a Y shift clock and a Y shift start pulse included in the clock signal, and control. The bidirectional shift register is configured to generate a scanning signal having a predetermined pulse width and a predetermined timing based on the signal, and apply the scanning signal to the scanning line 31 line-sequentially.

In this case, the shift register receives the Y shift start pulse supplied in each vertical scanning period to start shifting, and shifts in synchronization with the Y shift clock supplied in each horizontal scanning period. , The scan signal is sequentially generated for each horizontal scanning period according to the shift.

As a result, in each pixel portion, the thin film transistor 30 whose gate electrode is connected to the scanning line 31 to which the scanning signal is applied becomes conductive, and the thin film transistor whose gate electrode is connected to the scanning line 31 to which the scanning signal is not applied. 30 becomes out of control.

Here, the scanning line driving circuit 230 fixes the transfer direction of the bidirectional shift register to the forward direction or the reverse direction in accordance with the transfer direction control signal C included in the control signal, so that the plurality of scanning lines 31 are connected. On the other hand, it is possible to sequentially supply the scanning signals in the order from top to bottom and the scanning signals in the order from bottom to top.

In such a configuration, the sampling signals S1, S2, ... Sn from the data line driving circuit 220 are sent to the sampling circuit 210 via the sampling signal line 216.
To the image signal V
1 to V24 are sampled at the same time, and the image signal V1 is applied to 24 adjacent data lines 35 forming each data line group.
~ V24 are applied simultaneously. This is the sampling signal S
1, S2, ... Sn are sequentially performed, and the sampling of the image signals V1 to V24 is sequentially performed for each data line group within the horizontal scanning period.

That is, the data line driving circuit 220 and the sampling circuit 210 simultaneously supply the image signals V1 to V24, which are phase-developed into 24 parallel signals and are input, to the data line 35.

<1-2: Image Processing Unit> Next, the image processing unit 100A will be described. FIG. 2 shows the image processing unit 100.
It is a block diagram which shows the structure of A. As shown in the figure, the image processor includes a distributor 101, first and second switches 1
02, 103, first and second serial-parallel conversion circuits 104, 105, 24 D / A converters 106,
And 24 amplifiers 107.
Note that in the signal names shown in FIG. 2, the code enclosed in [] is a case where the transfer direction control signal C is “1” indicating the forward direction, and the code not enclosed in []. Indicates that the transfer direction control signal C is "0" indicating the reverse direction.

<1-2-1: Distributor, First and Second Switches> First, the distributor 101 synchronizes the input image data D with the first image data DO corresponding to odd dots in synchronization with the divided clock. And second image data DE corresponding to even dots
It is configured to distribute to. Here, the divided clock has a cycle twice as long as the sampling cycle of the input image data D, and is generated by dividing the sampling clock of the input image data D by 1/2.

The distributor 101 has, for example, a first latch circuit which latches the input image data D at the rising edge of the divided clock and outputs the first image data DO, and a falling edge of the divided clock. Latch the input image data D
And a second latch circuit for outputting the image data DE (not shown). Since the distributor 101 distributes the input image data D into two, it is possible to operate the constituent parts in the subsequent stage at 1/2 of the sampling frequency (video transfer frequency).

Next, the first and second switches 102,
The first and second image data DO and DE are supplied to 103, which are selected and output based on the transfer direction control signal C. Here, if the transfer direction control signal C indicates the forward direction (C = 0 in this example), the first switch 102 selects the first image data DO and sets it to the first serial-parallel conversion circuit 104. To the second, while the second
The switch 103 selects the second image data DE and outputs it to the second serial-parallel conversion circuit 105.
Conversely, if the transfer direction control signal C indicates the reverse direction (C = 1 in this example), the first switch 102 causes the second switch
The image data DE is selected and output to the first serial-parallel conversion circuit 104, while the second switch 103 is selected.
Selects the first image data DO and outputs it to the second serial-parallel conversion circuit 105.

<1-2-2: First and Second Serial-Parallel Conversion Circuits> The first serial-parallel conversion circuit 104 is different from the input terminal in that it is connected to the first switch 102. A second serial-parallel conversion circuit 105 whose input terminal is connected to the second switch 103,
Since the configurations are the same, the first serial-parallel conversion circuit 104 will be described here.

First serial-parallel conversion circuit 104
Has one input terminal and twelve output terminals OUT1 to OUT12, and serially input the first or second image data DO, DE by 12 times the time and aligning the phases. Convert to 12 parallel data. If the transfer direction control signal C indicates the forward direction, the output terminals OUT1 and OUT
2, ... OUT12, while when the transfer direction control signal C indicates the reverse direction, the data input later is sequentially output to the output terminals OUT1, OUT2 ,.

Here, the operation of the first serial-parallel conversion circuit 104 will be described with reference to FIGS. Figure 3
4 is a timing chart of the first serial-parallel conversion circuit when the transfer direction control signal C indicates a forward direction, and FIG. 4 is a first serial-parallel conversion circuit when the transfer direction control signal C indicates a reverse direction. It is a timing chart of a parallel conversion circuit.

Input image data D is sampled in the order of D
When represented as 1, D2, ..., The first image data DO corresponding to the odd dots becomes D1, D3, D5, ... And the second image data DE corresponding to the even dots is D2, D4, D6 ,.
Becomes Here, when the transfer direction control signal C indicates the forward direction (see FIG. 3), the first image data DO is supplied to the input terminal, so the first serial-parallel conversion circuit 104 is By sequentially latching one image data D1, D3, D5 ..., Internal data iD1 to iD12 whose time axis is expanded by 12 times are internally generated. After that, the first serial-parallel conversion circuit 104 further latches the internal data iD1 to iD12 to output data in phase from the output terminals OUT1 to OUT12.

In this case, during the period T1, the output terminal OU
D1, D3, ... D23 are simultaneously output from T1 to OUT12,
In the period T2, the output terminals OUT1 to OUT12 to D25, D
27, ... D47 are output at the same time, and even in the periods T3, T4, ..., 12 pieces of data converted in parallel are output as in the periods T1, T2. Here, j = 1, 2, ... 1
When 2, k = 0, 1, ..., DOj is DOj = Dn (n
Is a subscript of the input image data D), and n = 2j-1 + 24k is defined, the data output from the output terminals OUT1, OUT2, ... OUT12 is DO1, DO2, ... D as shown in FIGS.
It becomes O12.

On the other hand, when the transfer direction control signal C indicates the reverse direction, the second image data DE is supplied to the input terminal, and therefore the first serial-parallel conversion circuit 104.
Is the second image data D2, D4, D6 as shown in FIG.
Internal data iD1 to iD obtained by expanding the time axis of ... by 12 times
12 and finally the internal data iD1 to iD12
Output from the output terminals OUT1 to OUT12 with the same phase. However, when the transfer direction control signal C indicates the forward direction,
Internal data iD1, iD from output terminals OUT1, OUT2, ... OUT12
2, ... Corresponding data of iD12 is output, whereas when the transfer direction control signal C indicates the reverse direction,
Data corresponding to the internal data iD12, iD11, ... iD1 are output.

That is, in this case, the output terminals OUT1 to OUT12 output D24, D22, ... D2 at the same time in the period T1, and the output terminals OUT1 to OUT12 in the period T2.
From D48, D46, ... D26 are output at the same time,
Even in the periods T3, T4 ..., Twelve pieces of data converted in parallel are output as in the periods T1, T2. If DEj is defined as DEj = Dm (m is a subscript of the input image data D) and m = 2j + 24k (j = 1,2, ... 12, k = 0,1, ...), output terminals OUT1, OUT2 The data output from OUT12 is DE12, DE11, ... As shown in FIGS.
It becomes DE1.

The second serial-parallel conversion circuit 105 is configured similarly to the first serial-parallel conversion circuit 104 as described above, and the input data is the same as the first serial-parallel conversion circuit 105. Only they are different. Therefore, as shown in FIG. 2, when the transfer direction control signal C indicates the forward direction, its output terminal OUT
When DE1, DE2, ... DE12 are output from 1, OUT2, ... OUT12 and the transfer direction control signal C indicates the reverse direction, D
O12, DO11, ... DO1 are output.

<1-2-3: D / A Converter and Amplifier> Next, as shown in FIG. 2, each D / A converter 106A to 106L, 1.
06M to 106X are connected to the output terminals OUT1 to OUT12 of the first and second serial-parallel conversion circuits 104 and 105, respectively, and convert a digital signal into an analog signal.
Further, the amplifiers 107A to 107X are provided in the subsequent stages of the D / A converters 106A to 106X, respectively amplifying the image signals obtained via the D / A converters 106A to 106X to a predetermined level,
The liquid crystal panel 20 described above is used as the image signals V1 to V24.
Output to 0.

In this embodiment, since the distributor 101 divides the input image data D into two, the first and second serial-parallel conversion circuits 104 and 105 generate the first image data DO corresponding to odd-numbered dots. The second image data DE corresponding to the even dots are serial-parallel converted. Therefore, when the transfer direction control signal C indicates the forward direction, the output signals of the amplifiers 107A to 107L correspond to odd dots, while the amplifier 10
Output signals from 7M to 107X correspond to even dots. Therefore, when supplying the output signals of the amplifiers 107A to 107X to the image signal supply lines L1 to L24, it is necessary to consider the order of the odd dots and the even dots. So 107A →
The processing results obtained by the two processing systems such as L1, 107M → L2, 107B → L3, 107N → L4 ... Are alternately supplied to the image signal supply lines L1 to L24.

An amplifier corresponding to DO1 to DO12
Output signals from 107A to 106X to AO1 to AO12 and DE1 to D
The output signal of the amplifier 107A-106X corresponding to E12 is AE1.
If the transfer direction control signal C is in the forward direction, V1, V3, ...
O1, AO2, ... AO12, and V2, V4, ... V24 become AE1, AE2, ... AE12, respectively. On the other hand, when the transfer direction control signal C is in the reverse direction, V1, V3, ... V
23 are AE12, AE11, ... AE1, respectively, V2,
V4, ... V24 become AO12, AO11, ... AO1, respectively.

<1-3: Overall Operation of Liquid Crystal Display Device> Next, the overall operation of the liquid crystal display device will be described with reference to the drawings. FIG. 5 is a conceptual diagram showing the operation of the liquid crystal display device when the transfer direction control signal C indicates the forward direction, and FIG. 6 is the operation of the liquid crystal display device when the transfer direction control signal C indicates the reverse direction. It is a conceptual diagram which shows. In addition, the liquid crystal panel 200 of this example is assumed to have a pixel portion of 1272 dots in the X direction, and in FIGS. 5 and 6, the pixel portions forming the first scanning line are shown with reference symbols P1 to P1272. It shall be. Further, the symbols D1, D2, ... D1272 of each data forming the input image data D will be conveniently used for the signals after serial-parallel conversion respectively corresponding thereto.

First, consider the case where the transfer direction control signal C indicates the forward direction (see FIGS. 2 and 5). Input image data D
Is supplied to the image processing unit 100A, the input image data D is sorted into the first image data DO and the second image data DE by the distributor 101 and the first and second switches 102 and 103. After that, the first and second image data DO and DE are supplied to the first and second serial-parallel conversion circuits 104 and 105, respectively. As a result, the first and second serial-parallel conversion circuits 1
The operating frequencies of 04 and 105 can be reduced to 1/2 as compared with the case where the input image data D is directly serial-parallel converted.

After that, the first and second serial-parallel conversion circuits 104 and 105 convert the first and second image data DO and DE into 12-system parallel data, respectively. As a result, parallel data in which one sample period of the input image data D is expanded 24 times in time is obtained. For example, in the period T1, the first serial-parallel conversion circuit 104 has the parallelized D1, D2,
... D23 is output, and the second serial-parallel conversion circuit 105 outputs parallelized D2, D4, ... D24.

Next, each parallelized data is D / A converted and amplified to a predetermined level. After that, the respective image signals generated by the two processing systems are respectively supplied to the corresponding image signal supply lines L1 to L24. For example, D1, D2, ... D23 and D2, D4 ,.
D24 is D1 → L1, D2 → L2, ... D24 → L24
And so on. That is, the processing results of the two processing systems are combined at the stage of supplying each image signal to the image signal supply lines L1 to L24.

Next, the image signals supplied to the image signal supply lines L1 to L24 are sampled by the sampling circuit 210. The sampling in this case is performed for every 24 adjacent data line groups. Further, in this example, since the transfer direction control signal C indicates the forward direction, the sampling signals are sequentially supplied from the sampling signal line at the left end to the sampling signal line at the right end. Therefore, the phases of the sampling signals S1, S2, ... S53 are S1 →
S2 → ... proceeds to S53. Therefore, the period T1
In this case, image signals (D1 to D2) are supplied to the pixel units P1 to P24.
4) is supplied, and in the period T2, the pixel portions P25 to P25
An image signal (D24 to D48) is supplied to 48, and this is repeated thereafter, and in the period T53, the pixel portion P1248.
The image signals (D1248 to D1272) are supplied to P1272.

Therefore, the scanning direction of each of the pixel portions P1 to P1272 is the forward direction indicated by the arrow X in the figure.

Next, consider the case where the transfer direction control signal C indicates the reverse direction (see FIGS. 2 and 6). In this case, contrary to the case of the forward direction, the second image data DE is supplied to the first serial-parallel conversion circuit 104,
The first image data DO is supplied to the second serial-parallel conversion circuit 105. After that, the first and second serial-parallel conversion circuits 104 and 105 convert the second and first image data DE and DO into 12-system parallel data, respectively. At this time, each conversion circuit reverses the order of the data output from those output terminals OUT1 to OUT12 as compared with the case of the forward direction. As a result, the image signal supply line L
The order of the image signals supplied to 1 to L24 can be reversed from that in the forward direction.

That is, in the case of the forward direction, L1 is D1,
L2 is D2, ... L24 is D24, and in the opposite direction, L1 is D2.
4, image signals are supplied to L2, D23, ... L24, and so on. Here, each image signal supply line L1 to L2
4 is sequentially supplied to each data line group via the sampling circuit 210. As described above, the image signal supply lines L1 to L24 are forward and backward.
Since the image signals supplied to the image signals are inverted, it is possible to invert the order of the image signals supplied to the respective pixel portions connected to a certain data line group according to the transfer direction.

Next, in this example, since the transfer direction control signal C indicates the reverse direction, the data line drive circuit 220 outputs the sampling signals S1 to S53 from the sampling signal line 216 at the right end to the sampling signal line 216 at the left end. Supply in sequence. Therefore, the sampling signals S1, S2, ... S
The phase of 53 advances in the order of S53 → S52 → ... S1. Therefore, in the period T1, the image signals (D1 to D24) are supplied to the pixel units P1272 to P1249 that form the 53rd data line group, and in the period T2, the image signals (D1 to P1225) to the pixel units P1248 to P1225. D25 ~ D4
8) is supplied, and this is repeated thereafter, and the image signals (D1249 to D1D to D1249 to D1) are supplied to the pixel units P24 to P1 in the period T53.
1272) is supplied.

Therefore, the scanning direction of each of the pixel portions P1 to P1272 is the opposite direction as indicated by the arrow Y in the figure.

<1-4: Effect of First Embodiment> As described above, according to the present embodiment, the distributor 110 distributes the input image data D to the first image data DO corresponding to the odd dots and the even image data DO. Since the 22nd image data DE corresponding to the dot is separated and serial-parallel conversion is performed for each, the operating frequency of the first and second serial-parallel conversion circuits 104, 105 is halved. Can be lowered.

Further, the respective data parallelized by the two processing systems such as the first and second serial-parallel conversion circuits 104 and 105 are passed through D / A converters 106A to 106X and amplifiers 107A to 107X. Image signal supply lines L1 to L
According to the present embodiment, the image signals are combined when being supplied to 24, but the type of the first image data DO and the second image data DE supplied to the two processing systems, that is, odd-numbered dots. Since the images are combined in consideration of the order of even dots, even if two processing systems are used, the image signals can be displayed in the correct order.

When the transfer direction is the reverse direction, the image signals of even dots are supplied to the odd-numbered pixel portions and the image signals of odd-dot dots are supplied to the even-numbered pixel portions, contrary to the case of the forward direction. First switch 10 and second switch 10
2103 switches the processing system that outputs the first or second image data DO, DE based on the transfer direction control signal C, so that such control is possible. Further, when the transfer direction is the reverse direction, the first and second serial-parallel conversion circuits 104 and 105 output the respective parallelized data from the respective output terminals OUT1 to OUT12, but the transfer direction control signal Since the data output order is switched based on C, the order of the image signals supplied to the data lines forming each data line group can be reversed according to the transfer direction. In addition, since the data line drive circuit switches the supply order of the sampling signals based on the transfer direction control signal C, in the case of the forward direction, the image signals are supplied to the pixel portion in ascending order from the first data line group, In the reverse direction, image signals can be supplied to the pixel portion in descending order from the 53rd data line group. As a result, even if two processing systems are used to reduce the operating frequency of serial-parallel conversion, the direction of image display can be reversed.

<2. Second Embodiment> Next, a liquid crystal display device according to a second embodiment will be described. This liquid crystal display device
Instead of the image processing unit 100A described above, the image processing unit 10
The liquid crystal display device has the same configuration as that of the liquid crystal display device of the first embodiment except that 0B is used.

<2-1: Configuration of Image Processing Unit 100B> FIG. 7 is a block diagram showing the configuration of the image processing unit 100B. In the signal names shown in FIG. 7, the code enclosed in [] is the case where the transfer direction control signal C is “1” indicating the forward direction, and the code not enclosed in []. Is
This is the case where the transfer direction control signal C is "0" indicating the reverse direction.

The image processing unit 100B differs from the image processing unit 100A shown in FIG. 2 in that the sample-hold circuits 108A to 108X are used instead of the first and second serial-parallel conversion circuits 104 and 105. Parallel conversion is performed, a D / A converter 106a and an amplifier 107a are provided after the first switch 102, and a D / A converter 106b and an amplifier 107 are provided after the second switch 103.
b is provided and a trigger pulse generation circuit TPG is provided. That is, the image processing unit 1 of the first embodiment
00A performs serial-parallel conversion by digital processing, whereas the image processing unit 100B of the second embodiment.
Is configured to perform serial-parallel conversion by analog processing.

More specifically, the output terminal of the amplifier 107a is connected to each input terminal of the sample hold circuits 108A to 108L, and the output terminal of the amplifier 107b is connected to each input terminal of the sample hold circuits 108M to 108X. Has been done. The output signal of the amplifier 107a is the first signal as shown in the figure.
When the transfer direction control signal C indicates the forward direction, the transfer direction control signal C corresponds to the odd-numbered dot image signal whose time axis is doubled and is transferred in the transfer direction. When the control signal C indicates the reverse direction, it corresponds to an image signal of even dots whose time axis is doubled. On the other hand, the output signal of the amplifier 107b corresponds to the image signal of even dots when the transfer direction control signal indicates the forward direction, and the image of the odd dot when the transfer direction control signal indicates the reverse direction. It corresponds to the signal. In the following description, the output signal of the amplifier 107a will be referred to as a first amplifier output signal AS, and the output signal of the amplifier 107b will be referred to as a second amplifier output signal BS.

Next, the trigger pulse generating circuit TPG is set to 1
Two-phase sampling pulses SP1, SP2, ... SP12 and a latch pulse LP are generated. Sampling pulse SP
1 to SP12 are respectively supplied to the sample hold circuits 108A to 108L and 108M to 108X based on the transfer direction control signal C,
Also, the latch pulse LP is used for all sample and hold circuits.
It is designed to be supplied to 108A-108X.

Here, the sampling pulses SP1 and SP
The pulse phases of 2, ... SP12 and the latch pulse LP proceed in the order of SP1 → SP2 → ... SP12 → LP. When the transfer direction control signal C indicates the forward direction, SP1 is 108A and 108M, and SP2 is 108B and 108M.
When SP12 is supplied to 108L and 108X, and the transfer direction control signal C indicates the reverse direction, SP1 is changed to 108L and 108X, SP2 is changed to 108K and 108W,
... SP12 is supplied to 108A and 108M. The sampling pulses SP1 to SP12 and the latch pulse LP are synchronized with the input image data D, and their frequencies are set to 1/24 of the sampling frequency of the input image data D.

Next, the sample hold circuits 108A to 108L, 1
08M to 108X are configured to internally perform two-step sample hold, and include a buffer amplifier, an analog switch, a hold capacitor, and the like. First, in the first stage, the first and second amplifier output signals AS and BS are supplied to the sampling pulses SP1 and SP, respectively.
2, ... Holds samples based on SP12. As a result, the first and second amplifier output signals AS, BS
The time axis of is extended 24 times. However, since the phases of the sampling pulses SP1 to SP12 are different, the phase of the time-expanded image signal is not uniform at the time when the first step is completed. Next, in the second stage, the sampled and held image signal is sampled and held again by the latch pulse LP. As described above, since the latch pulse LP is common to the sample and hold circuits 108A to 108X, the phases of the output signals can be aligned.

Further, the sample hold circuits 108A, 108B, ...
Output signals of 108L are image signal supply lines L1, L3, ... L23 of the liquid crystal panel 200 as image signals V1, V3 ,.
To the sample and hold circuits 108M, 108N, ... 10
The 8X output signal is supplied to the image signal supply lines L2, L4, ... L24 of the liquid crystal panel 200 as image signals V2, V4 ,.

<2-2: Operation of Image Processing Unit 100B> Next, the serial-parallel conversion operation of the image processing unit 100B will be described with reference to FIGS. Note that the sample-hold circuits 108A to 108L and 108M to 108X differ only in whether the input signal is the first amplifier output signal AS or the second amplifier output signal BS.
The description of 8M to 108X is omitted, and the sample and hold circuits 108A to 10
The 8L will be described. FIG. 8 shows a sample hold circuit 108A to 108A when the transfer direction control signal C indicates the forward direction.
FIG. 9 is a timing chart of 108L, and FIG. 9 is a timing chart of the sample hold circuits 108A to 108L when the transfer direction control signal C indicates the reverse direction.

First, when the transfer direction control signal C indicates the forward direction (see FIG. 8), the image signal corresponding to the first image data DO is output from the amplifier 107a as the first amplifier output signal AS. It Here, the input image data D
When the amplifier output signals corresponding to the respective data D1, D2, ... Constituting the above are represented as A1, A2, .., the first amplifier output signal AS becomes A1, A3 ,. .

Sample hold circuits 108A, 108B, ... 108L
Internally samples the first amplifier output signal AS by sampling pulses SP1, SP2, ... SP12 shown in the figure. Sample hold circuit 108A, 108B, ... 108L
Letting SH1, SH2, ... SH12 represent the image signals obtained by the sample hold in the first stage in, the image signals are as shown in the figure. That is, the time axis is extended 12 times and the image signals SH1, SH2, ... SH12 are out of phase by the first-stage sample hold. After this, the sample hold circuits 108A, 108B, ... 108L
Are image signals SH1 and SH by the latch pulse LP shown in the figure.
.., SH12 are sampled and held, so that image signals V1, V3, ... V23 whose phases are aligned are obtained. Here, when j = 1, 2, ... 12, and k = 0, 1 ,.
j is AOj = Dn (n is a subscript of the input image data D), n =
If defined as 2j-1 + 24k, the image signals V1, V3, ...
V23 is AO1, AO2, ... AO as shown in FIGS.
Twelve.

Next, when the transfer direction control signal C indicates the reverse direction (see FIG. 9), the image signal corresponding to the second image data DE is output from the amplifier 107a as the first amplifier output signal AS. To be done. Therefore, the first amplifier output signal AS becomes A2, A4, ... As shown in the figure. When the transfer direction control signal C indicates the reverse direction, the sampling signals SP12, SP11, ... SP1 are supplied to the sample hold circuits 108A, 108B ,. , As shown in the figure. That is, when the transfer direction control signal C indicates the forward direction, the image signal SH1 is A1, A25 ... And the image signal SH2 is A3, A2.
4, the image signal SH1 is A24, A48 ..., and the image signal SH2 is A.
22, A26 ...

Therefore, in the case of the reverse direction, the image signal SH1,
When SH2, ... SH12 are sampled and held again by the latch pulse LP, image signals V1, V3 ,.
Will be obtained. Where AEj is AEj = Dm
(M is a subscript of the input image data D), m = 2j + 24k
If defined as (j = 1,2, ... 12, k = 0,1, ...), output terminals OUT1,
The data output from OUT2, ... OUT12 is the image signal V1,
V3, ... V23 are AE12, AE as shown in FIGS.
11, ... becomes AE1.

In addition, the sample hold circuits 108M-10
8X has the same configuration as 108A to 108L, except that the input signal is the second amplifier output signal BS, and therefore FIG.
When the transfer direction control signal C indicates the forward direction, the image signals V2, V4, ...
When AE2, ... AE12 is output and the transfer direction control signal C indicates the reverse direction, AO12, AO11, ... AO1
Is output.

From the above, the image signals V1 to V24 generated by the image processing unit 100B of the second embodiment are the first
Image signal V generated by the image processing unit 100A of the embodiment
1 to V24. The liquid crystal panel 200 used in the liquid crystal display device of the second embodiment has the same configuration as that of the first embodiment. Therefore, the liquid crystal display device of the second embodiment can reverse the direction of image display as in the first embodiment. The overall operation of this liquid crystal display device is shown in FIGS. 5 and 6 used for explaining the overall operation of the first embodiment. In FIG. 5 and FIG. 6, the outputs of the first and second serial-parallel conversion circuits are sample and hold circuits.
Corresponding to the outputs of 108A to 108L and 108M to 108X, it is the same as the overall operation of the first embodiment, and therefore detailed description thereof is omitted here.

<2-3: Effect of Second Embodiment> According to the present embodiment, the serial-parallel conversion is performed by dividing into two processing systems as in the first embodiment.
D / A converters 106a and 106b, amplifiers 107a and 10
7b and the operating frequencies of the sample and hold circuits 108A to 108X can be reduced to 1/2. Further, the image signals parallelized by the two processing systems are combined when they are supplied from the sample hold circuits 108A to 108X to the image signal supply lines L1 to L24.
.. 108X and the image signal supply lines L1 to L24 are connected in consideration of the order of odd dots and even dots, the image signals can be displayed in the correct order even if two processing systems are used. Even if two processing systems are used to reduce the operating frequency of serial-parallel conversion, the direction of image display can be reversed.

Further, in this example, since the serial-parallel conversion is performed by using the sample hold circuits 108A to 108X, the number of D / A converters is greatly increased as compared with the first embodiment. Can be reduced.

<3. Third Embodiment> Next, a liquid crystal display device according to a third embodiment will be described. In the first embodiment described above, the serial-parallel conversion is processed digitally, and in the second embodiment, it is processed analogically. On the other hand, in the third embodiment, serial-parallel conversion is performed by using both digital processing and analog processing. The liquid crystal display device according to the third embodiment is configured similarly to the liquid crystal display device of the first embodiment, except that the image processing unit 100C is used instead of the image processing unit 100A described above.

<3-1: Configuration of Image Processing Unit 100C> FIG. 10 is a block diagram showing the configuration of the image processing unit 100C. In the signal names shown in FIG. 10, the code enclosed in [] is a case where the transfer direction control signal C is “1” indicating the reverse direction, and the code not enclosed in []. Is "0" indicating that the transfer direction control signal C indicates the forward direction.
Is the case.

In the image processing unit 100C, the third and fourth serial-parallel conversion circuits 104 'and 105' are provided.
Has one input terminal and two output terminals OUT1 and OUT2, and the first or second image data DO and DE that are serially input are doubled in time and aligned in phase. Convert to two parallel data. Therefore, the circuit in the subsequent stage can be operated at 1/4 of the sampling frequency of the input image data D. Also, the third and fourth serial-parallel conversion circuits 104 'and 105'.
When the transfer direction control signal C indicates the forward direction,
The data input first is output from the output terminal OUT1, and the data input later is output from the output terminal OUT2.
On the other hand, when the transfer direction control signal C indicates the reverse direction, the data input later is output from the output terminal OUT2 and the data input earlier is output from the output terminal OUT1.

Next, in the subsequent stage of the third serial-parallel conversion circuit 104 ', there are two systems of D / A converters 106a, 1a.
06b and amplifiers 107a and 107b are provided, and two systems of D / A converters 106c and 106d and amplifiers 107c and 107d are also provided at the subsequent stage of the fourth serial-parallel conversion circuit 105 '. By these, the parallelized data is converted from a digital signal to an analog signal, and the image signal is amplified to a predetermined level.

Next, the sample and hold circuits 108A to 108F, 108G to 108L, 108M to 108R, 108S for performing serial-parallel conversion in 6 systems are respectively provided in the subsequent stages of the amplifiers 107a to 107d.
~ 108X is provided. These sample hold circuits 108A to 108X have the same configuration as that of the second embodiment.

The trigger pulse generation circuit TPG 'is
It is configured to generate 6-phase sampling pulses SP1 'to SP6' and a latch pulse LP '. Based on the transfer direction control signal C, the sampling pulses SP1 ′ to SP6 ′ are sample hold circuits 108A to 108F, 108G to 108L,
108M to 108R, 108S to 108X, and the latch pulse LP 'is supplied to all sample and hold circuits 108A to 108X.
To be supplied to.

Here, the sampling pulses SP1 'to S
The P6 'and the latch pulse LP' are synchronized with the input image data D, and their frequencies are set to 1/24 of the sampling frequency of the input image data D. The pulse phases of the sampling pulses SP1 ′, SP2 ′, ... SP6 ′ and the latch pulse LP ′ are SP1 ′ → SP2 ′ →
... SP6 '->LP'. Also,
If the transfer direction control signal C indicates the forward direction, SP
1'for 108A, 108G, 108M, 108L, SP2 'for 108B, 108H, 108
When SP6 'is supplied to 108F, 108L, 108R, 108X to N, 108T and the transfer direction control signal C indicates the reverse direction,
Contrary to the case of forward direction, SP1 'is 108F, 108L, 108R, 108X
And SP2 'is 108E, 108K, 108Q, 108W, ... SP6' is 108
It is designed to be supplied to A, 108G, 108M, 108L.

Furthermore, each sample hold circuit 108A-10A
Since the image signal supplied to 8X has the time axis doubled as compared with that of the second embodiment, the pulse widths of the sampling pulses SP1 ′ to SP6 ′ and the latch pulse LP ′ are the sampling pulses. The pulse widths of SP1 to SP12 and the latch pulse LP are set to double the pulse width.

By the way, generally, in the sample hold circuit, it is necessary to charge the hold capacitor with a switching element or to cut off the input from the hold capacitor. In order to guarantee these performances, the shorter the sampling period, the higher the operating speed of the switching element, which complicates the configuration. In this example, since the pulse width can be increased, the sample hold circuit
108A to 108X can be easily configured. In other words, two systems are parallelized in the third and fourth serial-parallel conversion circuits 104 'and 105' in order to supplement the performance of analog processing.

With the above configuration, the image processing unit 100C
Then, serial-parallel conversion consisting of three steps is performed. First, in the first stage, the distributor 101 converts the input image data D into two-system image data DO, DE in parallel, and in the second stage, the third and fourth serial-parallel conversion circuits 104 ', 105'. Image data DO, DE
Are parallel-converted into two systems for each circuit, and in the third stage, the image signals of the four systems obtained in the second stage are converted into sample hold circuits 108A to 108F, 108G to 108L, 108M to 108.
24 system image signals V1 to V24 by R, 108S to 108X
Has been converted to.

<3-2: Operation of Image Processing Unit 100C> Next, the serial-parallel conversion operation of the image processing unit 100C will be described with reference to FIGS. The third serial-parallel conversion circuit 104 ′ and the D / A converter 106
a, 106b, amplifiers 107a, 107b and sample hold circuits 108A to 108L, a fourth serial-parallel conversion circuit 105 ', D / A converters 106c, 106d, amplifiers 107c, 107d and sample hold circuit 108.
Since M to 108X have the same configuration, here,
Only the former will be explained.

FIG. 11 is a timing chart showing the operation of serial-parallel conversion when the transfer direction control signal C indicates the forward direction, and FIG. 12 is a serial chart when the transfer direction control signal C indicates the reverse direction. 6 is a timing chart showing the operation of parallel conversion.

First, when the transfer direction control signal C indicates the forward direction (see FIG. 11), the distributor 101 parallel-converts the input image data D into the two-system image data DO, DE, and The image data DO is further serial-parallel converted into two systems by the third serial-parallel conversion circuit 104 '. As a result, as shown in the figure, from the output terminal OUT1 of the conversion circuit 104 ', D1, D5,
Data such as ... is output, while the conversion circuit 104 'is output.
The data such as D3, D7, ... Is output from the output terminal OUT2 of.

Here, the amplifier output signals corresponding to the respective data D1, D2, ... Which compose the input image data D are A1, A
2, the output signal of the amplifier 107a becomes A1, A5, ... As shown in FIG.
The output signal of b is A3, A7, ....

Sample and hold circuits 108A to 108F, 108G to 1
08L internally samples and holds the output signals of the amplifiers 107a and 107b by sampling pulses SP1 ', SP2', ... SP6 'shown in the figure, and further simultaneously samples and holds the internal sample and hold result by a latch pulse LP'. 1 was parallelized by
Two-system image signals V1, V3, ... V23 are obtained. Here, when j = 1, 2, ... 12, and k = 0, 1 ,.
j is AOj = Dn (n is a subscript of the input image data D), n =
If defined as 2j-1 + 24k, the image signals V1, V3, ...
V23 is AO1, AO2, ... As shown in FIGS.
It becomes AO12.

Next, when the transfer direction control signal C indicates the reverse direction (see FIG. 12), the twelfth image data DE
Is further serial-parallel converted into two systems by the third serial-parallel conversion circuit 104 '. As a result, as shown in the figure, data such as D4, D8, ... Is output from the output terminal OUT1 of the conversion circuit 104 ', while
From the output terminal OUT2 of the conversion circuit 104 ', D2, D6, ...
Data is output.

Next, when the transfer direction control signal C indicates the reverse direction, each sample hold circuit 108A, 108B, ... 10
8F and 108G, 108H, ... 108L for each sampling pulse SP6,
SP5, ... SP1 are supplied. That is, in the case of the forward direction, the sampling and holding circuits 108A, 108B, ... 108F and 108G, 108H ,.
In contrast to the case of supplying 8L, in the case of the reverse direction, the sampling pulses are supplied in the order of slower pulse phase. Therefore, the image signals V1, V3, ... V23 shown in the figure are obtained. Here, AEj is AEj = Dm (m is a subscript of the input image data D), m = 2j + 24k (j = 1,2, ...
12, k = 0,1, ...), output terminals OUT1, OUT2, ... OUT
The data output from 12 is the image signals V1, V3, ... V2.
3 is AE12, AE11, ... As shown in FIGS.
It becomes AE1.

Further, the fourth serial-parallel conversion circuit 105 ', D / A converters 106c and 106d, the amplifier 10
7c, 107d and sample hold circuit 108M-108X
Is the same as that described above except that the input data is different. Therefore, as shown in FIG. 10, when the transfer direction control signal C indicates the forward direction, the image signals V2, V4,
... AE1, AE2, ... AE12 are output as V24,
When the transfer direction control signal C indicates the reverse direction, AO1
2, AO11, ... AO1 are output.

From the above, the image signals V1 to V24 generated by the image processing unit 100C of the third embodiment are the first
And the image signals V1 to V24 generated by the image processing units 100A and 100B of the second embodiment are equal. Also,
Liquid crystal panel 2 used in the liquid crystal display device of the third embodiment
00 has the same configuration as that of the first and second embodiments. Therefore, the liquid crystal display device of the third embodiment can reverse the direction of image display as in the first and second embodiments.

<3-3: Effect of Third Embodiment> According to the present embodiment, the distributor 101 divides into two processing systems to perform serial-parallel conversion, as in the first embodiment. Therefore, the operating frequencies of the third and fourth serial-parallel conversion circuits 104 'and 105' can be reduced to 1/2. Further, since the two systems are further parallelized by the third and fourth serial-parallel conversion circuits 104 'and 105', the operating frequencies of the sample hold circuits 108A to 108X are compared with those of the second embodiment. Since it can be halved, these can be easily configured. In addition, the image signals parallelized by the two processing systems are sampled and held by the sample and hold circuits 108A to 108A.
The sample-hold circuits 108A to 108X and the image signal supply lines L1 to L24 are connected in consideration of the order of odd-numbered dots and even-numbered dots, although they are combined when they are supplied from the 108X to the image signal supply lines L1 to L24. Therefore, the image signals can be displayed in the correct order even if the two processing systems are used.
Even if two processing systems are used to reduce the operating frequency of serial-parallel conversion, the direction of image display can be reversed.

<4. Application Example> Next, an example in which the liquid crystal display device described in the first to third embodiments is applied to an electronic device will be described.

<4-1: Video Projector> A video projector using the liquid crystal display device described in the first to third embodiments as a light valve will be described. FIG.
FIG. 3 is a plan view showing a configuration example of a video projector.

As shown in the figure, inside the video projector 1100, a lamp unit 1102 including a white light source such as a halogen lamp is provided. Projection light emitted from the lamp unit 1102 is reflected by a plurality of mirrors 1106, 1 arranged in a light guide 1104.
106, ... and two dichroic mirrors 110
Liquid crystal panels 1110R, 111 as light valves corresponding to each of the three primary colors of RGB by 8
It is incident on OB and 1110G. In addition, the video projector 1100 can be used in a stationary mode in which it is installed on the floor and in a ceiling suspension mode in which the upper surface and the lower surface are reversed and is hung on the ceiling. Input can be made by a mode selection switch (not shown) or an infrared remote controller (not shown) provided.

The configuration of the liquid crystal panels 1110R, 1110B and 1110G is that of the above-described liquid crystal panel 200 and includes image processing units 100A, 100B, or 1 (not shown).
Driven by R, G, and B primary color signals supplied from 00C, respectively. The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In this dichroic prism 1112, R and B lights are refracted by 90 degrees, while G
Light goes straight on. Therefore, as a result of combining the images of the respective colors, the color image is projected on the screen or the like via the projection lens 1114.

Here, since the upper and lower surfaces of the device are used in reverse in the stationary mode and the ceiling suspension mode, the liquid crystal panel 111 is used.
The relative positional relationship of 0R, 1110B, and 1110G with respect to the screen is such that the vertical and horizontal directions are reversed. Therefore, in this example, the mode input by the mode selection switch is discriminated and the transfer direction control signal C described above is generated. Specifically, the transfer direction control signal C that indicates the forward direction in the stationary mode and the reverse direction in the ceiling suspension mode is generated, and is provided for each of the liquid crystal panels 1110R, 1110B, and 1110G. It is supplied to the image processing unit 100A, 100B, or 100C. As a result, no matter which mode the video projector 1100 is used in, the vertical and horizontal positional relationship of the image displayed on the screen can be made constant.

In this example, three liquid crystal panels 111 are used.
Although 0R, 1110B, and 1110G are used, a single liquid crystal panel may display a color image. In this case, a color filter may be provided on the front surface of the liquid crystal panel.

<4-2: Video Camera> Next, an example in which the liquid crystal display device described in the first to third embodiments is applied to the display portion of a video camera will be described. 14 is an external perspective view of the video camera, and FIG. 15 is a view showing a display mode of the video camera.

In the video camera 1200 shown in FIG. 14, light incident through the lens 1210 forms an image on an image pickup device (not shown). Based on the photoelectric conversion output of this image pickup device. Thus, the input image data D described above is generated. The display unit 1220 of the video camera 1200 is composed of the liquid crystal panel 200 described above, and the video camera 1200
The image processing unit 100A, 100B, or 100
C is provided.

In this video camera 1200, the display section 1220 is normally directed to the operator side (referred to as a normal rotation state), but the display section 1220 can be rotated 180 degrees to be directed to the subject side. (It is referred to as an inverted state). If the image display of the display unit 1220 is the same in the normal rotation state and the reverse rotation direction, for example, the image shown in FIG. 15A is displayed in the normal rotation state, and in the reverse rotation state, the image is displayed in FIG. 15B. The image shown will be displayed.

For this reason, the video camera 1200 is internally provided with a detection section for detecting the display state of the display section 1220, and the transfer direction control signal C described above is generated by the detection section. There is. Specifically, the detector generates a transfer direction control signal C that indicates the forward direction in the normal state and the reverse direction in the inverted state, and generates the transfer direction control signal C, and the liquid crystal panel 200 and the image processing units 100A, 1
It is configured to supply to 00B or 100C. This allows the display unit 1220 to display the image shown in FIG. 15A even in the reverse rotation state, as in the normal rotation state.

<5. Modifications> The present invention is not limited to the above-described embodiments, and the modifications described below are possible, for example.

(1) In each of the above embodiments, the image signals V1 and V2 to be output in the serial-parallel conversion.
However, the present invention is not limited to this, and the image signals V1 to V24 may have different phases. In this case, for example, the pulse width and the timing of the sampling signal supplied to the sampling thin film transistor 211 may be appropriately adjusted and supplied for each data line group.

(2) In each of the above-described embodiments, the input image data D, which is a digital signal, has been described as an example of the input image signal. However, instead of the input image data D, an analog image input image signal is supplied. May be In this case, the distributor 101 may be composed of two systems of sample and hold circuits.

(3) In each of the above-described embodiments, an example in which two processing systems are used to serial-parallel convert one system image signal into 24 system image signals has been described. Is not limited to 2N
(N is a natural number of 2 or more) In order to supply the image signal to the image signal supply lines, first, the input image signal is distributed into two systems, and then the first processing system and the second processing system respectively perform N processing. It may be one that generates an image signal parallelized to the system.

(4) Image processing unit 1 of each embodiment described above
00A, 100B, 100C, when performing gamma correction on the image signal, the first and second switches 10
The first correction circuit and the second correction circuit may be provided in the subsequent stage of 2,103. A well-known look-up table including a ROM or the like may be used for the first and second correction circuits. In this case, the read speed of the look-up table can be halved as compared with the case where gamma correction is applied to the input image data D, so that the first and second correction circuits can be easily configured. You can

(5) In the above-described third embodiment, the third and fourth serial-parallel conversion circuits 104 ', 10 are provided.
The parallel conversion of two systems is performed by 5 ′, and the parallel conversion of six systems is further performed by the sample hold circuits 108A to 108X. However, the present invention is not limited to this, and n systems are realized by digital processing. After the parallel conversion, the analog conversion may be performed for the m systems of parallel conversion to perform the n × m systems of parallel conversion as a whole. In this case, n, m
By appropriately setting, it is possible to allocate the load of digital processing and the load of analog processing, and thus it is possible to significantly expand the degree of freedom when configuring the image processing unit 100C.

(6) In each of the above-described embodiments, the image signal is first distributed to two systems, but the present invention is not limited to this, and the input image signal is expanded in time J times and parallelized. The J-system image signals are generated respectively,
A distributor that reverses the order of the image signals of the J system according to the direction indicated by the transfer direction control signal C, and a distributor that is provided corresponding to each of the image signals of the J system, and time-expands the image signal of one system to K times. In addition, each of the parallelized K image signals is output, and J processing means for inverting the order of the K image signals in accordance with the direction indicated by the transfer direction control signal C is provided. Good. In this case, as the first step, since the J-system image signal is generated by the distributor, the operating frequencies of the J processing means can be reduced. Further, in the second stage, each processing means generates K image signals by parallelizing the image signals of 1 system by K times, and thus N (N = J × K) image signal supplies. It is possible to supply N image signals to the line at the same time. Further, since the order of the image signals output by the distributor and each processing means can be reversed according to the transfer direction, the direction of image display can be reversed.

[0120]

As described above, according to the present invention, it is possible to generate a parallel image signal at a low operating frequency even if the video transfer frequency becomes high, so that it is possible to use an element having a high operating frequency. Both can form an image processing circuit and can reverse the direction of image display.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an image processing unit 100A used in the same embodiment.

FIG. 3 is a timing chart of the first serial-parallel conversion circuit when the transfer direction control signal C indicates a forward direction in the same embodiment.

FIG. 4 is a timing chart of the second serial-parallel conversion circuit when the transfer direction control signal C indicates a reverse direction in the same embodiment.

FIG. 5 is a conceptual diagram showing an operation of the liquid crystal display device when the transfer direction control signal C indicates a forward direction in the same embodiment.

FIG. 6 is a conceptual diagram showing an operation of the liquid crystal display device when the transfer direction control signal C indicates a reverse direction in the same embodiment.

FIG. 7 is an image processing unit 1 according to a second embodiment of the present invention.
It is a block diagram which shows the structure of 00B.

FIG. 8 is a diagram showing a sample hold circuit according to the first embodiment when a transfer direction control signal C indicates a forward direction.
It is a timing chart of 8A ~ 108L.

FIG. 9 is a diagram showing a sample hold circuit according to the first embodiment when a transfer direction control signal C indicates a forward direction.
It is a timing chart of 8A ~ 108L.

FIG. 10 is a block diagram showing a configuration of an image processing unit 100C according to a third embodiment of the present invention.

FIG. 11 is a diagram showing a transfer direction control signal C in the embodiment.
5 is a timing chart showing the operation of serial-parallel conversion when the unit indicates the forward direction.

FIG. 12 is a diagram showing a transfer direction control signal C in the embodiment.
6 is a timing chart showing an operation of serial-parallel conversion in the case where the reverse direction is designated.

FIG. 13 is a plan view showing a configuration example of a video projector.

FIG. 14 is an external perspective view of a video camera.

FIG. 15 is a diagram showing a display mode of a video camera.

[Explanation of symbols]

C ... Transfer direction control signal (control signal) D ... Input image data (input image signal) 35 ... Data line 31 ... Scan lines L1 to L24 ... Image signal supply line DO ... First image data ( First image signal) DE ... Second image data (second image signal) 101 ... Distributor (distributor) 102, 103 ... First and second switches (distributor) 104 ... No. 1 serial-parallel conversion circuit (first processing unit) 105 ... Second serial-parallel conversion circuit (second processing unit) 106A to 106X ... D / A converter (D / A conversion unit) 108A 〜108X …… Sample hold circuit (sample hold unit) 211 …… Sampling thin film transistor (switching element) SP1 to SP12, SP1 ′ to SP6 ′ …… Sampling pulse TPG …… Trigger pulse generation circuit (pulse) Generation unit) 100A, 100B, 100C ... Image processing unit (image processing circuit) 200 ... Liquid crystal panel (electro-optical device)

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G09G 3/00-3/38 G02F 1/133 505-580 H04N 5/66-5/74

Claims (9)

(57) [Claims] 1. N (where N = J × K, J and K are 2 or more)
(Natural number of the image) The image display direction can be changed by supplying parallel image signals to the image signal supply lines.
In an image processing circuit used in an image display device, J-system image signals are output, each of which is parallelized while time-expanding an input image signal by J times, and the control signal indicates the forward direction and the reverse direction. Distribution means for reversing the order of the image signals of the J system, and one parallel image signal of the one system, which is provided in correspondence with the image signals of the J system, by time-expanding K times. Each of the K system image signals is output, and J processing means for reversing the order of the K system image signals when the control signal indicates a forward direction and a reverse direction. An image comprising J × K image signals output from J processing means, each of which is supplied to the N image signal supply lines in accordance with a corresponding dot order. Signal processing circuit 2. N (N is a natural number of 2 or more) image signals
By supplying a parallel image signal to the supply line ,
In an image processing circuit used in an image display device capable of changing a display direction of an image , a first image signal corresponding to an odd dot and a second image corresponding to an even dot are obtained by time-expanding an input image signal to twice. The first image signal and the second image signal, which are parallelized from the first and second output terminals, respectively, are output, and the control signal indicates a forward direction or a reverse direction. And an image supplied from the first output terminal, in which the image signal output from the first output terminal and the image signal output from the second output terminal are switched and output. While extending the signal N times, the parallelized N image signals are output from the N output terminals, and the N signals are output depending on whether the control signal indicates the forward direction or the reverse direction. Output end A first processing means for reversing the order of the image signals output from the second output terminal; and N times the image signals supplied from the second output terminal while extending the image signals supplied in parallel by N times. Second processing means for outputting the output signal from the output terminal and inverting the order of the image signals output from the N output terminals depending on whether the control signal indicates the forward direction or the reverse direction; The N image signals output from the first processing means and the N image signals output from the second processing means,
An image signal processing circuit, comprising: image signal supply means for supplying each of the 2N image signal supply lines in accordance with a corresponding dot order. 3. The first image signal and the second image signal are digital signals, and the first processing means is a system of one system supplied from the first output terminal by digital processing. The image signal is subjected to serial-parallel conversion to generate a digital image signal parallelized into N systems and output from N output terminals, and the control signal indicates a forward direction and a reverse direction. In some cases, a first serial-parallel converter that reverses the order of the digital image signals output from the N output terminals, and N D / D converters that convert N digital image signals from digital signals to analog signals. The second processing means performs serial-parallel conversion on the image signal of one system supplied from the second output terminal by digital processing to convert the image signal into N systems. A digital image that is generated from the N output terminals while the digitalized image signal is generated and output from the N output terminals, and the control signal indicates the forward direction and the reverse direction. 3. A second serial-parallel converter that reverses the order of signals, and N D / A converters that convert N digital image signals from digital signals to analog signals. The image signal processing circuit according to. 4. A pulse generator that generates N-phase sampling pulses and reverses the order of the N-phase sampling pulses depending on whether the control signal indicates a forward direction or a reverse direction. The first image signal and the second image signal are digital signals, and the first processing means converts the digital image signal supplied from the first output terminal from a digital signal to an analog signal. The D / A converter that converts the analog image signal to the N
And N sample-and-hold units that sample and hold each in accordance with a phase sampling pulse, and the second processing unit converts the image signal supplied from the second output terminal from a digital signal to an analog signal. The image signal processing circuit according to claim 2, further comprising an A / A conversion unit and N sample and hold units that sample and hold an analog image signal in accordance with the N-phase sampling pulse. 5. A case in which m (where N = n × m, n and m are natural numbers of 2 or more) phase sampling pulses are generated and the control signal indicates a forward direction and a reverse direction. And a pulse generator for reversing the order of the m-phase sampling pulses, wherein the first image signal and the second image signal are digital signals, and the first processing means performs digital processing. , 1-system image signals supplied from the first output terminal are subjected to serial-parallel conversion to generate n-system parallel digital image signals and output from the n output terminals, and the control is performed. A first serial-parallel conversion unit that reverses the order of the digital image signals output from the n output terminals when the signal indicates the forward direction and when the signal indicates the reverse direction, and n digital systems. N number of D / A converter for converting the analog signal Le image signals from the digital signal,
M sample and hold units for respectively sampling and holding an analog image signal in accordance with the m-phase sampling pulse, wherein the second processing means is one system supplied from the second output terminal by digital processing. Serial-parallel conversion is performed on the image signal to generate a digital image signal parallelized to n systems and output from the n output terminals, and the control signal indicates the forward direction and the reverse direction. A second serial-parallel converter that reverses the order of the digital image signals output from the n output terminals, and n D that converts the digital image signals of n systems from digital signals to analog signals. / A converter,
The image signal processing circuit according to claim 2, further comprising m sample and hold units that sample and hold analog image signals in accordance with the m-phase sampling pulses. 6. An electro-optical material is sandwiched between a pair of substrates, and a plurality of data lines and a plurality of scanning lines intersecting each other are provided on one substrate of the pair of substrates, wherein N (however, N
= J × K, where J and K are natural numbers of 2 or more). Each of the image signal supply lines and the plurality of data lines are connected via a switching element, and based on a control signal indicating the scanning direction of the data line. 2. An electro-optical device that changes the display direction of an image by controlling ON / OFF of the switching element by supplying an image signal parallelized for every N adjacent data lines. The image processing circuit described above and a sampling signal for controlling ON / OFF of the switching element are generated for each data line group unit composed of N adjacent data lines, and the sampling signal is sequentially supplied to each switching element Data for reversing the order of the sampling signals sequentially supplied to the respective data line groups depending on whether the control signal indicates the forward direction or the reverse direction. An electro-optical device comprising a line driving circuit. 7. An image display device for displaying an image according to an input image signal, comprising the electro-optical device according to claim 6 and a control signal generation means for generating the control signal for instructing a display direction of the image. An image display device characterized by being provided. 8. N (however, N = J × K, J and K are 2 or more)
(Natural number of the image) The image display direction can be changed by supplying parallel image signals to the image signal supply lines.
In an image signal supplying method used for an image display device, an input image signal is time-expanded J times and parallelized to generate an image signal of J system, and a reverse direction to a case where the control signal indicates a forward direction is generated. A first step of reversing the order of the J image signals to be distributed to the J processing systems in the case of instructing, and in each of the processing systems, the supplied image signals are time-expanded by K times and parallelized. A second step of reversing the order of each of the K image signals depending on whether the control signal indicates the forward direction or the reverse direction while generating the converted K image signals; And a third step of respectively supplying J × K image signals output from the system to the N image signal supply lines according to a corresponding dot order. 9. A 2N (N is a natural number of 2 or more) image signal supply line is supplied with parallelized image signals to be used in an image display device capable of changing an image display direction. In the image signal supply method for supplying 2N image signals parallelized to the image signal supply line of No. 1, the input image signal is time-doubled and the first image signal corresponding to odd dots and the even image dots are supported. When the control signal indicates the forward direction, the first image signal is output to the first processing system and the second image signal is output to the second image signal. When outputting to the processing system and the control signal indicates the reverse direction, the second image signal is output to the first processing system and the first image signal is output to the second processing system. In the first step and the first processing system , N image signals are generated by parallelizing the supplied image signal by expanding the time by N times, and the second processing system parallelizes the supplied image signal by expanding the time by N times. A second step of reversing the order of each of the N image signals depending on whether the control signal indicates a forward direction or a reverse direction while generating N image signals; A third image signal supply line that supplies the N image signals output from the system and the N image signals output from the second processing system to the 2N image signal supply lines according to the corresponding dot order. A method for supplying an image signal, comprising: