JP3517884B2 - Data processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system DMA.
The present invention relates to a data input / output method in a control unit. With recent demands for improving the performance of computer systems, it is necessary to perform input / output processing efficiently. However, with the recent increase in the number of input / output devices (I / O) connected to computer systems, central processing units (C
There is a tendency that access from the PU to the main storage device (MSU) and access from the input / output device (I / 0) to the main storage device (MSU) often conflict with each other. In particular, when low-speed input / output processing such as a disk device and message communication is present, the high-speed central processing unit (CPU) competes with the access to the main storage unit (MSU), and the central processing unit (CPU) CPU performance is often affected. [0004] Because of this, the central processing unit (CPU)
Data between the input / output unit (I / O) and the main storage unit (MSU) on a data bus commonly used by the input / output unit (I / O) and the main storage unit (MSU). There is a demand for a data input / output method that makes effective use of the idle time generated in the transfer. FIG. 6 is a diagram for explaining the operation of a conventional direct memory access (hereinafter referred to as DMA) control unit. FIG. 6A shows an example of the configuration of a computer system, and FIG. ),
(b2) shows a normal accessible range at the time of data transfer by DMA, and (c) shows a problem at the time of data transfer by conventional DMA. A central processing unit (C) as shown in FIG.
PU) 1, main storage unit (MSU) 2, and input / output unit (I / O) 3
And a DMA controller (DMAC, hereinafter abbreviated) that controls data transfer between the main storage device (MSU) 2 and the input / output device (I / O) 3
Each of the devices is connected by an internal bus 6, and the memory is managed by an address translation buffer (TLB) 10 in the central processing unit (CPU) 1. In the system, the DMA control unit 4 sends a message from a central processing unit (CPU) 1 to a main storage unit (MSU).
2 After receiving the data transfer start address, current address, and number of bytes transferred, and setting them in the specified register,
Based on a start instruction from the central processing unit (CPU) 1,
Data is autonomously transferred between the main storage device (MSU) 2 and the input / output device (I / 0) via the internal bus 6. In this case, as shown in FIGS. 6 (b1) and 6 (b2), the data read from the input / output device (I / O) 3 to the main storage device (MSU) 2 is completed until the data is read. Storage unit (MSU) 2
Cannot read the data in the area where the data has been read. Also, the main storage unit (MSU) 2 is connected to the input / output unit (I
Until the data writing to / O) 3 is completed, new writing cannot be performed from the central processing unit (CPU) 1 to the writing area. Therefore, the main storage device (M
While the data transfer by the DMA is performed between the (SU) 2 and the input / output device (I / O) 3, for example, the input / output device (I / 0) 3 is a low-speed input / output device. Ah, internal bus 6
If the above data transfer has a vacant period as shown in FIG. 6C, for example, even if an attempt is made to access the transfer data C, the transfer data C is still in the main storage device ( MSU) 2 cannot be read or written, so the central processing unit (CP
U) 1 cannot access (read, write) the data transfer area of the main storage device (MSU) 2 until the series of data transfer is completed, and the central processing unit (CPU)
There was a problem that the calculation performance of 1 was hindered. In view of the above-mentioned conventional disadvantages, the present invention provides a central processing unit (CPU), a main storage unit (MSU), and an input / output unit (I / O).
And a DMA control unit for transferring data between the main storage device (MSU) and the input / output device (I / O) .The memory management is performed by an address translation buffer (TLB), and data input / output is performed. A data input / output method in a DMA control unit that can access data in a main storage unit (MSU) that does not cause side effects even during data input / output in the DMA control unit. It is intended to do so. FIGS. 1 to 3 are explanatory diagrams of the principle of the present invention. FIGS. 1 and 2 (a1) and (a2) show the case of reading data. (b1) and (b2) show the case of writing data, (a1) and (b1) show the relationship between the memory management table and the main storage unit (MSU), and (a2) and (b2) show the operation 3A shows a time chart, FIG. 3A shows the principle of address translation, and FIG. 3B shows the concept of an address translation buffer (TLB). The above problem was configured as follows
The problem is solved by the data input / output circuit in the DMA controller. A data processing device according to the present invention is a main storage device.
, I / O devices, and translate logical addresses to physical addresses
A central processing unit having an address translation buffer
D for controlling data transfer between a storage device and an input / output device
And a MA control unit.
During the DMA transfer of data by the A control unit, the central processing unit
Access address when access to main storage
Is the data-transferred area on the main storage device by DMA transfer
Access area detecting means for detecting whether the
Issued, the central processing unit accessed main storage.
When the access address is the main storage device by DMA transfer
Data access when in the data transferred area above
And when the data is outside the data transfer area, the central processing
Access control means for notifying the outside of the access area
Configuration. [0013] The access area detecting means may include a main storage device.
Transfer of data between a device and an input / output device by DMA transfer
Data transfer number counting means for counting the number of transmissions;
A control unit, access from the central processing unit to the main storage device
When the upper address of the logical address matches,
Logical address of access from main processor to main storage
Counter by the lower address of
Address comparing means for comparing the number of transferred data
And the result of the comparison, the central processing unit
Whether the access address to is in the data transferred area
And a region determining means for determining whether Further , the central processing is performed by the access control means.
When the device is notified of the out of access area, the central processing unit
Holds access to main storage for a certain period of time
This is a configuration having access hold means. [0017] The operation of the address translation buffer (TLB) shown in FIG.
Numeral 10 is for converting a logical address indicating a block of a huge logical address space of the virtual memory address space into a physical address of an actual main storage unit (MSU) 2 as shown in FIG. 3 (a). And logical address-physical address pair information obtained by a dynamic address translation mechanism (DAT) not shown. Here, "Base" indicates a base register storing a physical address corresponding to a hit logical address (upper), and a physical register corresponding to the logical address (upper) is included in the base register. Contains the address (upper). "R, e, w" and the like indicate "attributes" indicating the validity of access, and "Len" indicates the data length in the word direction of the logical address block on the main storage unit (MSU) 2. I have. Normally, memory addresses are managed by the base registers "Base", "r, e, w", and "Len" of the address translation buffer (TLB) 10. It is known. According to the present invention, the address translation buffer (TL
B) The register "Len" for "Len" of 10 or "Cnt" instead of "Len" is actually read or updated by updating in synchronization with data input / output, or
Focusing on the fact that the area of the written (unnecessary) data can be recognized, the central processing unit (CPU) 1
When the main storage (MSU) 2 is accessed,
The access from the central processing unit (CPU) 1 is permitted when the start address of the memory space indicated by `` e '' and the area indicated by the `` Len '' are detected. To prevent the access or hold the access for a certain period of time, and when the access area enters the transfer area, the central processing unit (CP
U) to allow access. Hereinafter, the operation and operation of the data input / output circuit in the DMA control unit of the present invention will be described more specifically with reference to FIG. FIGS. 1 (a1) and (a2) show the operation when data is read from the input / output device (I / O) 3 to the main storage device (MSU) 2. In the present invention, the DMA controller 4, a memory management table 42 having the same configuration as that of the address translation buffer (TLB) 10 is provided, and the transfer start address on the main storage device (MSU) 2 is set in the `` Base '' column of the memory management table 42. Thereafter, the “Len” column is set to “0”, and the DMA control unit 4 is started. The DMA control unit 4 increments the “Len” column by “+1” every time there is a data transfer, and the central processing unit (CPU)
Increase read-accessible area from 1 (indicated by diagonal lines). With this mechanism, the central processing unit (CPU) 1
The corresponding area of the main storage device (MSU) 2 can be accessed without waiting until all data arrives from the input / output device (I / O) 3. ｝ Refer to the operation time chart of FIG. 1 (a2)｝ When writing data from the main storage device (MSU) 2 to the input / output device (I / O) 3, it is generally not necessary to change the data to be written. After copying to system buffer
(However, a method in which the transfer area is write-protected and not copied has also been proposed), starts the DMA control unit 4. In the case of the present invention, as shown in FIGS. 2 (b1) and 2 (b2), the main storage (MSU) 2 is used to
O) For the part where data writing to 3 has been completed (indicated by hatching), even if data is being transferred, the central processing unit
Since the operation is performed so as to permit the writing of data from the (CPU) 1, there is no need for copying as in the conventional method, and the waiting time is reduced. << Refer to the operation time chart of FIG. 2 (b2) >> As described above, in the data transfer method using the data input / output circuit in the DMA control unit of the present invention, the side effect of the DMA control unit is not affected even during the data transfer. Since partial data that does not occur can be accessed from the central processing unit (CPU), the copying time when writing data can be reduced, and the performance of the computer system can be improved. Embodiments of the present invention will be described below in detail with reference to the drawings. FIGS. 1 to 3 are explanatory views of the principle of the present invention.
4 and 5 are views showing an embodiment of the present invention,
FIG. 4 shows a case where the memory management table is provided outside the DMA control unit, and FIG.
The figure shows the case where it is provided in the DMA control unit. In the present invention, a central processing unit (CPU) 1
, A main storage device (MSU) 2, an input / output device (I / O) 3, and a DMA for controlling data transfer between the main storage device (MSU) 2 and the input / output device (I / O) 3 In a data processing system comprising a control unit 4 and performing memory management by an address translation buffer (TLB) 10 in the central processing unit (CPU) 1 and inputting / outputting data, an input buffer 40 of the DMA control unit 4 is used. ,
Alternatively, to hold the state of the output buffer 41, for example, the address conversion buffer (T
(LB) A memory management table 42 having the same configuration as that of 10 is provided.
(See FIG. 5) In response to the data transfer in the DMA control unit 4,
The contents of the memory management table 42 are updated, and during the data transfer by the DMA control unit 4, the input / output device is instructed by the updated contents of the memory management table 42.
From (I / 0) 3, the area that has been read into the main storage unit (MSU) 2 or the area that has been written out from the main storage unit (MSU) 2 has the above-mentioned central processing unit (CPU) 1 The means for accessing (reading or writing) is the means necessary to carry out the present invention. Note that the same reference numerals indicate the same objects throughout the drawings. Hereinafter, referring to FIGS. 1 to 3, FIG.
The configuration and operation of the data input / output circuit in the DMA control unit according to the present invention will be described with reference to FIG. 4 and 5 show the interrelationship between the address translation buffer (TLB) 10 and the DMA controller 4. FIG. 4 shows the input buffer 40 or the output buffer 41 managed by the DMA controller 4. As an example in which a memory management table 5 that holds the state of the memory is provided in the central processing unit (CPU) 1 outside the DMA control unit 4, for example,
FIG. 5 shows an example in which only the “n” part is provided as “Cnt” for each channel, and FIG.
The address translation buffer (TLB) 10
An example in which the same configuration is provided is shown. First, in the example of FIG. 4, the central processing unit (CPU)
The counter 1 of the memory management table 5 corresponding to the “Len” portion of the address translation buffer (TLB) 10 provided for the channel for activating the DMA control unit 4 and performing data transfer from now on After resetting Cnt
Control information (transfer start address, transfer amount, etc.) necessary for performing data transfer by the DMA is sent to the DMA control unit 4, and the control information is set in a predetermined control register of the DMA control unit 4. At this point, the DMA control unit 4 is started. The started DMA control unit 4 operates as a main storage device.
Each time an autonomous data transfer is performed between the (MSU) 2 and the input / output device (I / O) 3, the counter `` Cnt '' provided for the channel in the central processing unit (CPU) 1 Is counted up. During the data transfer in the DMA controller 4, when the central processing unit (CPU) 1 issues an access instruction (read or write) to the main storage unit (MSU) 2, the access address It is checked whether or not the upper address of (logical address) matches the “Addr” part of the address translation buffer (TLB) 10, and if it matches (i.e., hits), it is converted to a physical address, and This is added to the lower address of the address to generate the physical address to be accessed, and the lower address is
When the detection means (area check) 43 detects that the data is within or within the area to which data has been transferred by comparison with the counter "Cnt", the access to the main storage unit (MSU) 2 by the access instruction is performed. In the comparison, the detection means 43 detects that the data is outside the area to which data has been transferred, and when a trap different from a so-called normal access exception occurs, the memory access is temporarily stopped by the central processing unit. (CPU) 1, and, for example, as described later, transition to execution of another program. Then, when it is detected that the access address is in or within the area to which data has been transferred, the program returns to the program including the relevant access instruction, and the access instruction to the area is executed. At this time, the address translation buffer (TLB) 10
(Normal read access, normal write access, etc.) are checked at the same time, and the validity of the access is confirmed. Next, FIG. 5 shows a memory management table 42 for holding the state of the input buffer 40 or the output buffer 41 at the time of data transfer in the DMA control unit 4.
4 and the access conversion buffer (TLB) 10
The "Len" section has a function of counting the number of bytes of data transfer. Here, after the “Len” part having the counting function in the memory management table 42 in the DMA control unit 4 is set to “0”, predetermined control information is sent out, The DMA control unit 4 is started at the time when it is set in a predetermined control register in the control unit 4. The DMA controller 4 counts up the "Len" section every time data transfer is performed. On the other hand,
During the data transfer by the DMA controller 4, when the central processing unit (CPU) 1 issues an access instruction (read or write) to the main storage unit (MSU) 2, the central processing unit (CPU) 1 Then, it is checked whether or not the upper address of the access address (logical address) indicated by the access instruction matches the “Addr” portion of the access translation buffer (TLB) 10. The logical address (upper) is converted to a physical address, added to the lower address of the logical address to generate the physical address to be accessed, and the memory management table 42 in the DMA controller 4 Look at the "Len" section,
It is checked whether the lower address of the logical address specified by the access instruction does not exceed the area specified by the "Len" part in the DMA control unit 4, and it is determined that the lower address is within the area. Is detected by the detection means (area check) 43, the access instruction is executed with respect to the main storage device (MSU) 2 even though the DMA control unit 4 is transferring data. When the detection means 43 detects that the address indicated by the access instruction is outside the above-mentioned area or (that is, a trap is generated), an exception different from the normal access exception is generated. Then, the execution of the access instruction is temporarily held, and the process is shifted to another process, for example, another program. Then, the data transfer in the DMA control unit 4 proceeds, and the address specified by the access instruction is changed to the read or written area, or
When it is detected that the access instruction has been entered, the program shifts to the program of the stored access instruction, and operates to execute the stored access instruction. At this time, as described above, the attributes of the address translation buffer (TLB) 10 (non-readable, writable, normality of access to, etc.) are checked at the same time, and the validity of the access is confirmed. . As described above, the data input / output method using the address translation buffer (TLB) according to the present invention comprises a central processing unit (CPU), a main storage unit (MSU), and an input / output unit (I / O).
And a DMA control unit for transferring data between the main storage device (MSU) and the input / output device (I / O) .The memory management is performed by an address translation buffer (TLB), and data input / output is performed. In the computer system for performing the above, the input buffer managed by the DMA control unit and the memory management table holding the state of the output buffer are configured to correspond to, for example, the register of the address translation buffer (TLB), and the memory The "data length (Len)" part of the management table is controlled according to the data transfer amount, and while data is being read from the input / output device (I / O) into the input buffer, the data of the read portion is centrally processed. While the device (CPU) is reading or writing data in the output buffer to the input / output device (I / O), the written portion is added to the central processing unit (CPU).
There is a characteristic in that it is made to light. As described in detail above, the data input / output circuit using the address translation buffer (TLB) according to the present invention includes a central processing unit (CPU), a main storage unit (MSU), , An input / output device (I / O), the main storage device (MSU) and an input / output device (I / O).
O), a DMA control unit that transfers data to and from the computer system that manages memory using an address translation buffer (TLB) and inputs and outputs data.
For example, a memory management table that holds the state of the input buffer and the output buffer managed by the DMA control unit is configured to correspond to the register of the address translation buffer (TLB), and the “data length (data length)” of the memory management table is set. Len) '' part is controlled according to the data transfer amount, and while the data is being read from the input / output device (I / O) into the input buffer, the central processing unit (CPU) reads the data of the read portion. Or, while the data in the output buffer is being written to the input / output device (I / O), the written portion is written by the central processing unit (CPU). Central processing unit (CPU) for partial data that does not cause side effects even during transfer
This makes it possible to reduce the copy processing required by the conventional method when writing data, thereby improving the performance of the computer system.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram illustrating the principle of the present invention (part 1). FIG. 2 is a diagram illustrating the principle of the present invention (part 2). FIG. 3 is a diagram illustrating the principle of the present invention (part 3). FIG. 4 is a diagram showing an embodiment of the present invention (part 1); FIG. 5 is a diagram showing an embodiment of the present invention (part 2); FIG. 6 is an operation of a conventional direct memory access control unit. [Explanation of symbols] 1 Central processing unit (CPU) 2 Main storage device
(MSU) 10 Address conversion buffer (TLB) 3 I / O device (I / O) 4 DMA control unit 40 Input buffer 41 Output buffer 42,5 Memory management table 43 Detecting means Start signal or start instruction to DMA control unit Read area Write area

Continuation of front page (56) References JP-A-59-178522 (JP, A) JP-A-3-122746 (JP, A) JP-A-63-86057 (JP, A) JP-A-61-74051 (JP, A) , A) JP-A-63-47825 (JP, A) JP-A-4-308956 (JP, A) JP-B-61-3710 (JP, B1) (58) Fields investigated (Int. Cl. ⁷ , DB G06F 13/38 G06F 13/28

Claims (1)

(57) [Claims] [Claim 1] A main storage device and an upper address of a logical address
Base for storing the physical address of the main storage device corresponding to the
In a data processing device having a central processing unit provided with a segment type address conversion buffer for storing a data register and a DMA control unit for controlling data transfer between a main storage device and an input / output device, a logical address Address translation buffer in address part
Address part output by indexing the
And the lower address part of the logical address is
Physical address that generates a physical address as the address part
Indicates the generation means and the relative position from the start address indicated by the base register
A counter between the main memory and the I / O device.
Counts up each time data is transferred by DMA transfer
Counting means; and, during a DMA transfer, a central processing unit (DMA) in a main storage device.
Of the physical address generated by accessing the transfer area
It is counted by the lower address in
Address comparing means for comparing the counter value with the lower address in the physical address generated as a result of the comparison.
When the dress is smaller than the count value, the access area
Access to main storage from central processing unit
A data processing device comprising: