JP3457432B2 - Method of communication between processors and processor used therefor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention includes a CPU (Central Processing Unit), a memory, and a communication device between processors having a receiving device and a transmitting device, and between a plurality of processors connected by an interprocessor network. And a device for communication between the processors, and more particularly, to a method and a device for inter-processor communication that can improve the transmission processing speed in response to message transmission processing requests by a plurality of UPs (user processes) and can secure the transmission processing. .

[0002]

2. Description of the Related Art Conventionally, in this type of interprocessor communication method and apparatus, a network is provided in which a processor is provided with an interprocessor communication apparatus, and this transmission apparatus receives a backup of processing operation by a CPU and connects a plurality of processors. Communication between the processors is performed via.

Some conventional interfaces between a communication device in a processor and a CPU employ a method of starting message transmission processing by the CPU writing a command in a command buffer in the communication device. .

According to this method, when the CPU requests the transmission of one message and then requests the next transmission, in order to know the end of the processing of the command in the command buffer, the status register in the transmitter is read. There is a need.

Further, when processing a message transmission from UP (user process), the UP makes a system call to the OS so that the OS creates a message header on behalf of the UP and uses the communication device. There is a method of communicating.

In this method, a process switching process from the UP to the OS occurs, and the process of saving the register and the process of recovering the process during the process switching process become one of the overhead factors for the communication between the processors. In particular, when a large number of short messages are transmitted, this overhead becomes significant, which adversely affects communication processing.

On the other hand, when the UP creates a message header and requests the communication device to perform processing, as in the case of the OS, there is a high probability that incorrect information will be specified in the created message header.

The message header includes the destination processor number, source address, destination memory address, etc. If the destination processor number is wrong, another UP
Wrong message is delivered to the processor that is running. If the source address is wrong, the message body is read from an address that is not mapped in the memory and a bus error occurs. In addition, if the destination memory address is wrong, the OS may destroy the data being used and the system may be down.

As a means for solving this problem, all of the destination processor number, the source address and the destination memory address designated by the user are set to logical values, and the logical values relating to the respective information are converted into physical values in the communication device between the processors. There is a method in which this information is protected by having a table that controls.

In this configuration, in the case of the transmitting device, the logical destination processor number is replaced with the physical destination processor number, the logical source address is converted into the physical source address, and the message body is transmitted. In the case of reception processing, the logical destination memory address in the message header is converted into the physical destination memory address and written in the memory. Further, when there is no conversion table corresponding to the logical value designated by the UP when the processing is attempted, this processing becomes an error.

Further, when a plurality of UPs on one processor perform inter-processor communication, a system call is made to the OS to perform inter-processor communication. In this method, when the OS receives requests from a plurality of UPs, it is not possible to use the interprocessor communication device.
Although only S is used, since the system call is used, the above-mentioned problem of deterioration of inter-processor communication performance occurs.

[0012]

Of the above-described conventional interprocessor communication methods and devices, the method of starting message transmission processing by the CPU writing a command in the command buffer in the communication device is
After requesting transmission of one message, the next transmission request needs to read the status of the status register in the transmitter. As a result, transmission requests from the CPU to the transmission device cannot be made consecutively. Further, in order to confirm that the execution by the transmission request is completed, it is necessary to access the status register in the transmission device before making the transmission request.
There is a problem of increasing the communication processing time.

The processor makes a system call to the OS to send a message from the UP, and the OS creates a message header on behalf of the UP,
In the transmission method, process switching processing from the UP to the OS occurs. As a result, there is a problem in that the overhead generated for the communication between the processors due to the processing of saving and restoring the registers necessary for this process switching processing deteriorates the communication performance between the processors.

Further, in the structure having the table for converting the logical value of each information into the physical value in the communication device between the processors, the same page table handled by the CPU is required for the source address and the destination memory address. Become. As a result, there is a problem that a large memory is required to store the entire page table in the communication device. Further, since the page table in the communication device needs to be changed every time the CPU changes the mapping between the logical address and the physical address, the resulting overhead is very large.

Further, when a plurality of UPs are processed by one processor, a system call by the OS is used to perform interprocessor communication by the OS. However, in this case, there is a problem of process switching overhead at the time of system call as described above.

At the time of process switching between the two UPs (UP1 and UP2), the transmission processing requested by the transmission device may not be completed. That is, the allocation of the CPU is changed from UP1 to UP2, but at that time, an unprocessed header remains in the HB (message header buffer) of UP1. The CPU executes the UP1 transmission process.
It must be processed even after switching to P2. Therefore, at some point, the UP executed by the CPU may be different from the UP executed by the transmission device and requested for the transmission process.

An object of the present invention is to provide a pointer register copy for storing the same instruction value as the pointer register of the transmitting device for instructing the write area of the message header on the memory of the processor. Instead of the pointer register in the transmitter, the message header is written in the area designated by the pointer register copy, and the address is read from the transmitter, and the instruction value of the last pointer and the copy of the pointer register is displayed on the memory. Only when they match, the transmission from the user process is directly processed without making a system call, and in the case of a processor that can be transmitted from the user process, the source address and the destination memory address are limited to a predetermined range by the OS. And all submissions from the user process By providing an interrupt for notifying the completion of the processing request, it is possible to reduce the number of times information is exchanged between the CPU and the communication device in the processor, and the communication from the user process can be performed directly, safely and at high speed. An object of the present invention is to provide an interprocessor communication method and apparatus capable of processing a plurality of user processes on one processor.

[0018]

A method for interprocessor communication according to the present invention comprises a CPU, a memory, and a communication device between processors having a receiving device and a transmitting device,
In the method of communication between a plurality of processors connected by an interprocessor network, the memory is the CP
HB containing the header of the message sent by U
(Message header buffer), and a PR copy that stores the same indication value as a PR (pointer register) that indicates the address of the header to be written next to the header, and the transmission device includes the PR copy for the HB. PR
And a CT (counter) for designating the address of the header to be processed next.

On the other hand, the CPU writes the header at the address of the HB designated by the PR copy instruction value on the memory, and then writes the PR instruction value and the PR copy instruction value to the next header. Is updated to the address to be written, and the transmission device sets the PR instruction value and the C
When the transmission processing request is known due to the difference from the indicated value of T, the header is read from the memory area designated by the CT and the message transmission processing is performed. At the end of the transmission processing, the header of the next processing is processed. The CT is updated so as to indicate the storage address, and the transmission processing is performed until the PR indicated value and the CT indicated value match.

As an additional means, the memory is H
B has an LP (last pointer) that points to the last area that can be used in B, and when the CPU writes the header, the CPU compares the LP instruction value with the PR copy instruction value on the memory, Only when the values are the same, C of the transmitting device
The instruction value of T is read and the instruction value of the LP is updated and set immediately before the address of the HB address indicated by the CT. On the other hand, after the update setting, the instruction value of LP and P
When the R copy instruction value matches, the writing of the header is stopped.

As a further additional means, the HB,
PR, CT, PR copy, and LP are UP
When the UP and the OS operate on the CPU, the transmission device includes two sets (for a user process) and for an OS (operating system), and for the UP, the PR indicated value and the CT indicated value. If it is different, the transmission processing request from the UP is determined, while if the PR instruction value and the CT instruction value for the OS are different, it is determined that the transmission processing request from the OS is requested. If the instruction values for both the OS and the OS are different, it is determined that the OS is a transmission request and the transmission processing is performed.

In the above means, when the UP performs inter-processor communication, the transmitting device sets an MKR (mask register) having a mask value preset by the OS and an offset value preset by the OS. OFF (offset register) having
The destination processor number designated by the P header is replaced with the number limited by the mask value and the offset value, and the transmission processing is performed. Further, the transmission device has bits specified in advance by the OS in a SAR (source address register), and a part of the bits of the source address specified by the header of the UP for storing the data to be transmitted, While replacing the bit specified in advance in the SAR with the bit specified in advance by the OS in the DAR (destination address register), the write area on the memory of the destination processor specified by the header of the UP is set. Transmission processing is performed by replacing some of the bits of the destination memory address shown with the bits specified in advance in the DAR.

In the above means, when a plurality of UPs are operating on the processor, the OS provides the HB on the memory for each UP. In addition, the OS
Is currently executing UP1, UP1 to another UP
At the time of switching to 2, the logical addresses of the UP PR and CT referred to by UP2 are not the physical addresses of the UP PR and CT that are registers in the transmission device, but the temporary PR provided on the memory. The page table is set so as to be converted into the physical address of the temporary CT, and the PR and CT values saved from the UP2 save area on the memory are read and set to the temporary PR and temporary CT on the memory. Write 1 to the idle interrupt enable bit in the transmitter, wait for an idle interrupt from the transmitter indicating that all transmission processing requests to be processed in the UP1 HB have been processed, and allocate the CPU to UP2. When the PR for UP and the CT have the same value, the inside of the transmitter causes an idle interrupt to the CPU, sets the STOP bit to 1, and stops the transmission process.

Further, when the idle interrupt occurs from the transmitter, the OS has a P P for UP in the transmitter.
The values of R, CT, SAR, DAR, MKR, and OFR are stored in the save area for UP1 in the memory, and the SAR, DAR, MK in the save area for UP2 in the memory are stored.
The values of R and OFR are set in the registers of the transmitter,
The values of the provisional PR and the provisional CT of UP2 on the memory are set in the UP PR and CT in the transmitter, and the logical addresses of the UP PR and CT referred to by UP2 are
The page table is set so as to be converted into the physical addresses of the UP PR and CT, which are registers in the transmitter, the idle interrupt enable bit is set to 0, and the S
By setting the TOP bit to 0, releasing the stopped state, and returning from the interrupt, the UP2 in the CPU is continuously executed.

Further, the processor according to the present invention is a processor.
It is connected by the network between the processors and the communication between the processors.
A plurality of processors that perform communication,
Is a CPU (central processing unit), a memory, and a receiver.
And a communication device between processors having a storage device and a transmission device.
I have it.

The memory has an HB (message buffer) for storing a header of a message transmitted by the CPU, and a PR (pointer register) for storing an address of an area for storing a header to be written next to the HB by the CPU. A PR copy that stores the same indication value as
And an LP (last pointer) indicating the last area usable in the HB.

Further, the transmitting device indicates on the memory the PR and the header of the message to be processed next on the memory.
T (counter), RL (comparator) that compares the indicated value of the PR and the indicated value of the CT and detects a difference, and if a difference is detected by the RL, it is determined that a transmission processing request is made, The header is read from the memory location designated by the CT to perform message transmission processing, and at the end of the transmission processing, the CT is updated so as to indicate the storage address of the header to be processed next, and the PR Transmission processing means is provided for performing the transmission processing until the instruction value and the instruction value of the CT match, and the receiving device stores the header of the message received from the interprocessor network. A header register) and a BAR (buffer address register) for storing an address of an MB (message buffer) prepared in advance on the memory, When received, stores the header in the HR, the destination memory address in the header or,
Reception processing means for storing in the address of the memory designated by the BAR is provided.

Further, the CPU writes the header at the address of HB designated by the PR copy on the memory, and then updates the designated value of the PR and the PR copy to the address at which the next header is written. PR updating means, a comparing means for comparing the indicated values of the PR copy and the LP at the time of the PR updating, and a CT indicated value of the transmitting device when the comparing means notifies the coincidence of the indicated values. And CT updating means for updating the indicated value of the LP to a value immediately before the indicated value of the CT, and P after the CT update.
When the indicated values of R and LP are the same, a stop unit for stopping the writing of the header is provided.

Further, in addition to the above configuration, the transmission device provides the PR, CT, and RL for UP (user process) and OS (operating system).
Stores the type of message to be sent and sent,
The output of both the RL for P and the RL for OS is received, and the CP
When UP and OS operate in U, if a difference in the indicated values is detected in the UP RL, it is determined that a transmission processing request has been issued from the UP, while a difference in the indicated values is detected in the OS RL. In this case, it is determined that the transmission processing request from the OS has occurred, and if they are different, it is determined that the transmission processing request from the OS has occurred, and one of UP and OS is selected SQ (sequencer). When the SQ notifies the transmission process request, the header is read from the memory address designated by the corresponding CT, each information in the header is stored in each corresponding register, and the corresponding message is sent. Message type information indicating whether the message is for UP or OS is set and transmission processing is performed, and when the processing of the message is completed, the corresponding CT instruction is used to indicate the next message header. And a transmission processing means for updating the value.

Further, a configuration that is further added, the header includes at least information specifying the destination processor (hereinafter, destination processor number), the length information of the message (hereinafter, message word count), stored in the memory Address of the message body (hereafter, source address), the memory address of the destination processor that sends the message (hereafter, destination memory address), and at least information indicating the message type that distinguishes the message processing destination and the message writing destination ( Thereafter, the transmission device includes a message type), the transmission device includes an ER (destination processor number register) for storing a destination processor number and a SAR (source address) for storing the source address, in addition to the PR, CT, and RL. Register) and D for storing the destination memory address AR (destination address register)
And two sets of a user interface (UP) and an OS (operating system), and in addition to the SQ, an LR (message word number register) for storing the number of message words to be transferred, and a header of the UP. The numerical value for limiting the destination processor number of MKR (mask register) and OFR (offset register) stored by the OS, and the transmission processing request by the UP, when there is a transmission processing request from the UP, the HB in the header The destination processor number is read, the AND circuit for inputting the read destination processor number and the stored value of the MKR, the output value of the AND circuit and the stored value of the OFR are input, and the destination processor number is input to the ER. And a logical sum circuit for outputting as.

In addition to the above configuration, the S for UP is added.
The AR is designated by an area for storing a replacement bit previously designated by the OS for replacing a part of the bits of the source address included in the UP message header and the UP for storing a portion other than the replacement bit. And a source address portion area, the transmission device stores the source address read from the header in the memory in the UP SAR when a transmission processing request is made by the UP, and the body of the message. Has a transmission processing means for reading out the message body from an address obtained by combining the source address specified in the UP and stored in the SAR with the numerical value of the replacement bit, and transmitting the message body to the interprocessor network. .

On the other hand, the DAR for UP stores an area for storing a replacement bit designated in advance by the OS for replacing with a part of the bits of the destination memory address included in the header of the UP message, and other than the replacement bit. Is compared with the area of the destination memory address portion designated by the UP that stores the portion of, and the transmission device determines the destination memory address read from the header in the memory when the transmission processing request is made by the UP. Store in DAR for UP,
When the message is sent to the interprocessor network, it has transmission processing means for sending an address obtained by combining the destination memory address specified in the UP and stored in the DAR with the numerical value of the replacement bit as the destination memory address of the message. ing.

Further, the SQ has a STOP bit that does not start a new transmission process when 1 is written,
If the CPU has an idle interrupt enable bit and the CPU writes 1 to the idle interrupt enable bit, SQ
CP when the values of PR for UP and CT for UP become equal
It has an idle interrupt generation means for interrupting U and writing 1 to the STOP bit to stop.

[0034]

With the above configuration, the transmission processing request between the CPU and the communication device can be independently operated and executed via the HB (message header buffer) on the memory. Also,
Until the PR copy instruction value becomes the same as the LP (last pointer) instruction value, the CPU can request the transmission processing request without checking the progress of the processing of the transmission device.

Further, by using two HBs (message header buffers) for UP and OS, each HB can be provided on a different memory page, so that between the UP (user process) and the OS (operating system). It is possible to eliminate the destruction of the message header in.
Further, since the UP can directly create a message header and request the communication device to perform the transmission process, high-speed communication between the processors from the UP can be realized.

Further, with this configuration, regarding the destination processor number, the source address, and the destination memory address, which require designation without error in communication between the processors,
It can be protected with a small amount of hardware, and system down can be completely avoided.

Further, the destination processor number is limited to the same set of processors by the MKR and OFR designated in advance by the OS. As a result, even if an incorrect destination processor number is specified, the message will reach the same UP and will not reach other UPs.

Since a part of the address register is used to replace a part of the bits of the source address and the destination memory address with bits specified by the OS, only a part of the memory can be accessed. As a result, there is no reading from an address that is not memory-mapped, and the OS data is not destroyed.

Since the HB is provided on the memory, the HBs of a plurality of UPs can be taken on the memory at the same time. By using the idle interrupt, the OS is processed by the transmitter when the process of the CPU is switched. It is possible to know the completion of all the transmission processes of the UPs that are present. at the time,
PR for UP, CT for UP, MKR, OF in the transmitter
R, SAR, and DAR are saved in the save area of this UP, and the saved value of the UP to be executed next is the MK in the transmitter.
By setting to R, OFR, SAR, DAR, U
The P switching process can be performed. As a result, even if a plurality of UPs are processed on one processor, U
P can directly use the interprocessor communication device to perform high-speed and secure communication.

[0040]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a functional block diagram showing an embodiment of the present invention. As shown in FIG. 1, the plurality of processors 1 are connected by an inter-processor network 2 and are connected by a bus 10. The communication device 13 includes a CPU 11, a memory 12, and a communication device 13.
Has a transmitter 15 and a receiver 16.

The memory 12 has an UP (user process) HB (message header buffer) 21, an OS (operating system) HB 22 and an MB (message buffer) 23. This MB23
Normally, the UP and OS are provided similarly to the HBs 21 and 22, but only one buffer is shown in FIG. Each HB 21, 22 has a message header 24 and a message body 25 on the memory 12.
Are stored respectively. Further, for each HB 21 and 22, LP (last pointer) 21 is stored on the memory 12.
1, 22 and PR (pointer register) copy 21
2, 222 are provided. Details of the memory 12 will be described later with reference to FIG.

The transmission device 15 of the communication device 13 has ARs (address register) 30, 40, PR for UP and OS.
(Pointer register) 31, 41, CT (counter) 3
2, 42, and ER (destination processor number register) 33, 43, and for UP, MKR (mask register) 51 and OFR (offset register) 52. In addition, the transmitting device is
It has an idle interrupt bit that specifies that an interrupt will occur when B has no header to process. The details will be described later with reference to FIG.

The receiving device 16 of the communication device 13 includes a BAR (buffer address register) 61 for UP, a BAR 62 for OS, and an HR (message header register) 63. The BARs 61 and 62 store the address in the MB 23 that stores the received message body in the memory 12. The HR 63 also stores the received message header.

The messages stored in the memory 12 of the processor 1 will now be described with reference to FIGS. 1, 2 and 3.

The message has a header 24 and a main body 25. In the illustrated UP message, the header 24 is stored in the HB 21 and the main body is stored in the memory 12.

As shown in FIG. 2, HB for UP
21, the memory 211 (FIG. 1) has an LP211
And a PR copy 212 showing the same contents as the UP PR 31 (FIG. 1) of the transmission device 15, are provided.
The header of the next message is written in the header area of the HB 21 indicated by 2. On the HB 21, the LP 211 indicates the last header area to write the message header, and this instruction is compared with the instruction of the PR copy 212 when the CPU 11 (FIG. 1) writes the message header.

As a result of this comparison, as shown in FIG.
When the instruction of the LP 211 and the instruction of the PR copy 212 match, the CPU 11 causes the transmitter CT 15 for UP 32.
The instruction value 213 is read from (FIG. 1), and as shown in FIG. 3, the LP 215 is set so as to instruct the header area immediately preceding the instruction value 213 of the CT 32, and the instruction is given by the PR copy 212. The message header is written in the header area, and the transmission device 15 is requested to perform the transmission process.

When the CPU 11 writes the message header, the message header is sequentially written from the state shown in FIG. 3, and the transmission process does not end even though the instruction value of the PR copy 212 matches the instruction value of the LP 214. , CT
Even when the instruction value 213 of 32 does not change, the above operation is executed, but the instruction setting of the LP 214 does not change. This means that the write area of the message header is full, so this transmission process is in error.

The same applies to the HB22 for OS.

Next, referring to FIG. 2, the header 2 of the message
The contents of 4 will be described.

In the message header 24, as shown in FIG. 2, the destination processor number 241, the message word number 242, the source address 243, the destination memory address 2
44 and the message type 245 are stored.

The message word number 242 indicates the length of the message body which is the data to be transferred. Source address 2
Reference numeral 43 denotes a storage address of the body 25 of the memory 12 (FIG. 1) which stores the message body 25. The destination memory address 244 stores the designated memory address when the memory address of the destination processor is designated by the source processor.

The message type 245 has a bit indicating the type of message. That is, the message type 245
(1) the storage destination address is the memory address of the transfer destination processor designated by the transfer source processor, or the address designated by the transfer destination processor, that is, the BAR 61, 62 shown in FIG. Information indicating whether the address is an address to be stored, (2) information indicating whether the message to be stored is from the UP or the OS, and the like.

[0055] Next, the configuration of the transmission apparatus 15 of FIG. 1 with reference to FIG. 4 and 5.

As described above with reference to FIG. 1, the transmitter 15 is provided with almost two sets of constituent elements, one for UP (user process) and the other for OS (operating system). RLs (comparators) 34 and 44 are added to the components described above, and ARs (address registers) 30 and 40 include SARs (source address registers) 35 and 45 and DARs (destination memory address registers). ) 36 and 46 are provided. Furthermore, UP
Is provided with an AND circuit 53 and an OR circuit 54 used for limiting the destination processor number, and U
LR (message word number register) 5 for both P and OS
5, SQ (sequencer) 56, and MUXs (multiplexing converters) 57 and 58 are provided.

Further, the SQ 56 is provided with an idle interrupt circuit for informing the HB for UP that there is no more header to be processed. The idle interrupt circuit has an idle interrupt bit that determines whether or not to generate an idle interrupt.

The RLs 34 and 44 and the PRs 31 and 41 and the CT
The numerical values stored in 32 and 42 are compared, and when there is a difference, the SQ 56 is notified of the difference. The source address 243 of the message header 24 (see FIG. 2) is stored in the SARs 35 and 45, and the destination memory address 244 of the message header 24 is stored in the DARs 36 and 46. Further, the number of message words 242 of the message header 24 is stored in the LR 55. SQ56 is RL34
When the storage instruction value difference notification is received from at least one of the RL 44 and the RL 44, the reception of the storage instruction value difference notification is determined to be a transmission processing request received by the transmission device 15 from the CPU 11, and the transmission processing is started. To do.

Further, when the SQ 56 receives a difference in the storage instruction value from both the RLs 34 and 44, the SQ 56 gives priority to the notification from the OS RL 44, and judges that it is a message transmission processing request from the OS and performs the transmission processing.

Next, referring also to FIG. 1 and FIG.
The transmission of a message by will be described.

The CPU 11 uses the OS HB2 of the memory 12
2 creates and stores the message header in the header area designated by the address stored in the OS PR copy 222. At this time, the instruction of the PR copy 222 is OS
When the instruction is the same as the instruction for the LP 221 for CPU,
221 is updated and the OS header is set to HB22.
Write in. If the LP 221 cannot be updated by this procedure, this message header is added to the HB22 as described above.
Can not write to.

After writing the header of the OS message to the HB 22, the CPU 11 updates the addresses of the PR copy 222 on the memory 12 and the OS PR 41 in the transmitter 15 to the address to write the next header. Store. For the OS of the transmission device 15, the RL (comparator) 44
Compares the storage instruction value of the PR 41 stored by the CPU 11 with the storage instruction value of the CT 42 and notifies the SQ (sequencer) 56 of the difference in the storage instruction value. The SQ 56 determines that the notification of the difference in the storage instruction value is received as the transmission processing request received by the transmission device 15 from the CPU 11, and starts the transmission processing.

In the transmission process, first, the transmission device 15 sets the O
With the address stored in the CT 42 for S, from the header of the message stored in the HB 22 for OS of the memory 12, the destination processor number, the number of message words, the source address, and the message similar to those shown in FIG. The type is read out, and when the message body is written in the memory address of the receiving side designated by the transmitting side in the message type, the destination memory address is also read out.

The transmitting device 15 uses the read destination processor number as the ER (destination processor number register) for the OS.
43, the number of message words in the LR 55, the source address in the SAR 45 for the OS, and the destination memory address in the DAR 46 for the OS.
At 8, the header is reconstructed and sent to the interprocessor network 2. In this case, information that is a message from the OS is added to the type of the header message that is sent.

Following the transmission of the header, the transmitter 15
The message body for the number of message words stored in the LR 55 is read from the memory 12 by the address stored in the SAR 45 for OS, and is sent to the interprocessor network 2 via the MUX 58 to end the message transmission.

Upon completion of the message transmission process, the transmission device 15 updates the count value of the CT 42 for OS to a numerical value indicating the header storage area of the message to be transmitted next.

Next, with reference to FIGS. 1, 2 and 4, the case where one UP is executed by one processor will be described as an example to explain the transfer of a message from the UP.

The OS is set to UP by the initial setting of the transmitter 15.
Part of SAR35 for SAR37 and DAR36
Predetermined bits are preset in some of the DARs 38.

The OS is the MKR in the transmitter 15.
The values of the (mask register) 51 and the OFR (offset register) 52 are set in advance so as to represent a set of processor numbers assigned for UP.

First, as in the case of the above-mentioned OS, the CPU 1
1 is a PR for UP on the UP HB 21 of the memory 12
The header of the message is created and stored in the header area designated by the address stored in the copy 212. At this time, the instruction for the UP PR copy 212 is the UP LP 211.
If it is the same as the instruction of, the CPU 11 updates the LP 211 and writes the UP header in the HB 21. If the LP 211 cannot be updated by this procedure, the header of this message cannot be written, as described above.

After writing the header of the UP message in the HB 21, the CPU 11 updates the addresses of the PR copy 212 on the memory 12 and the UP PR 31 in the transmitter 15 to the address to write the next header. Store. On the UP side of the transmitter 15, the RL (comparator) 34
Compares the storage instruction value of the PR 31 stored by the CPU 11 with the storage instruction value of the CT 32, and notifies the SQ (sequencer) 56 of the difference in the storage instruction value. The SQ 56 determines that the notification of the difference in the storage instruction value is received only from the UP, not from the OS, as the transmission processing request from the UP received by the transmission device 15 from the CPU 11, and starts the transmission processing.

In the transmission processing, first, the transmission device 15 makes the U
From the header 24 (see FIG. 2) of the message stored in the UP HB 21 of the memory 12 to the destination processor number 24 by the address stored in the P CT 32.
1, the number of message words 242, the source address 243, and the message type 245 are read, and when the message body is written to the memory address of the receiving side designated by the transmitting side in the message type 245, the destination memory address 244 is also read. The procedure so far is the same as that of the OS.

The transmitting device 15 stores the read message word number in the LR 55. The UP ER (destination processor number register) 33 has the destination processor number 241 and the MKR created in the UP message header 24.
The numerical value stored in 51 is input to the logical product circuit 53 to obtain a logical product, and the logical product value obtained by inputting the logical product value and the numerical value stored in the OFR 52 to the logical sum circuit 54 is Is stored.

The source address 243 stored in the UP message header 24 is SAR3 by the OS.
SAR for UP only for the part other than the part preset to 7
35. Regarding the destination memory address 244, the destination memory address 244 created in the UP message header 24 is written in the UP DAR 36 except for the portion preset in the DAR 38 by the OS. Furthermore, information that this message is a message from UP is added to the message type 245.

After storing the information contained in the header 24 from the memory 12 in each UP register of the transmitter 15, the transmitter 15 reconstructs the header by the MUX 58 and sends it to the interprocessor network 2. At the time of sending, the destination memory address of the sent header is formed by combining the address value of the DAR 36 written this time and the address value of the DAR 38 preset by the OS.

Following the transmission of the header, the transmitter 15
The message body for the number of message words stored in the LR 55 is read from the memory 12 by the address obtained by combining the address value stored in the UP SAR 35 and the address value of the SAR 37 preset by the OS,
The message is sent to the interprocessor network 2 via the MUX 58 and the message transmission is terminated.

Upon completion of the message transmission process, the transmission device 15 updates the count value of the CT for UP 32 to a numerical value indicating the header storage area of the message to be transmitted next.

Next, the reception of a message will be described with reference to FIG.

When the receiving device 16 of the processor 1 receives the message from the interprocessor network 2, it stores the header of the message in the HR 63. The following processing differs depending on the message type included in the header.

First, when writing a message from the OS to the MB23 provided by the processor 1, which is received,
The receiving device 16 writes the main body of the received message in the memory area of the MB 23 of the memory 12 designated by the address stored in the OS BAR 62 of the receiving device 16. As a result, the value of BAR 62 is updated to a value increased by the number of message words in the message body.

Next, when writing a message from the UP and writing it to the MB23 provided by the processor 1,
The reception device 16 writes the main body of the received message in the memory area of the MB 23 of the memory 12 designated by the address stored in the UP BAR 61 of the reception device 16. As a result, the value of BAR61 is updated to a value increased by the number of message words in the message body.

Next, when writing the received message body to the destination memory address specified in the received message header, the received message body is specified by the destination memory address included in the message header stored in the HR 63 first. The main body of the received message is written in the created memory 12.

Next, referring to FIG. 1, FIG. 4 and FIG. 5 together, a method of switching UPs when a plurality of UPs are executed on one processor will be described.

It is assumed that two user processes UP1 and UP2 are executed on the processor. UP1 and U
The P2 has the UP HB21 on the memory 12, and the values of the UP PR31 and the UP CT32 that indicate the header of each HB, and the SAR37 and DAR38 that the OS presets and limits. , MKR51,
The value of OFR52 is different between UP1 and UP2.

It is assumed that UP1 is currently being executed, and now it is time to switch the process, and the OS is trying to switch the process from UP1 to UP2.

The OS first saves the registers and the like in the CPU used by the UP1 in the save area for the UP1 on the memory 12, and then from the save area of the UP2 on the memory 12, as in the normal process switching. , Restores the UP2 execution environment such as CPU registers. Next, the OS is UP
The PR and CT logical addresses referenced from 2 are used as the UP PR31 and UP CT, which are registers in the transmitter 15.
The page table is set so as to be converted into the physical addresses of the temporary PR and the temporary CT on the memory 12, instead of the 32 physical addresses. In addition, the OS is UP2 on the memory 12.
The values of PR and CT saved from the save area for use are read out and set to the temporary PR and the temporary CT. Then, the OS writes 1 to the idle interrupt enable bit 71 in the SQ (sequencer) 56 in the transmitter 15 to enable the idle interrupt, and when the transmission processing requested by the UP1 to the transmitter 15 is completed, the idle interrupt is completed. To happen. Then, the OS assigns the CPU to UP2, and C
The process switching in PU is completed.

UP2 newly assigned to the CPU is
When requesting transmission processing from the transmission device, as described above,
A header is written in the HB 21 for UP2, and PR copy and temporary PR are set so as to indicate the next header area. At this point, the transmitter 15 is still in the H of UP1.
Since the transmission processing request remaining in B21 is being processed,
The header written by UP2 is not processed by the transmitter 15.

The SQ 56 in the transmitter 15 is an R for UP.
When the output from the L (comparator) 34 indicates that the PR (pointer register) 31 for UP and the CT (counter) 32 for UP are equal, the STOP bit 72 is set to 1
Then, a new transmission processing request is not processed and an idle interrupt is generated for the CPU 1 by using the interrupt generation circuit 73.

In the idle interrupt processing routine, the OS
Is the UP1 of UP1 that the transmitter 15 has been executing until now.
PR31 for UP, CT32 for UP, SAR37, DAR3
The values of 8, MKR51 and OFR52 are saved in the save area for UP1 on the memory 12.

Next, the OS reads the value from the UP2 save area on the memory 12, and the SAR3 in the transmitter 15 is read.
7, DAR38, MKR51, OFR52.
Then, the values of the provisional PR and provisional CT of UP2 on the memory 12 are used as the PR 31 for UP and the CT 32 for UP in the transmitter 15.
And the logical addresses of PR and CT referred to by UP2 are written into UP PR31 and CT32 in the transmitter 15.
Set the page table to translate to the physical address of. Finally, the OS writes 0 to the idle interrupt bit 71 and 0 to the STOP bit 72 to allow the transmitter 15 to process a new transmission processing request, and returns from the interrupt processing routine.

At this point, the transmitter 15 also executes the same process UP2 as the CPU 1.

[0092]

As described above, according to the present invention, a copy of the pointer register is provided in the message header buffer in the memory of the processor, and the pointer register copy of the transmitter which indicates the write area of the header. Has the same indicated value as. As a result, when requesting the transmission process, the CPU does not read the address from the pointer register in the transmitter, but writes the header according to the instruction value for copying the pointer register on the memory. Further, the reading of the address from the transmitter is necessary only when the instruction value of the last pointer and the instruction value of the pointer register copy match on the memory.

With this configuration, it is possible to eliminate the reading to the pointer register (PR) in the transmitter, which takes longer than the time to read the data on the memory, and further, the frequency of reading the counter (CT) in the transmitter. To
Since the number of headers that can be stored in the message header buffer can be reduced to one, the processing speed during communication can be improved and speeded up.

Further, the transmission process from the user process is
It processes directly without making a system call. As a result, the overhead of process switching processing is eliminated, and high-speed interprocessor communication can be realized.

Further, in the case of a processor which can be transmitted from the user process, and because the source address, the destination memory address, etc. can be limited to the range preset by the OS, even if the user process sets an incorrect message header, This prevents other users from accidentally sending messages to the processor they are using, and
It is possible to prevent the memory area used by S from being destroyed.

Furthermore, since no logical value is used,
The process of converting a logical value to a physical value is unnecessary, and even when the user process communicates, the transmission process can be performed in the same processing time as the transmission process performed by the OS.

When a plurality of user processes are provided in one processor, even if the CPU and the transmitter process different processes, the user process can directly and safely perform inter-processor communication without using a system call. Is possible.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing an embodiment of the present invention.

2 is a configuration explanatory view showing an embodiment of a memory portion of FIG. 1. FIG.

3 is a configuration diagram showing another embodiment of FIG. 2. FIG.

FIG. 4 is a functional block diagram showing an embodiment of the transmission device of FIG.

5 is a functional block diagram showing an embodiment of the sequencer of FIG.

[Explanation of symbols]

1 Processor 2 Interprocessor Network 10 Bus 11 CPU (Central Processing Unit) 12 Memory 13 Communication Device 15 Transmitter 16 Receiver 21, 22 HB (Message Header Buffer) 23 MB (Message Buffer) 24 Header (Message Header) 25 Main Body ( Message body) 30, 40 AR (address register) 31, 41 PR (pointer register) 32, 42 CT (counter) 33, 43 ER (destination processor number register) 34, 44 RL (comparator) 35, 45 SAR (source) Address register) 36, 46 DAR (destination address register) 51 MKR (mask register) 52 OFR (offset register) 53 AND circuit 54 OR circuit 55 LR (message word number register) 56 SQ (sequencer) 7, 58 MUX (multiplex converter) 61, 62 BAR (buffer address register) 63 HR (header register) 71 idle interrupt enable bit 72 STOP bit 73 interrupt generation circuit 211, 221 LP (last pointer) 212, 222 PR copy ( (Pointer register copy) 241 Destination processor number 242 Message word count 243 Source address 244 Destination memory address 245 Message type

Claims (11)

(57) [Claims] 1. A method of communication between a plurality of processors, comprising a CPU (Central Processing Unit), a memory, and a communication device between processors having a receiving device and a transmitting device, the method comprising: The memory is an HB (message header buffer) that stores the header of the message transmitted by the CPU.
And a PR copy that stores the same designated value as a PR (pointer register) that designates the address of the header to be written next to the header, and the transmitter transmits the PR for the HB and then the PR copy. and a CT (counter) which indicates an address of the header to be processed, on the memory
LP that indicates the last area that can be used in the HB
(Last pointer) , the CPU has a memory on which a header is written when the CPU writes the header.
Compare the indicated value of the LP with the indicated value of the PR copy
However, only when the values are the same, the CT indication value of the transmitter is
Is read out and the H indicates the indicated value of the LP by the CT.
While updating and setting one address before B address,
After the setting, the indicated value of LP and the indicated value of PR copy
If they match, the writing of the header is stopped
If not , the header is written to the HB address designated by the PR copy designation value on the memory, and then the PR designation value and the PR copy designation value are updated to the address for writing the next header. Further, when the transmission device learns the transmission request due to the difference between the PR indicated value and the CT indicated value, it performs a message transmission process by reading the header from the memory area indicated by the CT. At the end of the transmission process, the C
A method of interprocessor communication, characterized in that T is updated and the transmission processing is performed until the PR indicated value and the CT indicated value match. 2. The HB, PR, C according to claim 1 .
T, PR copy, and LP are for UP (user process) and OS (operating system), respectively
It consists of two sets of use, when the UP and the OS operating on the CPU, the transmitting device, the transmission processing from UP if and the indicated value of the CT with the indicated value of the PR is for UP different On the other hand, when the request value is determined to be a request, if the PR instruction value and the CT instruction value for the OS are different, it is determined that the transmission processing request is from the OS, and the instruction values for both the UP and the OS are different. In this case, the method of inter-processor communication is characterized in that the transmission processing is performed by judging the transmission request from the OS. 3. The transmitter according to claim 2 , wherein when the UP performs inter-processor communication, the transmitter has an MKR (mask register) having a mask value preset by the OS, and the preset by the OS. And an OFR (offset register) having an offset value.
The logical product of the destination processor number designated by the header of P and the mask value is calculated , and the logical product and the offset are calculated.
A method of interprocessor communication characterized by replacing with a restricted number by taking the logical sum of the value and the value . 4. The transmitter according to claim 2 , wherein when the UP performs inter-processor communication, the transmitting device has a bit preset in the SAR (source address register) by the OS and designated by the header of the UP. A method for interprocessor communication, characterized in that a part of the bits of the source address storing the data to be transmitted is replaced with a bit designated in advance in the SAR. 5. The transmitter according to claim 2 , wherein when the UP performs inter-processor communication, the transmission device has a bit preset in the OS in a DAR (destination address register) and the header of the UP is used. A method of inter-processor communication, characterized in that a part of bits of a designated destination memory address indicating a writing area on a memory of a destination processor is replaced with a bit designated in advance in the DAR. 6. A processor which is connected by an inter-processor network and performs inter-processor communication with other processors.
In the processor, the processor includes a CPU (central processing unit), a memory, and a communication device between processors having a receiving device and a transmitting device, and the memory is a header of a message transmitted by the CPU. HB (message header buffer) for storing the HB, a PR copy for storing the same indication value as the PR (pointer register) for storing the address of the area for storing the header to be written next to the HB by the CPU, and the HB And a LP (last pointer) indicating the last area that can be used in the PR, the transmitter, the PR, a CT (counter) that indicates a header of a message to be processed next on the memory, and the PR. Comparing the indicated value of the CT and the indicated value of the CT,
An RL (comparator) that detects a difference, and when a difference is detected by the RL, it is determined that a transmission processing request is made, the header is read from the memory location designated by the CT, and the message transmission processing is performed. At the end of the transmission process, the C is used to indicate the storage address of the header to be processed next.
Transmission processing means for performing the transmission processing until T indicated is updated and the indicated value of PR and the indicated value of CT match, and the receiving device includes a header of a message received from the interprocessor network. And an HR (message header register) for storing the address and a B for storing the address of the MB (message buffer) prepared in advance on the memory.
And an AR (buffer address register), which stores a header in the HR when a message is received, and a reception processing unit which stores the header in a destination memory address in the header or an address of a memory designated by the BAR. In addition, the CPU writes a header at an HB address designated by the PR copy in the memory, and then updates the designated value of the PR and the PR copy to the address at which the next header is written. Update means and the PR
At the time of updating, when the comparison means that compares the instruction values of the PR copy and the LP and the comparison of the instruction values are notified from the comparison means, the instruction value of the CT of the transmission device is read and the instruction of the LP is issued. A CT updating means for updating the value to a value immediately before the indicated value of the CT, and a canceling means for stopping the writing of the header when the indicated values of PR and LP are the same even after the CT update. processor for performing communication between processors, characterized in that it comprises. 7. The transmitter according to claim 6 , wherein the PR, CT, and RL are provided in two sets for UP (user process) and OS (operating system), respectively.
In addition, the type of message to be sent is stored, and the RL for UP is stored.
And outputs both OS RL and UP by the CPU
When the RL for OS detects a difference in the indicated values when the OS and the OS operate, it is determined that a transmission processing request from the UP has occurred, while when a difference in the indicated values is detected in the RL for the OS. It is judged that the transmission processing request from the OS has occurred, and
If the two are different, the SQ (sequencer) that selects one of the UP and the OS by determining that the transmission processing request is generated from the OS, and the SQ (sequencer) that is notified when the transmission processing request is generated from the SQ The header is read from the memory address designated by the CT, the information in the header is stored in the corresponding registers, and the message type information indicating whether the corresponding message is for UP or OS is set. A processor for performing inter-processor communication, comprising: a transmission processing means for performing a transmission process and updating a corresponding CT instruction value to instruct a next message header when the processing of the message is completed. 8. The header according to claim 7 , wherein the header is at least information designating a destination processor (hereinafter, destination processor number), message length information (hereinafter, message number), and a message body stored in a memory. Header address (hereinafter, source address), the memory address of the destination processor that sends the message (hereinafter, destination memory address), and at least information indicating the message type that distinguishes the processing destination and the writing destination of the message (hereinafter, the message Type), the transmission device includes, in addition to the PR, CT, and RL, an ER (destination processor number register) that stores a destination processor number, a SAR (source address register) that stores the source address, and DAR (destination address record) that stores the destination memory address Up)
Two sets are provided for (user process) and OS (operating system), and in addition to SQ, LR (message word number register) for storing the number of message words to be transferred, and destination processor number in the header of the UP. The MKR (mask register) and the OFR (offset register) stored by the OS, and the destination processor number in the header from the HB for UP when a transmission processing request is made by the UP. A logical product circuit for inputting the read destination processor number and the stored value of the MKR, and an output value of the logical product circuit and the stored value of the OFR are input and output to the ER as a destination processor number. A processor for performing inter-processor communication characterized by including a sum circuit.
Sa. 9. The SAR for UP according to claim 7 ,
Is an area for storing a replacement bit designated in advance by the OS for replacing a part of bits of the source address included in the header of the UP message, and a source designated by the UP for storing a portion other than the replacement bit. The transmission device stores the source address read from the header in the memory in the UP SAR and reads the body of the message when a transmission processing request is made by the UP. In this case, a transmission processing means for reading out the message body from an address obtained by combining the source address specified in the UP and stored in the SAR with the numerical value of the replacement bit and transmitting the message to the interprocessor network is provided. A processor that performs inter-processor communication. 10. The DAR for UP according to claim 7 .
Is an area for storing a replacement bit previously specified by the OS to replace a part of the bits of the destination memory address included in the header of the UP message, and the UP for storing a part other than the replacement bit. And an area of a destination memory address portion, the transmission device stores the destination memory address read from the header in the memory in the DAR for UP when a transmission processing request is made by the UP, and the message is transmitted. When transmitting to the inter-processor network, it has a transmission processing means for transmitting as the destination memory address of the message an address obtained by combining the destination memory address specified in the UP and stored in the DAR with the numerical value of the replacement bit. A processor that performs inter-processor communication. 11. The SQ according to claim 7 , wherein the SQ does not start a new transmission process when 1 is written.
Bit and an idle interrupt enable bit,
When the PU writes 1 to the idle interrupt enable bit, the SQ interrupts the CPU when the values of the PR for UP and the CT for UP become equal to each other, and writes an 1 to the STOP bit to stop the idle interrupt generation means. A processor for performing inter-processor communication characterized by having
Sa.