JP3233891B2 - Output buffer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data transfer system between LSI chips, and more particularly, to an output buffer circuit for outputting a signal to a bus.

[0002]

2. Description of the Related Art At present, in a data transfer system between LSIs, a high speed data transfer is required. In order to realize high-speed data transfer, the bus drive capability of the output buffer circuit may be set high to improve the responsiveness of the bus potential to a signal, but in this case, power consumption increases. And other problems.

[0003] From such a background, as a means for achieving both high speed and low power consumption in an output buffer circuit, there has been proposed a technique of changing a bus drive capability between a signal transition and a signal holding. I have. This means that at the time of transition of the input signal, the bus drive capability of the output buffer circuit is set high to promote a change in the bus potential, and when the bus potential reaches a predetermined level, the bus drive capability is reduced. As a result, it is possible to reduce the power consumption and increase the response speed of the bus potential to the signal (Mitsuhiro Yamada, "Speeding Up the Interface" (Journal of the Institute of Electronics, Information and Communication Engineers, VOL.76, NO.7, pp721). -
725, July 1993)).

[0004]

However, in the conventional configuration as described above, the bus potential at the time of holding the signal greatly changes due to a sudden change in the amount of current when the bus drive capability of the output buffer circuit is changed. Vibration may occur. This phenomenon undesirably causes a malfunction of a circuit at a subsequent stage of inputting a signal from the bus.

In view of the above problems, the present invention provides an output buffer circuit that realizes a high-speed response of a bus potential to a signal while suppressing power consumption, and stabilizes a bus potential when a signal is held. Make it an issue.

[0006]

Means for Solving the Problems To solve the above-mentioned problems, the invention according to claim 1 comprises, as an output buffer circuit, a driver for driving a bus connected to an output terminal according to an input signal. The drive capability of the driver differs between when the driver changes the bus potential according to the transition of the input signal and when the input signal does not transition and the driver maintains the bus potential. When the bus potential is changed in accordance with the transition, the drive capability control means is set relatively high while the input signal does not transition and the main driver maintains the bus potential. Wherein the drive capability control means gradually lowers the bus potential so as not to vibrate when the drive capability of the driver is reduced.

According to the first aspect of the present invention, the drive capability of the driver is set relatively high by the drive capability control means when the driver changes the bus potential according to the transition of the input signal, and the input signal transitions. When the driver keeps the bus potential without setting it, it is set relatively low.
In other words, the driving capability of the driver is set to be high during the transition of the signal and low during the holding of the signal, so that the response of the bus potential to the input signal can be made high while suppressing the power consumption. In addition, the drive capability control means reduces the drive potential of the driver gently so that the bus potential does not oscillate when lowering the drive capability of the driver. Vibration of the bus potential at the time of signal holding due to the change can be prevented beforehand. Therefore, it is possible to realize a high-speed response of a bus potential to a signal while suppressing power consumption, and to stabilize a bus potential when a signal is held.

According to a second aspect of the present invention, the driver in the output buffer circuit according to the first aspect includes a main driver that drives a bus connected to an output terminal in accordance with an input signal; Is connected,
An auxiliary driver for assisting a bus driving operation of the main driver, wherein the drive capability control means drives the auxiliary driver when the main driver changes a bus potential according to a transition of an input signal. On the other hand, when the input signal does not transition and the main driver maintains the bus potential, it is not driven, and when the drive capability of the auxiliary driver is lowered, the bus potential is gently lowered so as not to vibrate. .

According to the second aspect of the present invention, the auxiliary driver drives when the main driver changes the bus potential according to the transition of the input signal, while the input signal does not transition and the main driver maintains the bus potential. The driving capability is controlled by the driving capability control means so that the driving is not performed when the driving is performed. Therefore, the driving capability of the entire driver is set to be high during the transition of the signal and set to be low during the holding of the signal. In addition, the response of the bus potential to the input signal can be made faster. Moreover,
When the drive capability of the auxiliary driver is reduced, the bus potential is gently reduced so that the bus potential does not oscillate when the drive capability of the auxiliary driver is reduced. , The oscillation of the bus potential during signal holding can be prevented beforehand.

According to a third aspect of the present invention, the drive capability control means in the output buffer circuit according to the second aspect controls the drive capability of the auxiliary driver using a pulse signal as a control signal, and the control signal is: It is assumed that one of the rising edge and the falling edge for lowering the driving capability has a gentler inclination than the other edge for increasing the driving capability.

According to the third aspect of the present invention, the control signal for controlling the drive capability of the auxiliary driver is such that one of the rising edge and the falling edge for decreasing the drive capability is the other edge for increasing the drive capability. Since the slope is gentler than the edge, the bus potential responds at high speed at the time of signal transition, and the oscillation of the bus potential at the time of signal holding caused by a sudden change in the amount of current when lowering the drive capability is reliably prevented. Can be prevented.

According to a fourth aspect of the present invention, in the control signal in the output buffer circuit of the third aspect, the other edge is synchronized with a transition of the input signal.

According to the fourth aspect of the present invention, the control signal for controlling the auxiliary driver is synchronized with the transition of the input signal at the other edge for increasing the drive capability, so that the drive of the auxiliary drive is controlled by the transition of the input signal. At the same time, the response of the bus potential at the time of signal transition can be reliably made faster.

[0014] In the invention of claim 5, according to claim 1,
Output buffer circuit induces a potential change in the opposite direction to the bus potential change at the output end of the driver so that the bus potential does not deviate from a predetermined range when the driver changes the bus potential according to the transition of the input signal. It is assumed that a bus potential suppressing means is provided.

According to a sixth aspect of the present invention, the output buffer circuit includes a driver for driving a bus connected to an output terminal in accordance with an input signal, and the driver connected to an output terminal of the driver. A bus potential suppressing means for inducing a potential change in a direction opposite to the bus potential change so that the bus potential does not deviate from a predetermined range when the bus potential is changed according to the transition of the input signal.

According to the present invention, when the driver changes the bus potential in accordance with the transition of the input signal, the output terminal of the driver is controlled by the bus potential suppressing means so that the bus potential does not deviate from the predetermined range. Since a potential change in the opposite direction to the potential change is induced, the potential change at the output terminal of the driver becomes smooth, thereby preventing occurrence of an abnormal potential such as overshoot or undershoot.

According to a seventh aspect of the present invention, in the output buffer circuit of the sixth aspect, the bus potential suppressing means includes an under-supply circuit for supplying an electric charge to an output terminal of the driver when the potential falls below a predetermined value. At least one of a shoot preventing means and an overshoot preventing means for extracting a charge when an electric potential of the driver exceeds a predetermined value from an output terminal of the driver is provided.

[0018] According to the invention of claim 8, according to claim 6,
The bus potential suppressing means in the output buffer circuit of the above, in synchronization with the transition of the input signal, a pulse generation circuit that generates a pulse signal that transitions in the opposite direction to the bus potential change according to the transition of the input signal, Given a pulse signal,
Also, it is assumed that the other end includes a capacitive element connected to the output end of the driver.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a schematic configuration of an output buffer circuit according to an embodiment of the present invention, which prevents output data from vibrating when the drive capability is changed. In FIG. 1, reference numeral 1 denotes a main driver that drives a bus 51 in accordance with an input signal DIN to an output buffer circuit and maintains the potential of the bus 51, and 2 denotes a bus driver of the main driver 1 when the input signal DIN transitions. An auxiliary driver 3 for assisting the operation is a drive capability control means for controlling the drive capability of the auxiliary driver 2. The driver 4 is composed of the main driver 1 and the auxiliary driver 2.

The input signal DIN is input to the main driver 1 and also to the drive capability control means 3, and the drive capability control means 3 controls the drive capability of the auxiliary driver 2 according to the input signal DIN. The auxiliary driver 2 has an output terminal connected to the main driver 1 (output terminal OU).
T), the output terminal OUT is connected to a bus 51, and the bus 51 is connected to a terminal power supply having a terminal potential Vtt via a terminal resistor 52. The terminal potential Vtt is a potential substantially intermediate between the “H” level and the “L” level of the signal propagating on the bus 51.

The output buffer circuit according to the present embodiment includes a first bus potential suppressing means 10 for preventing overshoot and undershoot of the potential of the output terminal OUT.
And a second bus potential suppressing means 20, which will be described later in detail.

FIG. 2 is a diagram showing a specific configuration example of the auxiliary driver 2 and the drive capability control means 3 in the output buffer circuit according to the embodiment shown in FIG. In FIG. 2, the auxiliary driver 2 is configured as a push-pull type driver, and includes a P-type MOS transistor (hereinafter referred to as “PMOS”) QP1 and an N-type MOS transistor (hereinafter referred to as “NMOS”) QN1. The drive capacity control means 3 includes pulse generation circuits 4a, 4
b and inverters INV1 and INV2, and the pulse generation circuits 4a and 4b
Are input to the inverters INV1 and INV2, respectively. The inverter INV1 outputs the control signal NP for the PMOS QP1 of the auxiliary driver 2, and the inverter INV2 outputs the NMOSQ of the auxiliary driver 2.
The control signal NN of N1 is output.

The drive capability control means 3 sends a PMOS QP to the auxiliary driver 2 in order to speed up the transition of the output data, that is, to speed up the transition of the potential of the output terminal OUT.
1 is increased only when the input signal DIN falls, and the drive capability of the NMOS QN1 is increased only when the input signal DIN rises. PMOS QP1
Is controlled by a control signal NP.
The drive capability of the NMOS QN1 is controlled by a control signal NN.

The pulse generation circuit 4a generates an "H" pulse in synchronization with the falling edge of the input signal DIN, while the pulse generation circuit 4b generates an "L" pulse in synchronization with the rising edge of the input signal DIN. . Inverter INV1 outputs a control signal NP in response to an "H" pulse output from pulse generation circuit 4a, while inverter INV2 outputs a control signal NN in response to an "L" pulse output from pulse generation circuit 4b. .

The point here is that the inverter I
This is the setting of the size of the transistors constituting NV1 and INV2. That is, in the present embodiment, the inverter INV
In the case of 1, the size of the NMOS is set smaller than usual, while for the inverter INV2, the size of the PMOS is set smaller than usual.

FIG. 3 shows the input signal DIN and the control signal N
FIG. 4 is a diagram illustrating a relationship between P and NN and a potential of an output terminal OUT, where (a) illustrates a change over time of each signal and a potential in the output buffer circuit according to the present embodiment;
(B) shows a change over time of each signal and potential in a configuration in which the auxiliary driver 2 is simply turned on / off as a comparative example.

As shown in FIG. 3A, in the output buffer circuit according to the present embodiment, both the control signals NP and NN have a sharp edge for increasing the driving capability of the auxiliary driver 2 and have a sharp edge for decreasing the driving capability of the auxiliary driver 2. The edges are gentle. That is, for the control signal NP, the PMOS QP
The edge at which 1 is turned on, that is, the falling edge, is steep, but the edge at which it is turned off, that is, the rising edge (indicated by a broken circle in the figure) is gentle. On the other hand, as for the control signal NN, the edge when the NMOS QN1 is turned on, that is, the rising edge is steep, but the edge when the NMOS QN1 is turned off, that is, the falling edge (circled by a broken line in the figure) is gentle. . The signal waveforms of the control signals NP and NN as shown in FIG.
This is realized by setting the size of the transistor constituting the NV2.

The drive capability control means 3 responds to control signals NP and NN as shown in FIG.
Drives the auxiliary driver 2 when the potential of the output terminal OUT changes according to the transition of the input signal DIN. On the other hand, when the main driver 1 keeps the potential of the output terminal OUT without the transition of the input signal DIN. , The auxiliary driver 2 is not driven. When the drive capability of the auxiliary driver 2 is increased, the potential of the bus 51 is quickly increased so that the response of the potential of the bus 51 to the input signal DIN is increased. On the other hand, when the auxiliary driver 2 is decreased, the potential of the bus 51 is gradually decreased so as not to vibrate. By such control, when the driver capability of the auxiliary driver 2 is reduced, the bus 51 during signal holding is used.
Can be stabilized.

On the other hand, in the comparative example as shown in FIG. 3B, since the auxiliary driver 2 is simply turned on / off, the control signals NP and NN have rising edges and falling edges. Both are steep pulse signals. That is, the driving capability of the auxiliary driver 2 changes rapidly when it rises and falls. In this case, the potential of the output terminal OUT oscillates due to a rapid current change caused by a change in the driving capability of the auxiliary driver 2. This phenomenon is conspicuous when the driving capability of the auxiliary driver 2 is lowered, that is, when the PMOS QP1 and the NMOS QN1 are turned off (indicated by a dashed circle in the figure), which indicates the potential of the bus 51 during signal holding. As a result, vibration occurs, and a circuit that inputs a signal from the bus 51 may malfunction. In the present embodiment, it is possible to prevent such a problem that the bus potential oscillates when the signal is held.

As described above, according to the output buffer circuit according to the present embodiment, when increasing the drivability of the driver 4, the response of the potential of the bus 51 to the input signal DIN is quickly increased while decreasing it. By gently lowering the potential of the bus 51 so as not to vibrate, it is possible to stabilize the bus potential at the time of holding the signal while realizing a high-speed response of the bus potential to a signal. When the input data DIN does not transition for a long period of time, the auxiliary driver 2 is not driven, and the potential of the output terminal OUT is kept to a minimum by the main driver 1, so that power consumption can be suppressed low. .

The drive capability control means 3 is not limited to the configuration shown in FIG. 2, but may have any configuration as long as it outputs control signals NP and NN as shown in FIG. It doesn't matter.

(First Bus Potential Suppressing Means 10) Next, FIG.
The first bus potential suppressing means 10 shown in FIG.
The first bus potential suppressing means 10 includes a first damper 1 as an undershoot preventing means provided between the output terminal OUT of the main driver 1 and a power supply having the power supply potential Vdd.
1, the output terminal OUT of the main driver and the ground potential V
There is provided a second damper 12 as an overshoot preventing means provided between the ground and the ground having ss.

FIG. 4 is a diagram showing a potential difference / current characteristic of the first and second dampers 11 and 12 constituting the first bus potential suppressing means 10. As shown in FIG. 5A and 5B are diagrams showing a change in the potential of the output terminal OUT. FIG. 5A shows a case where there is no damper, and FIG. 5B shows a case where a damper is provided as in the present embodiment.

As shown in FIG. 4A, the first and second
Assuming that the potential differences of the dampers 11 and 12 are V1 and V2, respectively, and the currents are I1 and I2, respectively, as shown in FIG. 4B, the currents I1 and I2 are exponential functions with respect to the increase of the potential differences V1 and V2, respectively. To increase. By providing the first and second dampers 11 and 12 having characteristics as shown in FIG. 4B, as shown in FIG.
Overshoot and undershoot can be prevented.

That is, when there is no damper, FIG.
As shown in (a), an overshoot exceeding a predetermined range or an undershoot falling below a predetermined range may occur at the potential of the output terminal OUT due to a sudden change in the drive capability of the output buffer circuit. On the other hand, when the first and second dampers 11 and 12 having the characteristics as shown in FIG. 4B are provided, undershoot, that is, the excessive opening between the potential of the output terminal OUT and the power supply potential Vdd is prevented by By supplying a charge to the output terminal OUT by the first damper 11, overshoot, that is, excessive opening between the potential of the output terminal OUT and the ground potential Vss is prevented by the second damper 12.
Can be prevented by extracting the charge from the That is, the first and second dampers 11 and 12 are connected to the output terminal O
When the potential of the UT deviates from the predetermined range, it acts to return the potential to the predetermined range. As a result, as shown in FIG. 5B, no overshoot or undershoot occurs in the potential of the output terminal OUT.

FIG. 6 is a diagram showing a specific configuration example of the first bus potential suppressing means 10. As shown in FIG. In FIG. 6, the first damper 11 includes an NMOS QN2 having a drain connected to the power supply Vdd and a source connected to the output terminal OUT.
The second damper 12 has a PMOS Q having a drain connected to the ground Vss and a source connected to the output terminal OUT.
Consists of P2. The gate potential of the NMOS QN2 is (Vtt + Vtn) (Vttn is the threshold voltage of the NMOS QN2), and the gate potential of the PMOS QP2 is (Vtt + Vtn).
tt−Vtp) (Vtp is the threshold voltage of the PMOS QP2) is set and applied by the potential generation circuit 13.

According to the configuration shown in FIG.
When the potential of the UT falls below the potential Vtt, a current gradually starts flowing through the NMOS QN2, and charges are supplied to the output terminal OUT. On the other hand, when the potential of the output terminal OUT exceeds the potential Vtt, the current gradually starts flowing through the PMOS QP2,
Charge is drawn from the UT. Such an operation can suppress overshoot and undershoot in which the potential of the output terminal OUT greatly deviates from the terminal potential Vtt.

The NMO generated by the potential generation circuit 13
By changing the setting of the gate potentials of the SQN2 and the PMOS QP2, it is possible to control the range of the potential of the output terminal OUT on which the first and second dampers 11 and 12 operate.

The first and second dampers 11, 12
Is not limited to the configuration shown in FIG.
Any configuration may be used as long as it has the characteristics shown in FIG. In addition, the first and second dampers 1
Either one of 1 and 12 may be provided. For example, in an output buffer circuit in which only undershoot is a problem, only the first damper 11 may be provided.

(Second Bus Potential Suppressing Means 20) Next, FIG.
The second bus potential suppressing means 20 shown in FIG.
The second bus potential suppressing means 20 includes first and second capacitance elements C1 and C1 each having one end connected to the output end OUT.
2 and a first and second pulse generation circuit 2 for generating a pulse signal that transits in synchronization with the transition of the input signal DIN
1 and 22 are provided. The pulse signals generated by the first and second pulse generation circuits 21 and 22 respectively correspond to the first and second pulse generation circuits 21 and 22.
And the other ends of the second capacitors C1 and C2.

FIG. 7 is a diagram showing an example of a specific configuration of the main driver 1 and the second bus potential suppressing means 20. FIG.
, The main driver 1 is configured as a push-pull type driver, and a PMOS QP3 and an NMOS
QN3. In addition, the first pulse generation circuit 21
The first pulse signal CIN1 is generated by an AND gate, an inverter and a delay element, and the second pulse generation circuit 22 is generated by a NOR gate, an inverter and a delay element to generate a second pulse signal CIN2. I do.

FIG. 8 is a diagram showing the operation of the circuit shown in FIG. 7, and is a diagram showing a temporal change of the input signal DIN and the first and second pulse signals CIN1 and CIN2. As shown in FIG. 8, the first pulse signal CIN1 is a pulse signal which becomes “H” in synchronization with the rising of the input signal DIN, and the second pulse signal CIN2 is in synchronization with the falling of the input signal DIN. This is a pulse signal that becomes “L”.

When the input signal DIN rises, the output terminal OU
The potential of T is lowered by the main driver 1. At this time, since the first pulse signal CIN1 becomes “H”, a potential change in the pulling direction is induced at the output terminal OUT via the first capacitive element C1. , As a result, the output terminal OUT
Undershoot is suppressed. Similarly, when the input signal DIN falls, the potential of the output terminal OUT is raised by the main driver 1. At this time, since the second pulse signal CIN2 becomes "L", the potential of the output terminal OUT passes through the second capacitor C2. A potential change in the pull-down direction is induced at the output terminal OUT, and as a result, the overshoot of the potential at the output terminal OUT is suppressed.

Here, the first and second capacitive elements C1,
By appropriately setting the capacitance value of C2, the output terminal OU
The degree of the potential change induced by T can be adjusted.

Here, the main driver 1 is a push-pull type driver. However, the second bus potential suppressing means 20 can be similarly applied to an open drain type driver. . FIG. 9 is a circuit diagram showing a configuration in which the second bus potential suppressing means 20 is applied when the main driver 1 is of the open drain type. In FIG. 9, the second pulse generation circuit 22 and the second capacitor C
2 are configured.

Note that the first and second bus potential suppressing means 10 and 20 can be used to add overshoot or undershoot of the output terminal potential of the driver even when added to the conventional output buffer circuit, as in the present embodiment. Can be prevented.

[0048]

As described above, according to the present invention, the driving capability of the driver of the output buffer circuit is set high during the transition of a signal and low during the holding of a signal. A high-speed potential response can be realized, and the drive capability can be gently reduced so that the bus potential does not oscillate. And the bus potential during signal holding can be stabilized.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a schematic configuration of an output buffer circuit according to an embodiment of the present invention.

FIG. 2 is an auxiliary driver 2 of the output buffer circuit shown in FIG.
FIG. 3 is a diagram illustrating a specific configuration example of a drive capability control unit 3.

FIG. 3A is a diagram showing a temporal change of an input signal DIN, control signals NP and NN, and a voltage of an output terminal OUT in an output buffer circuit according to the present embodiment, and FIG. 3 shows the temporal change of the input signal DIN, the control signals NP and NN, and the voltage of the output terminal OUT in a configuration for simply turning on / off.

FIGS. 4A and 4B are diagrams showing potential difference / current characteristics of first and second dampers constituting first bus potential suppressing means of the output buffer circuit according to the present embodiment.

FIG. 5 is a diagram showing a potential change of an output terminal OUT;
(A) shows a case without a damper, and (b) shows a case with a damper as in the present embodiment.

FIG. 6 is a diagram illustrating a specific configuration example of a first bus potential suppressing unit of the output buffer circuit according to the embodiment;

FIG. 7 is a diagram showing a specific configuration example of a main driver and a second bus potential suppressing unit of the output buffer circuit according to the embodiment;

FIG. 8 is a diagram showing the operation of the circuit shown in FIG. 7, in which an input signal DIN and first and second pulse signals CIN;
It is a figure which shows the time change of 1, CIN2.

FIG. 9 is a diagram showing a configuration example in which the second bus potential suppressing means is applied to an output buffer circuit having an open drain type driver.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Main driver 2 Auxiliary driver 3 Drive capability control means 4 Driver DIN input signal OUT Output terminal NP, NN control signal 10 First bus potential suppression means 11 First damper (undershoot prevention means) 12 Second damper (Over Shooting prevention means) 20 Second bus potential suppression means 21 First pulse generation circuit 22 Second pulse generation circuit C1 First capacitance element C2 Second capacitance element CIN1 First pulse signal CIN2 Second pulse signal 51 bus

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03K 19/0175

Claims (8)

(57) [Claims] A driver for driving a bus connected to an output terminal in accordance with an input signal; and a drive capability of the driver when the driver changes a bus potential in response to a transition of an input signal. When the signal is not changed and the driver maintains the bus potential, the difference is set, and when the driver changes the bus potential in response to the transition of the input signal, the input signal is set at a relatively high level. A driving capability control unit that sets the driving potential relatively low when the driver maintains the bus potential. The driving capability control unit prevents the bus potential from oscillating when lowering the driving capability of the driver. An output buffer circuit characterized by being gradually lowered. 2. The output buffer circuit according to claim 1, wherein the driver is a main driver that drives a bus connected to an output terminal according to an input signal, and the main driver and the output terminal are connected to each other. And an auxiliary driver that assists the bus driving operation of the main driver. The drive capability control means changes the bus potential of the auxiliary driver according to a transition of an input signal by the main driver. When the main driver maintains the bus potential, it is not driven, and when the drive capability of the auxiliary driver is lowered, the bus potential is gently lowered so that the bus potential does not oscillate. An output buffer circuit characterized in that: 3. The output buffer circuit according to claim 2, wherein the drive capability control means controls a drive capability of the auxiliary driver using a pulse signal as a control signal, and the control signal includes a rising edge and a rising edge. An output buffer circuit characterized in that, of the falling edges, one edge for lowering the driving capability has a gentler gradient than the other edge for increasing the driving capability. 4. The output buffer circuit according to claim 3, wherein the control signal has the other edge synchronized with a transition of an input signal. 5. The output buffer circuit according to claim 1, wherein when the driver changes a bus potential according to a transition of an input signal, a bus is provided at an output terminal of the driver so that the bus potential does not deviate from a predetermined range. An output buffer circuit comprising bus potential suppressing means for inducing a potential change in a direction opposite to a potential change. 6. A driver for driving a bus connected to an output terminal according to an input signal, and a bus potential at an output terminal of the driver when the driver changes a bus potential according to a transition of an input signal. And a bus potential suppressing means for inducing a potential change in a direction opposite to the bus potential change so that the output buffer circuit does not deviate from a predetermined range. 7. The output buffer circuit according to claim 6, wherein said bus potential suppressing means comprises: an undershoot preventing means for supplying an electric charge to an output terminal of said driver when its potential falls below a predetermined value; An output buffer circuit, comprising: at least one of an overshoot preventing means for extracting a charge when an electric potential of the driver exceeds a predetermined value from an output terminal of the driver. 8. The output buffer circuit according to claim 6, wherein said bus potential suppressing means synchronizes with a transition of an input signal and changes in a direction opposite to a bus potential change corresponding to the transition of the input signal. An output buffer circuit, comprising: a pulse generation circuit that generates the pulse signal; and a capacitor that has one end supplied with the pulse signal and the other end connected to the output terminal of the driver.