JP3184757B2 - Coordinate input device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coordinate input device suitably used as an input device such as a personal computer or a portable information processing device. More specifically, the present invention relates to a coordinate input device which is formed integrally with a display device. Further, the present invention relates to a coordinate input device that performs a predetermined display indicating an input area on a display means, detects coordinates input to the coordinate input means, and outputs the coordinates.

[0002]

2. Description of the Related Art FIG. 11 is a block diagram showing a configuration of a control circuit 1 according to a first prior art. The control circuit 1 is, for example, an LCD of a liquid crystal display device 31 shown in FIG.
(LiquidCrystal Disply) is included in the controller 35. Display is performed on the liquid crystal display panel 32 based on each signal output from the control circuit 1. The control circuit 1 includes a frequency dividing circuit 2, a horizontal synchronizing circuit 3, and an inverter 4.

[0005] The signal XCK and the reset signal supplied to the control circuit 1 are input to the frequency dividing circuit 2. Dividing circuit 2
Sets the frequency of the signal XCK to 1/2, 1/4,.
A plurality of reference signals are created and output by dividing the frequency. The reset signal goes to a high level, for example, at the beginning of each horizontal scanning period to be described later. When the reset signal goes to a high level, the frequency dividing circuit 2 creates the reference signal again from the beginning.

The reference signal is, for example, a VRAM (random access memory for display data) shown in FIG.
It is used as a signal for designating the address 39. The reference signal is input to the horizontal synchronization circuit 3. The horizontal synchronization circuit 3 outputs a horizontal synchronization signal Hsync, which will be described later, based on the reference signal. The signal XCK is output from the inverter 4
And output as the clock signal CK. The control circuit 1 is provided in a duty driving type liquid crystal display device, an analog TFT driving type liquid crystal display device, and the like.

FIG. 12 is a timing chart of each signal in the liquid crystal display device including the control circuit 1. FIG.
The period T1 from the time t2 when the horizontal synchronization signal Hsync falls to the low level to the time t6 when the horizontal synchronization signal Hsync falls next is one horizontal scanning period. In the horizontal scanning period T1, display data is supplied to the electrode driving circuit in a period T3 from the time t3 when the signal ENAB shown in FIG. Horizontal synchronization signal Hsyn
In a period T4 from the time t2 when c falls to the time t3 when the signal ENAB falls, supply of display data is not performed. In the period T4, the display data is fixed at a high or low level. The display data is
This is supplied to the electrode driving circuit in synchronization with the clock signal CK shown in FIG.

The AC signal shown in FIG. 12 (5) is a signal for changing the polarity of the voltage applied to the liquid crystal display panel at predetermined time intervals, for example, the signal level is switched every horizontal scanning period. . The signal level of the alternating signal is switched from time t0 to time t2 when the horizontal synchronization signal Hsync is at the high level, and at times t1 and t5 in a period T2 from time t4 to time t6.

When the signal level of the AC signal is switched, the voltage applied to the display panel is inverted with reference to a predetermined potential. Since the voltage applied to each electrode fluctuates greatly, an induced potential is generated from the surface of the display panel. The induced potential is shown as tablet noise in FIG. The tablet noise starts oscillating at times t1 and t5 when the signal level of the AC signal is switched, and attenuates as time passes.

When the control circuit 1 is provided in a display device of an analog TFT (thin film transistor) driving system, the electrodes are controlled in the horizontal scanning period T1 in response to the rise of the signal HG shown in FIG. A drive voltage based on the display data supplied to the drive circuit is applied to the display panel. The induced potential is also generated when the signal HG rises.

In the liquid crystal display device having the control circuit 1 according to the first prior art, for example, in the case of the duty driving method, an induced potential is generated every time the signal level of the alternating signal changes, and the potential level is relatively high. High noise is generated. In the case of the analog TFT driving method, an induced potential is generated at a timing when the signal level of the signal HG for transferring data from the source driver to the picture element electrode of the display panel is switched, and noise having a relatively high potential level is generated.

[0010] The induced potential generated as described above affects the tablet provided on the display surface of the display panel, and accurate coordinate detection cannot be performed.

FIG. 13 is a block diagram showing a configuration of the gradation signal generating circuit 11 disclosed in Japanese Patent Application No. 6-66145 filed earlier by the present applicant. The gradation signal generating circuit 11 of the second prior art is provided in a display device for performing multi-gradation display, and is included in, for example, the LCD controller 35 shown in FIG. .

The gradation signal generating circuit 11 is used in an active matrix type liquid crystal display device for performing gradation display. In the liquid crystal display device, an analog voltage is created from a digital voltage by applying a pulse-like voltage having a different duty ratio to a pixel electrode without using an analog voltage having a different voltage level. Therefore, a simpler power supply circuit and driver configuration and lower power consumption can be achieved.

The gradation signal generation circuit 11 includes a clock cycle switching circuit 12, a pulse signal generation circuit 13, and an EXNOR.
And a circuit 14. Gradation signal generation circuit 11
Although only one pulse signal generating circuit 13 and one EXNOR circuit 14 are provided, the number of pulse signal generating circuits 13 and the number of EXNOR circuits 14 are provided in accordance with the number of gray scales of the gray scale display to be actually performed. For example, when four such circuits are provided in the gradation signal generation circuit 11, a reference numeral j described later takes a value of 0 to 3. The clock cycle switching circuit 12 receives the signal CLK and period control signals T1, T2, and T3 for controlling a period during which a pulse signal SPj described later is at a high level.
The clock cycle switching circuit 12 generates a signal obtained by dividing the frequency of the signal CLK by と and a signal obtained by dividing the frequency by １ ／, and controls one signal from the two signals and the signal CLK for period control. Selected by signals T1, T2, T3 and signal C
It is output as K.

The signal CK output from the clock cycle switching circuit 12 is input to a pulse signal generation circuit 13. The pulse signal generating circuit 13 outputs the signal CK and the signal RES
Generates the pulse signal SPj. The pulse signal SPj is input to one input terminal of the EXNOR circuit 14. An AC signal AD is input to the other input terminal of the EXNOR circuit 14. The EXNOR circuit 14 calculates the exclusive OR of the pulse signal SPj and the alternating signal AD, and outputs the result as the gradation pulse signal GSj.

FIG. 14 is a timing chart of each signal in the liquid crystal display device including the gradation signal generation circuit 11. Period control signals T1 and T shown in FIGS.
2 and T3 are signals that sequentially become high level corresponding to the period F1, the period F2, and the period F3 of the horizontal scanning period TH shown in FIG. 14A, and the period in which the period control signal T1 is at the high level. F1 is the longest, and the period F3 in which the period control signal T3 is at the high level is set to the shortest.

In the period F1 in which the period control signal T1 is at a high level, the clock cycle switching circuit 12 outputs a clock signal CK having a period four times as long as the clock signal CLK to the pulse signal generation circuit 13, and the period control signal T2 is output. In the high-level period F2, the clock signal CK having a period twice as long as the clock signal CLK is output. In the high-level period F3 of the period control signal T3, the clock signal CLK is output as it is as the clock signal CK. The pulse signal SPj generated by the pulse signal generation circuit 13 has the longest period of the first period F1 and the shortest period of the last period F3 in the horizontal scanning period TH.

The gradation pulse signal GSj shown in FIG.
Is a signal obtained by calculating an exclusive OR of the pulse signal SPj and the alternating signal AD. In the timing chart shown in FIG. 14, it is assumed that the AC signal AD does not change.

The row electrode scanning signal OG1 shown in FIG.
In the row electrode scanning period TG in which the signal is at a high level, a signal for driving the column electrode, which is given to the picture element electrode as an oscillating voltage, is applied. The voltage waveform VP shown in FIG. 14 (8) is applied to the picture element electrode. The voltage waveform VP is a waveform in consideration of the low-pass filter characteristics of the display panel. The voltage waveform VP is not averaged because the period of the oscillating voltage is long in the period F1, but is sufficiently averaged as the period of the oscillating voltage becomes shorter in order from the period F2 to the period F3, so that a substantially constant voltage is obtained. Become. Voltage is applied to, for example, a plurality of column electrodes of the liquid crystal display panel 32 by the signal HG shown in FIG.

Each time the signal HG rises, the potential applied to the column electrodes is switched and the voltage applied to the liquid crystal changes, so that an induced potential is generated from the display panel surface. FIG. 14 (10) shows a waveform of the tablet noise TN generated by the induced potential. Therefore, when the tablet is placed on the display panel surface, the induced potential acts on the tablet, and accurate coordinate detection cannot be performed.

Techniques relating to a display-integrated coordinate input device capable of eliminating the influence of the induced potential generated from the display panel as described above are disclosed in the respective publications as the following third to sixth prior arts. ing.

A third prior art is disclosed in Japanese Patent Application Laid-Open No. 63-26.
There is a coordinate input device with a liquid crystal display disclosed in Japanese Patent No. 8027. FIG. 15 is a timing chart of each signal in the coordinate input device with a liquid crystal display. Each time the signal level of the alternating signal shown in FIG. 15 (1) switches from high to low or from low to high, noise shown in FIG. 15 (4) is generated. In the coordinate input device, an alternating signal,
A signal b shown in FIG. 15 (3) is created based on a signal a shown in FIG. 15 (2) obtained by delaying the AC signal by a delay circuit. The signal b is at a high level during the period T. In the period T in which the signal b is at the high level, the coordinate detection is not performed, thereby preventing the induced signal shown in FIG. 15 (5) from being affected by noise.

A fourth prior art input device is disclosed in Japanese Patent Application Laid-Open No. Hei 4-33126. FIG. 16 is a timing chart of each signal in the input device. In the input device as well, every time the signal level of the AC signal shown in FIG. 16 (3) changes, noise is generated as shown in FIG. 16 (6). In the input device,
By setting the first and second detection signals shown in FIGS. 16A and 16B to a high level, the tablet and a circuit for converting a signal measured by the tablet are connected. The measurement of coordinates is started by the measurement start signal shown in FIG. 16 (4), and the measurement is performed until the measurement end signal shown in FIG. 16 (5) falls. During the measurement of the coordinates, the switching signal shown in FIG. 16 (7) is set to the low level so that the potential by the AC signal is not applied to the display panel. The switching signal is determined based on a measurement start signal and a measurement end signal. Therefore, during the measurement of the coordinates, a change in potential caused by the AC signal does not occur, so that accurate coordinates can be detected.

A fifth prior art electronic device is disclosed in Japanese Patent Application Laid-Open No. 6-187082. FIG.
6 is a timing chart of each signal in the electronic device.
In the electronic device as well, every time the signal level of the alternating signal shown in FIG. 17A changes, noise shown in FIG. 17B is generated. In the electronic device, FIG.
The coordinates are detected based on the detection permission signal shown in FIG. 7 (3). The electronic device monitors the timing at which the signal level of the AC signal changes, and determines the period DIS so as to include the timing at which the signal level changes. The coordinates are not detected in the period DIS, and the coordinates are detected in the period EN other than the period DIS, so that accurate coordinates are detected.

A sixth prior art position information input device is disclosed in JP-A-6-318137.
FIG. 18 is a timing chart of each signal in the position information input device. In the position information input device as well, every time the signal level of the alternating signal shown in FIG. 18 (2) changes, noise shown in FIG. 18 (3) is generated. Only during the period when the signal level of the AC signal is stable,
The coordinate detection signal shown in FIG. 18A is set to a high level to detect the coordinates.

[0025]

The noise synchronized with a change in the signal level of a control signal or the like supplied to the electrode driving circuit even during the period in which the coordinate detection is possible in the third to sixth prior arts described above. Has occurred. The noise has a lower noise level than noise generated based on the AC signal. Therefore, even if there is an influence of noise based on a control signal or the like, when judging whether or not a wide range such as a button displayed on a display panel is instructed, even if the detected coordinates have an error, No problem. However, when recognizing handwritten characters or the like written with a predetermined pointing tool on the display panel,
This is the cause of the decrease in recognition rate.

In recent years, low power consumption has been achieved in portable terminal devices that recognize handwritten characters as described above. For this reason, the voltage applied to the tablet for coordinate detection is changed from, for example, 5 V in the past to, for example, 3.3 V. Since the detection of the coordinates is performed at a low voltage, it is required to reduce noise due to the induced potential.

An object of the present invention is to provide a coordinate input device capable of detecting coordinates with high accuracy.

[0028]

According to the present invention, a display area is constituted by a plurality of horizontal display lines, each of the horizontal display lines being constituted by a plurality of picture elements, and a display area of the display means. A coordinate input means for performing a detection operation of detecting a coordinate designated on the coordinate plate and outputting a coordinate signal, and a horizontal display sequentially every predetermined horizontal scanning period Driving means for scanning a line and applying a voltage based on display data to picture elements constituting the scanned horizontal display line, and display control including a reference signal and display data for defining the horizontal scanning period to the driving means. Control means for transmitting a signal and instructing the coordinate input means to start a detection operation, wherein the control means transmits display data of one horizontal display line within the horizontal scanning period, and In the period until the flat scanning period starts, the potential of the display control signal supplied to the driving unit is fixed, the coordinate input unit is instructed to start the detection operation, and the detection operation is performed. A frequency dividing circuit that divides a signal and outputs a frequency-divided signal; and a synchronizing signal generating unit that generates a horizontal synchronizing signal that defines the horizontal scanning period based on the frequency-divided signal output from the frequency dividing circuit. A period setting unit that determines a period for fixing the potential of the display control signal based on a frequency-divided signal output from the frequency-dividing circuit;
A display control signal output unit that supplies a display control signal to the driving unit during a period other than the potential fixing period, wherein the display control signal is supplied to the driving unit while the potential of the display control signal is fixed during the potential fixing period. A coordinate input device. According to the present invention, the control means in the coordinate input device supplies the drive data to the driving means from after sending out the display data of one horizontal display line in the horizontal scanning period until the start of the next horizontal scanning period. The potential of the display control signal is fixed, and the coordinate input means is instructed to start the detection operation to perform the detection operation. Therefore, the potential of the display control signal is fixed during the period in which the coordinate input means performs the detection operation, and the coordinate of the coordinates is not affected by the induced potential generated from the display means by switching the signal level of the display control signal. Detection can be performed, and accuracy in coordinate detection can be improved. In addition, since the detection of the coordinates is performed in a period after the supply of the display data, which has to be supplied to the driving unit in the horizontal scanning period, is completed, the display performed on the display unit in the next horizontal scanning period is affected. Coordinate detection can be performed without the need.

Further, according to the present invention, a display area is constituted by a plurality of horizontal display lines, and each horizontal display line is arranged so as to overlap a display area constituted by a plurality of picture elements and a display area of the display means. A coordinate input means for detecting a coordinate indicated on the coordinate plate and outputting a coordinate signal, and sequentially scanning a horizontal display line every predetermined horizontal scanning period, A driving unit for applying a voltage based on display data to a picture element constituting the scanned horizontal display line, and a display control signal including a reference signal and display data defining the horizontal scanning period is sent to the driving unit. And control means for instructing the coordinate input means to start a detection operation, wherein the display means has m (m> 1) horizontal display lines composed of n (n> 1) picture elements. ,
The control unit generates a clock signal having a predetermined frequency, supplies display data to the driving unit in synchronization with the clock signal, and applies a voltage based on the display data to the driving unit based on the clock signal. Of the n × a (a> 1) clock signals included in the horizontal scanning period.
During the period from the start of the horizontal scanning period to the supply of the n (a-1) th clock signal, the potential of the display control signal supplied to the driving unit is fixed, and the start of the detection operation is performed by the coordinate input unit. A coordinate input device for instructing a detection operation by instructing and transmitting a display control signal to a driving unit during a remaining period.

According to the present invention, the control means includes a display means including n (n> 1) picture elements in one horizontal display line for performing display based on the display data during the horizontal scanning period. Of the n × a (a> 1) clock signals to be supplied, the period from the start of the horizontal scanning period to the supply of the n (a−1) th clock signal is the predetermined period, and the remaining period Supplies display data to the driving means. Therefore, since the potentials of the clock signal and the display data are fixed during the period in which the coordinate detection is performed, the coordinate detection is performed without being affected by the induced potential generated from the display means by switching the signal level of the display control signal. Can be performed, and the accuracy of coordinate detection can be improved.

[0031]

Further, the present invention provides a driving method based on display data provided via a first electrode to pixel electrodes arranged at intersections of a plurality of first and second electrodes arranged in a direction orthogonal to each other. Applying a voltage through a pixel switching element that is turned on by a pixel control signal supplied through a second electrode, applying a reference constant voltage to a common electrode provided opposite to the pixel electrode, A liquid crystal display panel that performs display by providing a potential difference between the pixel electrode and the common electrode, and a display area is a region where a plurality of pixel electrodes are arranged, and coordinates that are arranged to overlap the display region of the liquid crystal display panel A coordinate input means for detecting a coordinate designated on the coordinate plate and outputting a coordinate signal; and sequentially applying a picture element control signal to each second electrode for each horizontal scanning period. First driving means; A second driving unit for applying a voltage based on display data to the first electrode in the horizontal scanning period, and sending a display control signal including a reference signal and display data defining the horizontal scanning period to each of the driving units; And control means for instructing the coordinate input means to start a detection operation, wherein the display means has m (m> 1) horizontal display lines composed of n (n> 1) picture elements. The control means generates a clock signal having a predetermined frequency, supplies display data to the second drive means in synchronization with the clock signal, and supplies a drive voltage based on the display data to the second drive means based on the clock signal. Is applied to the picture element electrode, and among the n × a (a> 1) clock signals included in the horizontal scanning period, the n (a−1) th clock signal from the start of the horizontal scanning period is supplied. Until the first And fixing the potential of the display control signal to be supplied to the second driving means, instructing the coordinate input means to start the detecting operation, and performing the detecting operation. And transmitting a display control signal.

Further, according to the present invention, m (m
> 1) driving voltages based on display data given via the first electrodes to the pixel electrodes arranged at intersections of the first electrodes and the n (n> 1) second electrodes, respectively. The reference voltage is applied through a pixel switching element that is turned on by a pixel control signal supplied through a second electrode, and a reference constant voltage is applied to a common electrode provided to face the pixel electrode. Display by providing a potential difference between
A liquid crystal display panel having a display area in which a plurality of picture element electrodes are arranged, and a coordinate plate arranged so as to overlap the display area of the liquid crystal display panel, and detecting coordinates indicated on the coordinate plate Coordinate input means for performing a detection operation of outputting a coordinate signal, first driving means for sequentially applying a picture element control signal to each second electrode for each horizontal scanning period, and voltage based on display data in the horizontal scanning period Is applied to the first electrode.
A driving unit, and a control unit that sends a display control signal including a reference signal and display data defining the horizontal scanning period to each of the driving units, and instructs the coordinate input unit to start a detection operation, The control means generates a clock signal having a predetermined frequency, supplies display data to the second driving means in synchronization with the clock signal, and generates a voltage based on the display data from the second driving means based on the clock signal. N × a (a> a) in the horizontal scanning period.
Of the 1) clock signals, during the period from the start of the horizontal scanning period to the supply of the n (a-1) th clock signal, the display control signal supplied to the first and second driving means is supplied. A coordinate input device characterized by fixing a potential, instructing a coordinate input means to start a detection operation to perform a detection operation, and transmitting a display control signal to each drive means in a remaining period.

Further, according to the present invention, the coordinate plate has a structure in which two resistive films having translucency and conductivity, at least one of which is flexible, are arranged at intervals. When a force is applied from the side of the resistive film, the resistive films come into contact with each other, supply a voltage to one resistive film, measure a voltage value on the other resistive film to detect a coordinate in one direction, and It is characterized in that a voltage is supplied to the resistive film, and a coordinate in the other direction is detected by measuring a voltage value at one resistive film.

[0035]

FIG. 1 is a block diagram showing a configuration of a timing circuit 20 used in a coordinate input device 31 according to a first embodiment of the present invention, and FIG. 2 uses the timing circuit 20. FIG. 3 is a block diagram showing a configuration of a coordinate input device 31.

As shown in FIG. 2, the coordinate input device 31
LCD panel 32, column electrode driver 33, row electrode driver 34, LCD controller 35, CPU
(Central processing unit) 36, RAM (random access memory) 37, ROM (read only memory) 38,
It is configured to include a VRAM 39, a tablet 40, a tablet controller 41, and an A / D (analog / digital) converter 42.

In the present embodiment, it is assumed that the liquid crystal display panel 32 as a display means is, for example, a display panel of a duty driving system or a display panel of an analog TFT type driving system. The display panel 32 is provided with a plurality of column electrodes and row electrodes, and a display is performed by applying a predetermined potential supplied from a power supply circuit (not shown) to each electrode. Each pixel is composed of one column electrode and each row electrode provided to be orthogonal to the column electrode. One horizontal display line includes the same number of picture elements as the number of row electrodes provided on the liquid crystal display panel 32. The LCD controller 35 included in the control means includes an electrode driver 33 as a driving means,
A predetermined control signal is supplied to 34, and display data for performing display is supplied to the column electrode driver 33. When the liquid crystal display panel 32 is a display panel of a TFT type driving method, a pixel switching element is provided near a position where a column electrode and a row electrode intersect, and is connected to the pixel switching element. A picture element is formed by the picture element electrode and the common electrode formed so as to cover the plurality of picture element electrodes.

The CPU 36 controls the LCD controller 35, the tablet controller 41, and the A / D converter 42 and calculates the value detected by the A / D converter 42 based on a plurality of control programs stored in the ROM 38. . The RAM 37 temporarily stores numerical values such as calculation results. The VRAM 39 stores display data for each predetermined address.

The tablet 40, which is a coordinate input means, is, for example, a pressure-sensitive tablet, and uses the coordinates pressed by the pen 43 as an analog signal as an A / D converter 4.
Output to 2. A method of detecting coordinates on the tablet 40 will be described later. The A / D converter 42 converts the analog signal supplied from the tablet 40 into a digital signal indicating coordinates, and supplies the digital signal to the CPU 36.

The CPU 36 converts the digital signal into an LCD
The data is supplied to the controller 35, the display data is processed so as to perform a predetermined display on the detected coordinates, and the display is performed on the liquid crystal display panel 32. Tablet 40 and A / D
Converter 42 is controlled by tablet controller 41.

FIG. 3 is a diagram for explaining the principle of detecting coordinates in the tablet 40. In the tablet 40, as shown in FIG.
The axis and the vertical direction are the Y axis. FIG. 3A is a principle diagram showing a method of detecting a predetermined position in the X-axis direction, and FIG.
FIG. 3 is a principle diagram showing a method of measuring a predetermined position in the Y-axis direction.

As shown in FIG. 3, the tablet 40 has a plurality of spacers 152 made of an insulating material interposed between a lower film 150 made of a light-transmitting material and an upper film 151 made of the same light-transmitting material. Structure. The upper and lower films 151 and 150 are conductive members and have a predetermined resistance. A protective film 153 is provided so as to cover upper surface film 151. Note that the top film 151 and the protective film have flexibility. The coordinates are designated by pressing an arbitrary place with the pen 43 from the surface of the protective film 153.

In FIG. 3A, a power supply 154 is connected to both ends of the lower film 150, and a voltage between one end of the power supply 154 and the upper film 151 is measured. In FIG. 3B, the upper film 1
A power supply 154 is connected to both ends of the power supply 51, and a voltage between the power supply 154 and the lower surface film 150 is measured.

In the state shown in FIG. 3A, a voltage of, for example, 3 V is supplied from the power supply 154, and the tip of the pen 43 is brought into contact with a predetermined position and pressed.
The spacer 152 sandwiched between 1 and 150 moves right and left and back and forth, and the upper film 151 and the lower film 150 come into contact with each other. In this case, a voltage having a division ratio determined by the division resistance of the lower surface film 150 corresponding to the X-axis direction is obtained, and this value may be converted into a coordinate value in the A / D converter 42. Similarly,
In the state shown in FIG. 3 (2), a voltage in the Y-axis direction is obtained, and this voltage value is converted into coordinates in the Y-axis direction.

The A / D converter 42 detects the maximum voltage input from the tablet 40 before detecting the coordinates, and digitizes and stores this voltage as the comparison reference voltage VA. When the detection voltage VB is input from the tablet 40 during a coordinate detection period described later, the coordinates are calculated based on the following equation (1).

Coordinate detection position = (detection voltage VB / comparison reference voltage VA) × coordinate maximum value (1) In one coordinate detection period, coordinate detection in only one of the X and Y directions is performed. Therefore, in order to obtain coordinates, coordinate detection must be performed at least twice. The tablet controller 41 detects coordinates continuously twice in both the X and Y directions in order to prevent erroneous detection, and approximates the average only when both values are close. Therefore, coordinate detection is performed four times to obtain one coordinate. If the detected value is not close, re-detection is performed.

Referring to FIG. 1, LCD controller 35
Similarly, the timing circuit 20 included in the control means includes an inverter 21, a frequency dividing circuit 22, and a horizontal synchronizing circuit 23.
A period detection circuit 24, a display data supply circuit 25,
An AND circuit 26 is included. Dividing circuit 22
Divides the frequency of the signal XCK inverted by the inverter 21 into 1/2, 1/4,... To generate a plurality of reference signals which are frequency-divided signals. The signal is supplied to the circuit 24. The signal output from the frequency dividing circuit 22 is used as a signal indicating an address of the VRAM 39 for storing the display data.
The horizontal synchronizing circuit 23, which is a synchronizing signal generating means, counts the reference signal and outputs a horizontal synchronizing signal Hsync for defining a horizontal scanning period to be described later for each predetermined number.

The period detection circuit 24, which is a period setting means, counts the reference signal and outputs a detection signal which becomes low level during a retrievable period described later based on the counting result.

The display data supply circuit 25, which is a display control signal output means, operates in the VRAM
Display data R0 to R2, G0 supplied from
G2, B0 to B2 are supplied to a column electrode driver 33 which will be described later, and the display data is fixed to any value during a fetchable period which is a predetermined period so that the signal potential does not change.

The detection signal is input to one input terminal of the AND circuit 26, and the signal XCK is inverted and input to the other input terminal. The AND circuit 26 calculates the logical product of the signals input from the respective input terminals and outputs the result as a signal CK. The signal CK is supplied to each of the electrode drivers 33 and 3 described later.
4 is supplied.

FIG. 4 is a block diagram showing a configuration example of the frequency dividing circuit 22. In the following description, the inversion input and the inversion output are indicated by adding a suffix “B” to the output, for example, Q1B. The dividing circuit 22 includes the voltage circuit 5
1, frequency divider circuits 52 and 53, diode 54, EX
The circuit includes a NOR circuit 55, an AND circuit 56, and a frequency dividing circuit 57.

The power supply circuit 51 outputs predetermined high and low level potentials. The frequency dividing circuits 52 and 53 are the same circuit, and the output CRY of the frequency dividing circuit 52 is
3 operates as one frequency dividing circuit by being given to the inputs ENP and ENT, respectively. Frequency dividing circuit 52
Are supplied with a high-level potential from the power supply circuit 51. Low-level potentials are supplied from the power supply circuit 51 to the data inputs D0 to D3 of the frequency divider circuits 52 and 53, respectively.

A signal obtained by inverting the signal XCK is input to clock inputs C of the frequency dividing circuits 52 and 53, and the signals SM0 to SM are supplied in response to the rise or fall of the signal.
7, SMB1 to SMB7 are output. Signals SM0 to SM3 are output from outputs Q0 to Q3 of frequency dividing circuit 52, and signals SMB1 to SMB3 are output from outputs Q1B to Q3B. Further, signals SM4 to SM7 are output from outputs Q0 to Q3 of frequency divider circuit 53, and signals SMB4 to SMB7 are output from outputs Q0B to Q3B. Signal SM0
SM7 has a frequency of １ ／ in order from the signal SM0. Similarly, the signals SMB1 to SMB7 are
The frequency is halved from 1 in order.

The signal L is input to the input RB of the frequency dividing circuits 52 and 53.
VCCEN is input via the diode 54,
The frequency divider 52, depending on the signal level of the signal LVCCEN,
53 is reset. Input LO of frequency divider circuits 52 and 53
The output QB of a D flip-flop 71 included in the horizontal synchronization circuit 23, which will be described later, is input to the ADB. The signal LVCCEN is input every horizontal scanning period described later,
The outputs of the frequency dividing circuits 52 and 53 are reset, and the frequency division is performed again from the subsequently input signal XCK.

The output CRY of the frequency dividing circuit 53 is EXNOR.
The signal is input to one input terminal of the circuit 55. To the other input terminal of the EXNOR circuit 55, a signal SMB8 which is an output QB of the frequency dividing circuit 57 described later is input. The EXNOR circuit 55 obtains exclusive OR of the signals input from the two input terminals and outputs the result. The output of the EXNOR circuit 55 is input to one input terminal of the AND circuit 56. A
An output QB of a D flip-flop 71 described later is input to the other input terminal of the ND circuit 56. AND circuit 56
Is supplied to the input D of the frequency dividing circuit 57.

A signal obtained by inverting the signal XCK is supplied to the clock input C of the frequency dividing circuit 57. In response to the rising or falling of the signal, the frequency dividing circuit 57 outputs the signal SCK.
M8 and SMB8 are output. The signals SM8 and SMB8 are
These are signals obtained by dividing the frequency of the signals SM7 and SMB7 by half. The signal LV is input to the input RB of the frequency dividing circuit 57.
CCEN is input, and the frequency dividing circuits 52 and 53 are reset by the signal level of the signal LVCCEN.

FIG. 5 is a block diagram showing a configuration example of the horizontal synchronization circuit 23. The horizontal synchronization circuit 23 includes a signal output circuit 61, a counting circuit 62, and an enable signal output circuit 63
It is comprised including. The signal output circuit 61 outputs the signal SM
1, SM3, SM6, SM7, SMB2, SMB4, S
Based on MB5 and SMB8, the horizontal synchronization signal Hsync
Is output. The counting circuit 62 outputs signals SMB1 and SMB1.
2, SMB5, SMB6, SMB8, SM3, SM4
A period corresponding to 360 clock signals CK is measured based on SM7, and divided by the frequency dividing circuits 52 and 53 and AND.
The signal is supplied to a circuit 56. The enable signal output circuit 63
An enable signal ENAB is output based on each input signal.

The signal output circuit 61 includes an 8-input NOR circuit 6
4, NOR circuits 65 and 66, and D flip-flop 6
7, 68 are included. 8-input NOR circuit 64
Are supplied with the above-described eight signals supplied to the signal output circuit 61, respectively. The 8-input NOR circuit 64 outputs a low-level signal when any one of the eight input signals is at a high level, and outputs a high-level signal when all the signal levels are at a low level. I do.

The output of the 8-input NOR circuit 64 is input to one input terminal of the NOR circuit 65. NOR circuit 65
Is connected to a D flip-flop 6 described later.
7 is provided. The NOR circuit 65 calculates the logical OR of the two input signals and outputs the result. The output of the NOR circuit 65 is input to one input terminal of the NOR circuit 66. The other input terminal of the NOR circuit 66 is supplied with the output of an 8-input NOR circuit 69 of the counting circuit 62 described later. The NOR circuit 66 calculates the logical OR of the two input signals and outputs the result. The output of the NOR circuit 66 is supplied to the input D of the D flip-flop 67.

The D flip-flop 67 is supplied with a signal obtained by inverting the signal XCK by the inverter 21 to the clock input C, and operates in response to the rising or falling timing of the signal. The output Q of the D flip-flop 67 is supplied to the input D of the D flip-flop 68 and the NOR circuit 65. The same signal as the signal supplied to the input C of the D flip-flop 67 is supplied to the input CB of the D flip-flop 68.

The output Q of the D flip-flop 68 is output as a horizontal synchronization signal Hsync. The input SB of the D flip-flop 68 is supplied with the high-level potential from the above-described voltage circuit 51, and is always operating. The aforementioned signal LVCCEN is supplied to the input RB of the D flip-flops 67 and 68,
When VCCEN attains a predetermined level, D flip-flops 67 and 68 are reset.

The counting circuit 62 includes an 8-input NOR circuit 69
, An AND circuit 70, and a D flip-flop 71. The eight-input NOR circuit 69 is supplied with the above-described eight signals supplied to the counting circuit 62. Regarding the operation of the 8-input NOR circuit 69, the aforementioned 8-input NOR circuit is used.
The description is omitted because it is the same as the R circuit 64. 8 inputs N
The output of the OR circuit 69 is output from the NOR circuit 66 and AND
Circuit 70 and D of an enable signal output circuit 63 described later.
The signal is supplied to the flip-flop 72.

The AND circuit 70 has one input terminal supplied with the output of the 8-input NOR circuit 69 and the other input terminal supplied with the signal SM0. In the AND circuit 70,
A logical product of two input signals is obtained and output. AN
The output of the D circuit 70 is the input D of the D flip-flop 71.
Supplied to The D flip-flop 71 is supplied with the output of the above-described inverter 21 at the input CB, and operates in response to the rise or fall of this output. The output QB of the D flip-flop 71 is connected to the frequency dividing circuit 52,
53 and an AND circuit 56.

The enable signal output circuit 63 includes D flip-flops 72 and 73. The input D of the D flip-flop 72 is supplied with the output of the NOR circuit 69. The output QB of the D flip-flop 72 is
It is supplied to the input D of the D flip-flop 73. Output Q of flip-flop 73 is output as signal ENAB. D flip-flops 72 and 73 are connected to each input R
B is supplied with the signal LVCCEN, and the signal LVCC
Reset by EN. The clock input C of the D flip-flop 72 and the D flip-flop 73
The output of the inverter 21 is provided to the inverted clock input CB of the.

FIG. 6 is a block diagram showing a configuration example of the period detection circuit 24. The period detection circuit 24 has an 8-input NOR
Circuit 81, AND circuit 82, D flip-flop 8
3 is included. The 8-input NOR circuit 81 includes:
Signals SM1 to SM5, SM7, SMB6, and SMB8 are supplied. The operation of the eight-input NOR circuit 81 is the same as that of the above-described eight-input NOR circuits 64 and 69, and the description is omitted.

The output of the 8-input NOR circuit 81 is applied to one input terminal of an AND circuit 82. The signal SM0 is supplied to the other input terminal of the AND circuit 82. AN
The D circuit 82 calculates the logical product of the two supplied signals and outputs the result. The output of the AND circuit 82 is input to the input D of the D flip-flop 83. D flip-flop 8
3 outputs a detection signal from the output QB based on the output of the inverter 21 input to the input CB.

FIG. 7 is a block diagram showing a configuration example of the display data supply circuit 25. The display data supply circuit 25
It is configured to include nine AND circuits 84 to 92. AN
Each of the D circuits 84 to 92 is a set of three D circuits, and corresponds to RGB data in the display data. In the display data supply circuit 25, data R0 to R2, G0 to G2, and B0 of three bits each of RGB are provided.
To B2 are used. A detection signal, which is the output of the period detection circuit 24, is supplied to one input terminal of each of the AND circuits 84 to 92. The other terminals of the AND circuits 84 to 92 have the data R0 to R2, G0 to G2, B0 to B
2 are each supplied. Outputs of the AND circuits 84 to 86 are supplied as R data, outputs of the AND circuits 87 to 89 are supplied as G data, and outputs of the AND circuits 90 to 92 are supplied to the column electrode driver 33 as B data. In the present embodiment, each output of the display data supply circuit 25 is fixed at the low level during the detectable period in which the detection signal is at the low level.

FIG. 8 is a timing chart of each signal in the coordinate input device 31. Time t5 when the horizontal synchronization signal Hsync shown in FIG. 8A falls to a low level.
A period T51 from 2 to the next falling time t57 is one horizontal scanning period. In the horizontal scanning period T51, FIG.
Time t5 when signal ENAB shown in (4) becomes high level
In a period T52 from 3 to time 54, the display data is supplied to the column electrode driver 33. In a period other than the period T52, the signal ENAB is fixed at a low level. The display data is given to the column electrode driver 33 in synchronization with the clock signal CK shown in FIG.

The AC signal shown in FIG. 8 (5) is a signal for changing the polarity of the voltage applied to the display panel 32 every predetermined time, and in this embodiment, the signal is changed every one horizontal scanning period. The level switches. The signal level of the alternating signal is switched from time t50 to time t52 when the horizontal synchronization signal Hsync is at a high level, and from time t51 and t56 in a period T53 from time t55 to time t57.

Switching of the signal level of the AC signal,
When a signal for controlling the electrode drivers 33 and 34 is supplied, an induced potential is generated from the surface of the display panel 32. This induced potential is shown as tablet noise in FIG. The tablet noise generated due to the change of the alternating signal vibrates most at time t51, and attenuates with time. Further, tablet noise due to the control signal supplied to each of the electrode drivers 33 and 34 is generated at regular intervals.

As described above, the timing circuit 20 sets the one horizontal scanning period T51 as a period during which the clock signal CK is output 360 times, at the time t5 when the supply of the display data ends.
Period T54 from time t54 after time 4 to time t55
Is a detectable period. In a period T54, each signal level such as the clock signal CK is fixed at a low level,
The display data is also fixed at a low level. Therefore, in the period T54, the voltage applied to the display panel 32 and the voltage applied to each of the electrode drivers 33 and 34 do not change, and no induced potential is generated from the display surface of the display panel 32. By performing the above-described coordinate detection in the period T54, the coordinates can be detected without being affected by the induced potential.

The period T54 is set to be equal to the voltage stabilization period required by the A / D converter 42 used for coordinate detection. In the present embodiment, for example, 5 μs is equal to the time during which 26 clock signals CK are output. Is determined.

In the timing circuit 20, the number of clock signals included in one horizontal scanning period T51 is larger than that of the conventional configuration because the period T54 is included, but the period of the clock signal CK must be shortened. Thus, the display operation can be performed in the same time as the conventional horizontal scanning period.

As described above, according to the first embodiment of the present invention, in the horizontal scanning period T51, the horizontal synchronizing signal Hsync for defining the start of the next horizontal scanning period after the supply of the display data is completed. The period T54 until the rising is a period during which each signal level is fixed, and the coordinates are detected during the period. Therefore, the switching of each signal level is affected by various tablet noises generated from the display panel 32. The coordinates input to the tablet 40 can be detected without the need.

Since only one coordinate axis direction can be detected in the period T54, at least four horizontal scanning periods are required to obtain the coordinates input to the tablet 40. However, since the horizontal scanning period is generally very short, there is no problem even when, for example, capturing and displaying handwritten characters.

FIG. 9 is a block diagram for explaining a second embodiment of the present invention. Gray scale signal generation circuit 100
Is a gradation signal generating circuit portion 101 and a frequency dividing circuit 102
And AND circuits 103 to 106.
The output QB of the frequency dividing circuit 102 is connected to the input D. The horizontal synchronization signal Hsync is input to the clock input C, and the operation is performed based on the signal. Output Q
Outputs a signal HSTOP to be described later.

The clock signal CLK is input to one input terminal of the AND circuit 103 and the signal H is input to the other input terminal.
STOP is input. An output of the AND circuit 103 is input to a CK input of a D flip-flop 113 described later. Period control signals T1, T2, and T3, which will be described later, are input to one input terminals of the AND circuits 104 to 106, respectively. The other input terminals of the AND circuits 104 to 106 have
The signal HSTOP is commonly input.

The gradation signal generation circuit portion 101 includes a clock cycle switching circuit 110, a pulse signal generation circuit 111,
An EXNOR circuit 112 is included. The clock cycle switching circuit 110 includes D flip-flops 113 and 1
14, AND circuits 115 to 117, and a three-input OR circuit 118. Clock cycle switching circuit 1
In 10, the frequency of the clock signal CLK is divided by に よ っ て by the two D flip-flops 113 and 114, respectively. The output of the AND circuit 103 is given to the clock input C of the D flip-flop 113. The output Q of the D flip-flop 113 is the AND circuit 1
The output QB is applied to the input D and the clock input CK of the D flip-flop 114. Output Q of D flip-flop 114 is applied to AND circuit 117, and output QB is applied to input D.

One input terminal of the AND circuit 115 has A
The output of the ND circuit 103 is given, and the other input terminal
The output of ND circuit 106 is provided. AND circuit 116
Of the clock signal CLK at one input terminal
A signal obtained by dividing the frequency by に よ っ て by the flip-flop 113 is supplied, and the output of the AND circuit 105 is supplied to the other input terminal. One input terminal of the AND circuit 117 includes:
The frequency of the clock signal CLK is set to the D flip-flop 11
The signal divided by 1/4 by 3,114 is given,
On the other hand, the output of the AND circuit 104 is given to the input terminal.

The outputs of the AND circuits 115 to 117 are input to a three-input OR circuit 118, respectively. That is, the clock signal CLK, a signal obtained by dividing the frequency of the signal by 1/2, and a signal obtained by dividing the frequency of the signal by 1/4 are selected by the outputs of the AND circuits 104 to 106, respectively. Signal is a three-input OR circuit 11
8, the clock signal CK is input to the pulse signal generation circuit 111.

The pulse signal generation circuit 111 generates a pulse signal SPj based on the clock signal CK from the clock cycle switching circuit 101 and the reset signal RES supplied from another device. The reset signal RES is provided at the start of a horizontal scanning period. By the reset signal RES, the pulse signal SPj becomes, for example, low level. The pulse signal SPj is input to one input terminal of the EXNOR circuit 112. The other input terminal of the EXNOR circuit 112 receives the AC signal AD. EXNOR
The circuit 112 calculates the exclusive OR of the pulse signal SPj and the alternating signal AD, and outputs the result as the gradation pulse signal TSj.

FIG. 10 is a timing chart when the display panel 32 is driven by the control circuit including the gradation signal generation circuit 100. When the number of column electrodes provided on display panel 32 is, for example, 320, grayscale signal generation circuit 100 in the present embodiment sets one horizontal scanning period as a period in which clock signal CK is output 640 times to perform horizontal synchronization. Defines signal Hsync.

The frequency dividing circuit 102 generates a horizontal synchronizing signal Hs
The signal ync is input to the clock input C, and the output from the output Q is given to the AND circuits 103 to 106 as a signal HSTOP shown in FIG. Signal HSTOP
Is at a high level in a period T62.

The period control signals T1, T2 and T3 shown in FIGS. 10 (2) to 10 (4) correspond to the periods F1, F2 and F3 in the horizontal scanning period T61 shown in FIG. 10 (1), respectively.
, Respectively, are sequentially set to the high level, and the period F1 in which the period control signal T1 is at the high level is set to be longest, and the period F3 in which the period control signal T3 is at the high level is set to be shortest.

In the period F1 in which the period control signal T1 is at a high level, the clock cycle switching circuit 100 outputs a clock signal CK having a cycle four times as long as the clock signal CLK to the pulse signal generation circuit 13, and outputs the period control signal T2 During the high-level period F2, the clock signal CK having a cycle twice as long as the clock signal CLK is output. During the high-level period F3 when the period control signal T3 is high, the clock signal CLK is output as it is as the clock signal CK. That is, the pulse signal SPj generated by the pulse signal generation circuit 13 is in the period T
The period of the first period F1 in 61 is the longest, and the period of the last period F3 is the shortest.

The gradation pulse signal GSj shown in FIG.
Is a signal obtained by calculating exclusive OR of the pulse signal SPj and the alternating signal AD. In the timing chart shown in FIG. 14, it is assumed that the AC signal AD does not change.

The row electrode scanning signal OG1 shown in FIG.
During the row electrode scanning period TG in which the signal is at a high level, a signal for driving a column electrode, which is given as an oscillating voltage to a pixel electrode, is applied. The voltage waveform VP shown in FIG. 10 (9) is applied to the picture element electrode. The voltage waveform VP is a waveform in consideration of the low-pass filter characteristics of the display panel. The voltage waveform VP is not averaged because the period of the oscillating voltage is long in the period F1, but is sufficiently averaged as the period of the oscillating voltage becomes shorter in order from the period F2 to the period F3, so that the voltage waveform VP has a substantially constant voltage. Become. Voltage is applied to, for example, a plurality of column electrodes of the liquid crystal display panel 32 by the signal HG shown in FIG.

Each time the signal HG rises, the potential applied to the column electrode is switched and the voltage applied to the liquid crystal changes, so that an induced potential is generated from the display panel surface. FIG. 10 (11) shows a waveform of the tablet noise TN generated by the above-mentioned induced potential.

In the gradation signal generation circuit 100, the signal HSTO obtained by dividing the frequency of the horizontal synchronization signal Hsync by half
A signal for performing display only in a period T62 in which P is at a high level is supplied to each of the electrode drivers 33 and 34.

Time period T during which signal HSTOP is at low level
In 63, a predetermined potential is applied to the column electrode by the rise of the signal HG. In the period T63, the signal HSTO
Since only the P changes, the other signals are fixed at the low level, so that only the tablet noise due to the signal HSTOP is generated. Therefore, by detecting the coordinates in the period T64 from the time when the tablet noise is sufficiently attenuated until the signal for displaying is supplied,
The coordinates can be detected without being affected by any tablet noise.

As described above, according to the second embodiment of the present invention, the period T63 during which the signal HSTOP is at the low level
In the above, the period T64 from the time when the tablet noise generated by the rise of the signal HG is sufficiently attenuated until the signal HSTOP becomes high level is set as the detectable period. Therefore, when detecting the coordinates indicated by the pointing tool such as the pen 43, the coordinates are detected in the period T64 in which the supply of the signal to each of the electrode drivers 33 and 34 in the horizontal scanning period T61 is stopped. The coordinates can be detected without being affected by noise generated when the signal level of a control signal or the like supplied to the electrode drivers 33 and 34 changes. Therefore, it is possible to improve the coordinate detection accuracy.

In each of the above embodiments, the liquid crystal display device and the pressure-sensitive tablet have been described as examples. However, the display device may be an EL (electroluminescence) display device or another type of display device. Other methods such as an electrostatic induction type and an electromagnetic induction type may be used.

[0093]

As described above, according to the present invention, the potential of the display control signal is fixed during the period in which the coordinate input means specified by the control means performs the detecting operation. By switching, coordinates can be detected without being affected by the induced potential generated from the display means, and the accuracy of coordinate detection can be improved.

Further, since the period from the end of the supply of the display data in the horizontal scanning period to the start of the next horizontal scanning period is a predetermined period for performing the coordinate detection, it affects the display performed on the display means. , It is possible to perform highly accurate coordinate detection.

Further, according to the present invention, the control means controls the display means including n (n> 1) picture elements in one horizontal display line to perform display based on display data during the horizontal scanning period. Of the n × a (a> 1) clock signals included, the potential of the display control signal is fixed during the period from the start of the horizontal scanning period to the supply of the n (a−1) th clock signal. Then, the coordinate input means is caused to perform the detection operation, and the display data is supplied to the driving means during the remaining period, so that the potential of the clock signal and the display data is fixed during the period of detecting the coordinates, By switching the signal level of the display control signal, coordinates can be detected without being affected by the induced potential generated from the display means, and the accuracy of coordinate detection can be improved.

[0096]

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a timing circuit used in a coordinate input device according to a first embodiment of the present invention;

FIG. 2 is a block diagram illustrating a configuration example of a coordinate input device 31.

FIG. 3 is a diagram for explaining the principle of coordinate detection in the tablet 40.

FIG. 4 is a block diagram showing a configuration example of a frequency dividing circuit 22.

FIG. 5 is a block diagram illustrating a configuration example of a horizontal synchronization circuit 23;

6 is a block diagram illustrating a configuration example of a period detection circuit 24. FIG.

FIG. 7 is a block diagram illustrating a configuration example of a display data supply circuit 25.

8 is a coordinate input device 31 including a timing circuit 20. FIG.
5 is a timing chart of each signal in FIG.

FIG. 9 is a block diagram for explaining a second embodiment of the present invention.

10 is a timing chart of each signal in the coordinate input device including the gradation signal generation circuit 100 shown in FIG.

FIG. 11 is a block diagram showing a configuration of a control circuit 1 according to a first prior art.

12 is a timing chart of each signal in a display device including the control circuit 1. FIG.

FIG. 13 shows a second prior art gradation signal generation circuit 11;
FIG. 3 is a block diagram showing the configuration of FIG.

FIG. 14 is a timing chart of each signal in a display device including the gradation signal generation circuit 11;

FIG. 15 is a timing chart of each signal in the third prior art.

FIG. 16 is a timing chart of each signal in the fourth prior art.

FIG. 17 is a timing chart of each signal in the fifth prior art.

FIG. 18 is a timing chart of each signal in the sixth prior art.

[Explanation of symbols]

 Reference Signs List 20 timing circuit 21 inverter 22 frequency dividing circuit 23 horizontal synchronizing circuit 24 period detecting circuit 25 display data supply circuit 31 coordinate input device 32 liquid crystal display panel 33 column electrode driver 34 row electrode driver 35 LCD controller

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-8-314634 (JP, A) JP-A-9-128146 (JP, A) JP-A-9-50347 (JP, A) JP-A-8-108 339255 (JP, A) JP-A-8-115156 (JP, A) JP-A-8-123618 (JP, A) JP-A-7-64703 (JP, A) JP-A-6-161658 (JP, A) JP-A-5-150902 (JP, A) JP-A-5-53726 (JP, A) JP-A-2-252015 (JP, A) JP-A-62-286124 (JP, A) (58) (Int.Cl. ⁷ , DB name) G06F 3/033-3/037 G06F 3/03

Claims (5)

(57) [Claims] 1. A display area is composed of a plurality of horizontal display lines, each horizontal display line being composed of a display means composed of a plurality of picture elements, and coordinates arranged so as to overlap the display area of the display means. A coordinate input means for detecting a coordinate indicated on the coordinate plate and outputting a coordinate signal, and sequentially scanning a horizontal display line every predetermined horizontal scanning period. For the picture elements that make up the horizontal display line,
A driving unit for applying a voltage based on display data, a display control signal including a reference signal defining the horizontal scanning period and display data to the driving unit, and instructing the coordinate input unit to start a detection operation. Control means, wherein the control means supplies the driving data to the driving means in a period from after transmitting display data of one horizontal display line in the horizontal scanning period until a next horizontal scanning period is started. A frequency divider circuit for fixing the potential of the display control signal, instructing the coordinate input means to start a detection operation and performing a detection operation, dividing a clock signal of a predetermined frequency to output a divided signal, Synchronizing signal generating means for generating a horizontal synchronizing signal defining the horizontal scanning period based on the frequency-divided signal output from the frequency-dividing circuit; A period setting unit that determines a period for fixing the potential of the display control signal; and in the potential fixing period, the potential of the display control signal is fixed and supplied to the driving unit. In a period other than the potential fixing period, the display control signal is And a display control signal output means for supplying the control signal to the drive means. 2. A display area comprising a plurality of horizontal display lines, each horizontal display line comprising a display means comprising a plurality of picture elements, and coordinates arranged so as to overlap the display area of the display means. A coordinate input means for detecting a coordinate indicated on the coordinate plate and outputting a coordinate signal, and sequentially scanning a horizontal display line every predetermined horizontal scanning period. For the picture elements that make up the horizontal display line,
A driving unit for applying a voltage based on display data, a display control signal including a reference signal defining the horizontal scanning period and display data to the driving unit, and instructing the coordinate input unit to start a detection operation. Control means, wherein the display means has m (m> 1) horizontal display lines composed of n (n> 1) picture elements, and the control means outputs a clock signal of a predetermined frequency. Then, display data is supplied to the driving means in synchronization with the clock signal, and a voltage based on the display data is applied to the picture element by the driving means based on the clock signal, so that n × a ( a> 1) Among the clock signals,
During the period from the start of the horizontal scanning period to the supply of the n (a-1) th clock signal, the potential of the display control signal supplied to the driving unit is fixed, and the start of the detection operation is performed by the coordinate input unit. A coordinate input device for instructing a detection operation in accordance with an instruction and transmitting a display control signal to a driving unit during a remaining period. 3. A driving voltage based on display data provided via the first electrode is applied to picture element electrodes respectively arranged at intersections of a plurality of first and second electrodes arranged in directions orthogonal to each other. The reference voltage is applied through a pixel switching element that is turned on by a pixel control signal supplied through a second electrode, and a reference constant voltage is applied to a common electrode provided to face the pixel electrode. A liquid crystal display panel that performs display by providing a potential difference between the pixel electrode and the common electrode, and a display area is a region where a plurality of pixel electrodes are disposed; and a coordinate plate that is disposed so as to overlap the display region of the liquid crystal display panel. A coordinate input means for performing a detection operation of detecting coordinates designated on a coordinate plate and outputting a coordinate signal; and a first drive for sequentially applying a picture element control signal to each second electrode for each horizontal scanning period Means and said horizontal scanning The voltage based on the display data in the first period.
A second driving unit to be applied to the electrode; a control for transmitting a display control signal including a reference signal defining the horizontal scanning period and display data to each of the driving units, and instructing the coordinate input unit to start a detection operation. The display means has m (m> 1) horizontal display lines composed of n (n> 1) picture elements, and the control means generates a clock signal of a predetermined frequency. The display data is supplied to the second driving unit in synchronization with the clock signal, and the driving voltage based on the display data is applied to the picture element electrode by the second driving unit based on the clock signal, and is included in the horizontal scanning period. Out of the n × a (a> 1) clock signals, n (a−1) from the start of the horizontal scanning period
During the period until the clock signal is supplied, the potential of the display control signal supplied to the first and second driving units is fixed, and the detection operation is instructed by instructing the coordinate input unit to start the detection operation. A coordinate input device for transmitting a display control signal to the first and second driving means during the remaining period. 4. A picture element electrode arranged at a crossing position between m (m> 1) first electrodes and n (n> 1) second electrodes arranged in a matrix, A drive voltage based on display data provided through the electrode is provided through a pixel switching element which is turned on by a pixel control signal provided through a second electrode, and is supplied to a common electrode provided opposite to the pixel electrode. A liquid crystal display panel that applies a constant voltage serving as a reference, performs a display by providing a potential difference between the picture element electrode and the common electrode, and uses a region where a plurality of picture element electrodes are arranged as a display area; and a liquid crystal display panel. A coordinate input means for performing a detection operation of detecting a coordinate designated on the coordinate plate and outputting a coordinate signal; and a second coordinate input means for each horizontal scanning period. First driving means for sequentially applying a picture element control signal to the electrodes , The horizontal scanning period of the first voltage based on the display data in
A second driving unit to be applied to the electrode; a control for transmitting a display control signal including a reference signal defining the horizontal scanning period and display data to each of the driving units, and instructing the coordinate input unit to start a detection operation. The control means generates a clock signal of a predetermined frequency, supplies display data to the second drive means in synchronization with the clock signal, and converts the display data from the second drive means to the display data based on the clock signal. Is applied to the pixel electrodes, and among the n × a (a> 1) clock signals included in the horizontal scanning period, the n (a−1) th clock signal from the start of the horizontal scanning period is In the period until supply, the first and second
Fixing the potential of the display control signal supplied to the driving means,
A coordinate input device for instructing a coordinate input means to start a detection operation to perform a detection operation, and transmitting a display control signal to each drive means during a remaining period. 5. The flexible plate according to claim 1, wherein the coordinate plate has a light-transmitting and conductive property and at least one of the two flexible resistive films is arranged at an interval. When a force is applied from the film side, the respective resistive films come into contact, supply a voltage to one of the resistive films, and measure a voltage value on the other resistive film to detect coordinates in one direction,
The coordinate input device according to any one of claims 1 to 4, wherein a voltage is supplied to the other resistive film, and a coordinate in the other direction is detected by measuring a voltage value of the one resistive film. .