JP3184709B2 - CMOS semiconductor device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a CMOS semiconductor device having a polycide gate and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a dual gate is used to make a CMOS transistor a surface channel type. In this case, in order to realize a low resistance of a gate electrode,
The gate electrode is configured as a polycide gate electrode composed of a polysilicon film and a metal silicide film laminated thereon (hereinafter, this MOS transistor is referred to as a dual polycide gate transistor).

FIG. 3 shows a cross-sectional structure of a conventional dual polycide gate transistor. That is, the n-well 6 and the p-well 5 are formed on the surface of the silicon substrate 7, and the element regions are separated by the element isolation regions.
A gate oxide film 4 is formed in the element region. An nMOS transistor is formed in the p well 5 (in this transistor, an n-type impurity 12 is introduced into polysilicon), and its gate electrode is formed by an n-type polysilicon film 3 and a metal silicide film 1 thereon. It is composed of A pMOS transistor (in this transistor, a p-type impurity 13 is introduced into polysilicon) is formed in the n-well 6, and its gate electrode is formed by a p-type polysilicon film 2 and a metal silicide film 1 thereon. It is composed of The conductivity types of these polysilicon gate electrodes are divided on the element isolation region, and both electrodes are reduced in resistance by the metal silicide film 1 thereon.

[0004]

However, the conductivity type of the gate electrode of this dual polycide gate transistor is formed by separately implanting n-type impurities and p-type impurities in one continuous polysilicon film. For this reason, as shown in FIG.
13 is implanted, the n-type impurity 1
2 diffuses into the metal silicide layer, diffuses inside the metal silicide layer and moves toward the pMOS transistor, and the p-type impurity 13 also diffuses into the metal silicide layer and diffuses inside the metal silicide layer toward the nMOS transistor. Moving.

As a result, the p-type impurity 13 enters the polysilicon gate electrode of the nMOS transistor,
N-type impurity 1 in the polysilicon gate electrode of the transistor
2, the work function of both polysilicon gate electrodes changes, and the threshold voltage of the MOS transistor fluctuates.

Therefore, the p-type polysilicon film and the n-type polysilicon film of the gate electrode are separated on the element isolation region, and a conductive film such as a metal for preventing diffusion of impurities is embedded in the separated region. A structure has been proposed in which impurities are prevented from diffusing through a metal silicide film (JP-A-2-239656). However, in manufacturing a semiconductor device having such a structure, there is a problem that lithography and etching steps increase.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and has as its object to provide a CMOS semiconductor device capable of preventing impurities from diffusing into a metal silicide layer and a method of manufacturing the same. It is in.

[0008]

A CMO according to claim 1
An S semiconductor device is a CMOS semiconductor device having a p-type polycide gate electrode and an n-type polycide gate electrode, wherein a polycide (polysilicon film and metal) connecting the p-type polycide gate electrode and the n-type polycide gate electrode is provided. in the wiring structure) in which two layers of silicide, pMOS territory
Only in the intermediate region between the region and the nMOS region, or in the intermediate region
Is characterized by containing atoms that prevent diffusion of impurities at a higher concentration than other regions .

According to a second aspect of the present invention, there is provided a method of manufacturing a CMOS semiconductor device according to the first aspect, wherein an opening is formed only in an intermediate region between a pMOS region and an nMOS region after metal silicide is stacked. Using a resist pattern having a mask as a mask to introduce atoms that prevent diffusion of impurities.

According to a third aspect of the present invention, there is provided a method of manufacturing a CMOS semiconductor device according to the first aspect, wherein a resist pattern for forming a p-type diffusion region of a pMOS region is defined as a pMOS region. nMOS region
It is formed so as to have an opening including the intermediate region, and the resist
A step of introducing an atom that prevents diffusion of impurities pattern as a mask, the resist pattern at the n-type diffusion region formed in the nMOS region to have an opening that also includes the intermediate region
Forming the resist pattern and introducing an atom that prevents diffusion of impurities using the resist pattern as a mask.

[0011]

According to the CMOS semiconductor device of the first aspect, p
Only in the middle region between the MOS region and the nMOS region , or in the middle
Since the inter-region contains atoms that hinder the diffusion of impurities at a higher concentration than other regions , p-type impurities and n-type impurities are mutually connected to the polysilicon gate electrode via the metal silicide layer while maintaining low resistance. Spreading is suppressed.

In the method of manufacturing a CMOS semiconductor device according to the second aspect, atoms that prevent diffusion of impurities can be introduced only into an intermediate region between the pMOS region and the nMOS region.

According to a third aspect of the present invention, there is provided a method of manufacturing a CMOS semiconductor device.
The intermediate region between the region and the nMOS region is higher than other regions.
The concentration can introduce atoms that prevent diffusion of impurities.

[0014]

Next, an embodiment of the present invention will be described. Embodiment 1 FIG. 1 is an explanatory view of a manufacturing process of a CMOS semiconductor device. FIG. 1A is a cross-sectional view. In FIG. 1B, the upper side is a plan view, and the lower side is a cross-sectional view.

FIG. 1A: p-well 5 on silicon substrate 7
After forming the n-well 6 and the n-well 6, an element region and an element isolation region are formed by the element isolation field oxide film 14. A gate oxide film 4 is formed in the element region by thermal oxidation. Next, a polysilicon film is deposited on the entire surface of the substrate 7 to a thickness of about 200 nm. By lithography, the polysilicon film in the pMOS transistor formation region is changed to a p-type polysilicon film 2, and similarly, the polysilicon film in the nMOS transistor formation region is changed to an n-type polysilicon film 3. Thereafter, a metal silicide film 1 is deposited to a thickness of 150 nm. Examples of the metal silicide include titanium, vanadium, chromium,
Examples include zirconium, niobium, molybdenum, hafnium, tantalum, tungsten, cobalt, and nickel silicide. Further, the silicide film 1 and the polysilicon film 2 are formed by lithography and reactive etching.
3 are patterned to form gate electrodes (p-type polysilicon gate electrode and n-type polysilicon gate electrode).

FIG. 1B: pMO by lithography
A resist pattern (9 indicates a resist) having an opening 9a in an intermediate region between the S region and the nMOS region is formed, and using this as a mask, nitrogen 8 is used as an atom for preventing mutual diffusion of impurities in a later heat treatment step. Using an ion implantation method, the injection amount is 1 × 10 ¹⁴ to 1 × at an acceleration voltage of 10 to 50 keV.
It is introduced as 10 ¹⁶ / cm ² . Note that the same effect can be obtained even if a step of introducing nitrogen as an atom that prevents mutual diffusion of impurities is performed before patterning the gate electrode. By these steps, nitrogen 8 as an atom that prevents mutual diffusion of impurities in a later heat treatment step is added to the intermediate region between the pMOS region and the nMOS region by 1 × 10 ¹⁴ to 1 × 10 ^16.
/ Cm ² can be introduced.

Embodiment 2 FIG. 2 is an explanatory view of a manufacturing process of a CMOS semiconductor device. FIG. 2A is a plan view, and in FIGS. 2B and 2C, the upper side is a plan view and the lower side is a cross-sectional view.

FIG. 2A: As in Embodiment 1, a polycide gate electrode having a p-type polysilicon gate electrode and an n-type polysilicon gate electrode is formed.

FIG. 2B: Thereafter, a pMOS transistor formation region is covered with a resist 10 by lithography to form an n-type diffusion region of the nMOS transistor.
Using this resist 10 as a mask, nitrogen 8 is ion-implanted as an atom that prevents mutual diffusion of impurities. The acceleration voltage in this ion implantation is 10 to 50 keV, and the implantation amount is 5
× 10 ^{13 to} 5 × 10 ¹⁵ / cm ² . Using this mask, an n-type impurity 12 for forming an n-type diffusion region is ion-implanted.

FIG. 2C: After the resist 10 is removed, an nMOS transistor forming region is covered with a resist 11 by lithography to form a p-type diffusion region of the pMOS transistor. Using this resist 11 as a mask, nitrogen 8 is ion-implanted as an atom that prevents mutual diffusion of impurities. The acceleration voltage in this ion implantation is 10
５０50 keV, injection amount is 5 × 10 ¹³ -5 × 10 ¹⁵ / cm
^{Assume 2} . Using this mask, a p-type impurity 13 for forming a p-type diffusion region is ion-implanted. By these steps, without increasing a new photolithography process, an intermediate region of the pMOS region and the nMOS region, the nitrogen 8 as atoms that prevents mutual diffusion of impurities in a later heat treatment step, 1 × 10
¹⁴ to 1 × 10 ¹⁶ / cm ² can be introduced.

[0021]

As is apparent from the above description, claim 1
In the CMOS semiconductor device described in the above, the pMOS region and the nMO
Other areas only in the intermediate area with the S area or in the intermediate area
A higher concentration than, because it contains atoms that prevent the diffusion of impurities, p-type and n-type impurities is suppressed from diffusing into each other polysilicon gate electrode through the metal silicide layer, as a result, low The change in the work function of the polysilicon gate electrode can be suppressed while the resistance remains, and the change in the threshold value can be suppressed. According to the method of manufacturing a CMOS semiconductor device of the second aspect, atoms that prevent the diffusion of impurities can be introduced only into the intermediate region between the pMOS region and the nMOS region. The semiconductor device according to claim 1 can be provided. C of claim 3
According to the method for manufacturing a MOS semiconductor device, the intermediate region between the pMOS region and the nMOS region can be formed without increasing the photolithography process.
In the semiconductor device according to the first aspect of the present invention, atoms that prevent impurity diffusion are introduced at a higher concentration than other regions .

[Brief description of the drawings]

FIG. 1 is a view illustrating a manufacturing process of a CMOS semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a view illustrating a manufacturing process of a CMOS semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a structure of a conventional CMOS semiconductor device.

FIG. 4 is a diagram illustrating a problem in the semiconductor device of FIG. 3;

[Explanation of symbols]

 Reference Signs List 1 metal silicide film 2 p-type polysilicon film 3 n-type polysilicon film 4 gate oxide film 5 p-well 6 n-well 7 silicon substrate 8 nitrogen atom 9, 10, 11 resist 9a opening 12 n-type impurity 13 p-type impurity 14 field Oxide film

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/336 H01L 21/8238 H01L 27/092 H01L 29/78

Claims (3)

(57) [Claims] In a CMOS semiconductor device having a p-type polycide gate electrode and an n-type polycide gate electrode , a pMOS region and nM in a polycide connecting the p-type polycide gate electrode and the n-type polycide gate electrode are provided.
Only the intermediate area with the OS area, or other areas in the intermediate area
A CMOS semiconductor device characterized by containing atoms that prevent diffusion of impurities at a higher concentration than a region . 2. The method of manufacturing a CMOS semiconductor device according to claim 1, wherein the pMO is formed after laminating a metal silicide.
A method for manufacturing a CMOS semiconductor device, comprising a step of introducing atoms that prevent diffusion of impurities using a resist pattern having an opening only in an intermediate region between an S region and an nMOS region as a mask. 3. The method of manufacturing a CMOS semiconductor device according to claim 1, wherein a resist pattern at the time of forming a p-type diffusion region of the pMOS region is formed by a pMOS region and an nMOS region.
Formed with an opening that also includes the intermediate area between
A step of introducing atoms that impede the diffusion of impurities using the strike pattern as a mask, and a step of forming a resist pattern for forming the n-type diffusion region of the nMOS region, the opening including the intermediate region.
And introducing atoms that prevent diffusion of impurities using the resist pattern as a mask.