JP3075565B2 - Image display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Industrial applications]

The present invention relates to a multi-scan image display device including a circuit for digitally generating a correction waveform for performing side pin correction and focus correction.

[0002]

[Prior art]

In recent years, in display devices such as computer terminals,
The display position and display size of the screen, and the deflection frequency of the video signal to be displayed are various. Therefore, 1
2. Description of the Related Art A versatile multi-scan display capable of supporting various video signals (video signals) in one display device has been used.

A conventional example of such a multi-scan type display is disclosed in Japanese Utility Model Laid-Open Publication No. 64-4491. In this type of prior art, a microcomputer is used to control a memory that previously stores display position and display size information of a screen for each video signal,
Optimal screen display position and display size information are read from the memory in accordance with the input video signal, and the deflection circuit is controlled based on the read information. Therefore, the operation of the microcomputer here is merely to control the reading of the memory.

[0004] Regardless of the multi-scan display, there is a display which has a digital memory in the display, reads out various types of image distortion correction data from the memory, and generates and generates an image distortion correction waveform signal. As this type of conventional waveform generator, there is a waveform generator described in Japanese Patent Application Laid-Open No. 64-12716.

In this device, the corrected waveform data stored in the memory in advance is read out at a timing synchronized with the horizontal and vertical synchronization signals, converted into an analog signal by D / A conversion, and smoothed by a low-pass filter to obtain a parabolic waveform. And the like to obtain an image distortion correction waveform signal.

[0006]

[Problems to be solved by the invention]

In the prior art as described in Japanese Utility Model Application Laid-Open No. 64-4491 described above, a microcomputer is operated so as to correspond to various input video signals, but the operation is simply to selectively read information held in a memory. However, it is difficult to say that the microcomputer fully exerts its inherent functions. In other words, if a microcomputer is used, a more convenient and more convenient deflection control circuit for a multi-scan display can be realized, but no consideration has been given to that point.

Further, in the prior art described in Japanese Patent Application Laid-Open No. 64-12716, a screen distortion correction waveform signal is generated by a distortion correction waveform generation circuit using a memory. No consideration is given to so-called multi-scan, which can deal with video signals with different frequencies and display timings.Therefore, memories that hold dedicated correction information corresponding to various video signals are required, which leads to economic savings. There was a problem that it could not be achieved.

The present invention has been made in view of the above-mentioned state of the art, and an object of the present invention is to provide an image display device capable of obtaining an appropriate correction waveform corresponding to a display specification. It is in.

[0009]

[Means for Solving the Problems]

In order to achieve the above object, an image display device according to the present invention includes a correction waveform creation unit that creates a correction waveform for correcting an image displayed on a screen based on an input video signal and a synchronization signal. In the image display device, the correction waveform generating means generates a correction waveform corresponding to the deflection frequency of the input video signal, and stores memory data for storing waveform data corresponding to a reference correction waveform. Reading means for reading waveform data from the memory means on the basis of a synchronization signal, a control circuit for outputting correction data for correcting the waveform data read by the reading means, and correction data from the control circuit. An arithmetic processing means for performing arithmetic processing on the waveform data read by the reading means and outputting the processed data; and converting an output signal of the arithmetic processing means into an analog signal. Serial and a D / A means for outputting a correction waveform, characterized in that the rewritable constituting said memory means output signal as a new waveform data of said processing means.

Further, the image display device according to the present invention includes a correction waveform generation unit that generates a correction waveform for correcting an image displayed on a screen based on an input video signal and a synchronization signal. A correction circuit for outputting correction data for correcting the shape of the correction waveform generated by the correction waveform generation means; and a reference correction signal obtained at a timing synchronized with the input synchronization signal. Arithmetic processing means for arithmetically processing the waveform data corresponding to the waveform and the correction data output from the control circuit and outputting the processed data; and D for converting the output signal of the arithmetic processing means into an analog signal and outputting the analog signal as the corrected waveform / A means.

The arithmetic processing means may be an adding means for adding the waveform data and the correction data. The correction waveform may be a parabolic waveform for side pin correction supplied to a deflection circuit for performing a deflection operation for displaying an image, and may be supplied to a deflection circuit for performing a deflection operation for displaying an image. Alternatively, a parabolic waveform for side pin correction may be used.

Further, the control circuit may be a CPU. Further, the waveform data corresponding to the reference correction waveform may be stored in a memory means, and the waveform data may be obtained by reading out the waveform data from the memory means in synchronization with the input synchronization signal.

[0013] The memory means may be an E ² PROM.

[0014]

[Action]

According to the above configuration, since the waveform data stored in the memory is configured to be rewritable, appropriate waveform data can be held in accordance with a change in display specifications and the like. A correct correction waveform can be obtained.

[0015]

【Example】

Hereinafter, an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, 100 is a synchronous deflection control circuit (xtal is a clock generation circuit) according to the present invention, 101 is a control circuit (hereinafter, referred to as CPU) composed of a microcomputer, and 102 is a CP.
An input port (1) circuit for interfacing with U101, 103 is a read-only memory (hereinafter, ROM), 104 is a readable / writable memory (hereinafter, RAM), 105 and 106 are input ports (2), and inputs Port (3) circuit, 107 is a synchronization detection circuit for detecting the frequency of the synchronization signal contained in the input video signal, 108 is unifying the polarity of the synchronization signal contained in the input video signal, and outputs the horizontal synchronization pulse during the vertical blanking period. This is a polarity unification / H-missing countermeasure circuit that corrects any missing.

Reference numeral 109 denotes a synchronization separation / H / V separation circuit that separates a synchronization signal from an input video signal (green G video signal) and further separates the synchronization signal into horizontal / vertical synchronization signals. Reference numerals 110, 111, and 114 denote output ports (0), In the circuits (1) and (2), when the input video signal is switched and the frequency of the synchronizing signal is changed, if the frequency is suddenly dealt with, the horizontal deflection circuit may be overloaded and the circuit element may be damaged. _FH slow-down circuit, which provides horizontal protection to prevent it, 113
Is a vertical phase circuit for adjusting the vertical phase of the image screen.

Reference numeral 115 denotes a waveform generation circuit that generates a parabolic waveform signal (a waveform that can correct side pin distortion or the like on a screen) synchronized with an input video signal. Reference numerals 116 and 117 denote digital-analog conversion (hereinafter, referred to as D / A conversion). ) Circuit, 118 is a sample-and-hold (hereinafter referred to as S / H) circuit, 119 is a low-pass filter (hereinafter referred to as LPF), and 120 to 137 are synchronous deflection control circuits 100
FIG. 2 shows input / output terminals connecting between the display device and another part of the display device (mainly, a deflection circuit).

In FIG. 1, a ROM 103, a RAM 104, input / output port circuits 102, 105, 106, 110, 111, 114, a waveform generation circuit 1
Numeral 15 controls the exchange of information among the address bus, the data bus and the control bus, and the timing control thereof. This operation is similar to that of a general microcomputer circuit.

A video signal (green G video signal) to which a synchronization signal added from an input terminal 124 is added is separated by a synchronization separation / H / V separation circuit 109.
As a result, the horizontal and vertical synchronizing signals are separated, and the separated synchronizing signals are input to the positive unification / H loss prevention circuit 108. The horizontal / vertical separation synchronization signal is also input to the circuit 108 from the input terminals 125 and 126. Here, input terminal 12
There are positive and negative sync signals input from 5,126, and a sync signal of a signal input from the input terminal 124 is one in which a horizontal sync signal is not inserted during a vertical retrace period (a missing signal). That occurred).

Therefore, the polarity unification / H loss countermeasure circuit 108 at the next stage unifies the synchronization signal polarities and compensates for the horizontal synchronization signal loss.

In this way, the synchronization signal unified to either the positive or negative polarity and reproduced in a perfect form is supplied to the synchronization detection circuit 107.
And the frequency of the horizontal and vertical synchronization signals, etc.
Information necessary for identifying screen display specifications such as the screen size and screen position of the input video signal is detected. The frequency information (HD, VD) of the horizontal / vertical synchronizing signal and the synchronizing signal polarity information from the polarity unification / H loss countermeasure circuit 108 thus obtained are given to the CPU 101 via the input port (3) circuit 106. .

Based on the information, the CPU 101 recognizes what kind of screen display specification the video signal currently given to the display device is, and determines a screen size suitable for the video signal. Reading the adjustment information for specifying the position and the like from the ROM 103 to perform such adjustment,
After being input to the D / A conversion circuit 116 from the output port (2) circuit 114 and converted into an analog amount, the analog amount is supplied to the deflection circuit of the display device to adjust the screen.

With respect to the vertical position of the screen, the position information read from the ROM 103 is supplied to the vertical phase circuit 113 via the output port (1) circuit 111, and the vertical synchronization signal V is delayed based on the position information to VD To the vertical deflection circuit to perform vertical phase adjustment.

Further, the CPU 101 sends a control signal to the waveform generation circuit 115 based on the above-described recognition result of the video signal. The waveform generating circuit 115 creates a parabolic waveform signal for dynamic focus and side pin correction in accordance with the video signal, passes through a D / A conversion circuit 117, an S / H circuit 118 for deglitch, and an LPF 119 for waveform equalization. Get the waves. These correction waveform signals are respectively supplied to a focus circuit and a horizontal deflection circuit, and optimal adjustment is performed on a screen for each video signal.

[0026] f _H slowdown circuit 112 that operates to protect the horizontal deflection circuit is touched slightly earlier, when the input video signal is switched from the higher horizontal frequency when referred specifically The operation is performed when switching to a lower one. This is because changes towards suddenly lower the higher horizontal frequency, there is a risk of loss in the horizontal deflection circuit, not shown in FIG. 1 is increased, damage the circuitry, f _H slowdown circuit 112 Thus, the frequency of the horizontal synchronizing signal applied to the horizontal deflection circuit is gradually lowered, and finally, the horizontal synchronization signal matches the horizontal frequency after switching.

The control of f _H slowdown circuit 112 is performed by providing control information from the CPU101 through the output port (0) circuit 110 to f _H slowdown circuit 112. Further, during the operation of the f _H slowdown circuit 112 lowers its gain sends generates a video image mute pulse to the video amplifier circuit, so as not to display a screen disturbances during operation.

The above is a case where the CPU 101 recognizes an input video signal and automatically performs adjustment control. However, when there is a video signal having a screen display specification that cannot be recognized by the CPU 101, When the user of the display device wants to make an arbitrary adjustment, manual setting is possible using the input terminals 121 to 123.

At this time, the input terminal is set by switches attached to the display device main body (not shown in FIG. 1).
The setting information is performed through 121, 122, and 123, and the setting information is taken into the CPU 101 via the input port (2) circuit 105 and subjected to each adjustment control process.

In addition, factory adjustment data is input from the input terminal 120, so that the factory adjustment of the display device can be easily automated.

Therefore, according to the present embodiment, various kinds of adjustment control according to the screen display specification of the input video signal of the multi-scan display device can be easily and automatically performed, and a parabola waveform used for screen distortion correction and the like can be obtained. Since a function such as a generation function and a horizontal protection operation are also provided, the usability is significantly improved.

FIG. 2 is a block diagram showing peripheral circuits mainly including a deflection circuit around the display device which receives a control signal from the synchronous deflection control circuit 100 shown in FIG.

In FIG. 2, reference numeral 201 denotes a horizontal phase control circuit (H.phase),
202 is horizontal AFC circuit, 203 is horizontal oscillation circuit (H.VCO), 204
Is a horizontal pre-drive circuit (H, PRE-DRIVE), 205 is a horizontal drive circuit (H.DRIVE), 206 is a horizontal deflection output circuit, 20
7 is a high voltage generation circuit, 208 is a vertical oscillation circuit (V.OSC), 209 is a vertical drive circuit (V.DRIVE), 210 is a vertical deflection output circuit, 211 is an amplification circuit, 212 is a video amplification circuit, 213 is a cathode ray tube , 214 is a user adjustment circuit, 215 is a video signal input terminal, 21
Reference numeral 6 denotes a horizontal deflection coil, 217 denotes a vertical deflection coil, and those having the same numbers as those in FIG. 1 have the same functions. The circuit operation of FIG. 2 is as follows.

The horizontal synchronization signal HD output from the synchronous deflection control circuit 100 shown in FIG.
The horizontal phase adjustment signal via the output terminal 131 from the synchronous deflection control circuit 100 is adjusted so that the horizontal phase of the image displayed on the cathode ray tube 213 is adjusted so that the center of the screen of the cathode ray tube 213 matches the center of the image. Controlled by H.phase.

After performing the phase control in this manner, the synchronization signal is output to the horizontal AFC circuit 202, the horizontal oscillation circuit 203, the horizontal pre-drive circuit 204, and the horizontal drive circuit 20 similar to those in a normal display device.
After passing through 5, the signal is supplied to the horizontal deflection output circuit 206. The horizontal deflection output circuit 206 has an output terminal 13 from the synchronous deflection control circuit 100.
Horizontal display size adjustment signal HSIZE via 3 and output terminal
A horizontal screen center adjustment signal HCENT via the output terminal 136 and a side pin correction signal via the output terminal 136 are used to perform adjustment control so as to optimize the display screen, and output a deflection current to the horizontal deflection coil 216.

The high-voltage control signal output from the horizontal deflection output circuit 206 is supplied to a high-voltage generation circuit 207, which generates a high-voltage for the cathode ray tube 213 and also outputs a horizontal return signal to the horizontal AFC circuit 202.
Give HFB.

On the other hand, the vertical synchronization signal VD output from the synchronous deflection control circuit 100 is supplied to the vertical oscillation circuit 208 via the output terminal 128, and the circuit oscillates in synchronism with the synchronization signal VD. The oscillation output is supplied to a vertical deflection output circuit 210 via a vertical drive circuit 209. In the vertical deflection output circuit 210, a vertical display size adjustment signal VSIZE and a vertical screen center adjustment signal VC via output terminals 132 and 129 from the synchronous deflection control circuit 100 are output.
Adjustment is performed by the ENT so as to obtain an optimum display screen, and a vertical deflection current is output to the vertical deflection coil 217.

The horizontal and vertical parabolic wave signals for dynamic focus output from the output terminals 134 and 135 are input to the amplifier circuit 211 and are appropriately amplified, and then supplied to the focus electrode of the cathode ray tube 213 as a focus voltage.

Next, the video mute signal output from the output terminal 137 is output when the synchronous deflection control circuit 100 detects that the horizontal synchronization signal frequency input to the display device has been switched, and the video amplification circuit 212 The video blanking circuit operates within the circuit, and display is not performed on the cathode ray tube 213 for a predetermined period after the switching.

The user adjustment circuit 214 adjusts the image displayed on the cathode ray tube 213 to an optimal state when the image signal input to the display device is difficult to be identified by the CPU 101 and is unknown. Adjustment circuit 21
Adjust using the setting switches in 4. This adjustment data is supplied to the synchronous deflection control circuit 100 via the input terminals 121, 122 and 123.
And registered in the memory in the same circuit 100,
Next, when the same signal is input, an optimal image can be obtained without adjustment.

Further, adjustment data at the time of shipment from the factory is input from the factory adjustment data input terminal 120, and initial adjustment of signals for dynamic focus and side pin correction is performed.

FIG. 3 shows a circuit 108 for unifying the polarity and preventing missing H in FIG.
FIG. 3 is a block diagram showing details of a polarity unifying circuit portion in FIG.

In FIG. 3, 302 and 303 are D flip-flop circuits, 30
4 is an OR circuit, 305 and 308 are counter circuits, 306 and 30
9 is a latch circuit, 307 and 315 are inverters, 310 and
313 is a comparator circuit, 311 and 312 are bit shift circuits for shifting bits of input data by n bits (n: natural number), 314 is an RS flip-flop circuit, and 316 is a switch circuit (SW).

The operation of the circuit of FIG. 3 will be described with reference to the operation explanatory diagram of FIG. In FIG. 3, the input horizontal synchronizing signal Hsync is differentiated by a differentiating circuit including a D flip-flop circuit 302 and 303 and an OR circuit 304 by one clock width of the clock arriving from the CPU 101. A pulse generated by differentiating in the first falling part and a pulse generated by differentiating in the next falling part one cycle later are given to the counter (1) circuit 305, and the pulse is generated over one cycle. The clock is counted, and the counted value is latched by the latch (1) circuit 306 as the cycle of the horizontal synchronization signal.

For example, if it is assumed that a positive synchronization signal whose period data is represented by a binary number “1000” is input, the counter (2) circuit 308 generates a clock with a positive portion of the input synchronization signal. Is performed and the value is latched (2).
The circuit 309 holds. Assuming that the clock count value in the positive portion of the input synchronization signal is '0001', this data becomes the A input of the comparator (1) circuit 310 and (2) circuit 313.

Further, the period data “1000” latched by the latch (1) circuit 306 is shifted one bit lower by the bit shift (1) circuit 311 and the (2) circuit 312, respectively, and the two-minute period data Shall be set to 1.
The respective outputs of this bit shift circuit become "0100" and become the B inputs of the comparators (1) and (2) circuits 310 and 313.

The output of the comparator (1) circuit 310 is high when the condition of (A input) <(B input) is satisfied, and the output of the comparator (2) circuit 313 is high under the condition of (A input)> (B input). Is set to a high level.

Therefore, when the polarity of the synchronization signal is positive, the input condition is A <
Since the signal becomes B, the set terminal of the RS flip-flop circuit 314 goes high, and the output goes high.
Conversely, when the synchronization signal polarity is negative, the latch (2) circuit 309
Becomes '0111', and the input condition of the comparator (2) circuit 313 satisfies A> B. Therefore, the RS flip-flop circuit 314 is reset, and the output is set to a low level. The above circuit operation is shown in FIG.

Therefore, the output of the RS flip-flop circuit 314 becomes a polarity determination signal, and the switch circuit 316 is controlled by this signal. When the polarity is positive, the switch circuit 316 passes the input synchronization signal as it is.
After 315, the output is unified to positive polarity.

The operation of the polarity unifying circuit 301 has been described above. In FIG. 3, the case of inputting the horizontal synchronizing signal has been described. However, even when the vertical synchronizing signal is input, it is possible to operate with exactly the same circuit configuration. . In this case, in FIG. 3, the horizontal synchronizing signal is not the vertical synchronizing signal and the clock is not from the CPU 101, but is actually replaced by the horizontal synchronizing signal and the period measurement operation of the vertical synchronizing signal is performed.

FIG. 5 shows another specific example of the polarity unification circuit shown in FIG.
It is a block diagram shown as. In the figure, 501 and 504
Is a counter circuit, 502 and 505 are latch circuits, 503 is a comparator circuit, 506 is an inverter, and 507 is a switch circuit.

In the operation shown in the figure, the counter (A) circuit 501 and the latch (A) circuit 502 measure and hold the positive period of the input synchronization signal Hsync, while the counter (B) circuit 504 and the latch (B) The negative period of the synchronizing signal Hsync is measured and held in the portion constituted by the circuit 505.

The held data obtained in this way is input to the comparator circuit 503 and compared with which of the positive and negative periods is longer. If the positive period of the synchronization signal is longer, it is determined that the synchronization signal is a negative synchronization signal. The output goes low. If the negative period is long, it is determined to be a positive synchronization signal, and the comparator circuit 503 outputs a high level.

The switch circuit 507 is controlled by the polarity discrimination signal. When the polarity is positive, an input synchronization signal is selected. When the polarity is negative, a synchronization signal inverted through an inverter 506 is selected. More output.

Also in the case of FIG. 5, the vertical synchronization signal can be handled as it is as the input synchronization signal. In this case, the horizontal synchronization signal is used as the clock input so that the number of bits of the counter circuit and the like is not carelessly increased.

[0056] FIG. 6 is a block diagram showing details of f _H slowdown circuit 112 shown in FIG. In the figure, 601 is a counter circuit, 602
Denotes a shift register circuit, 603 denotes an RS flip-flop circuit, and 604 denotes a selector circuit.

In FIG. 6, when the display device is in a steady state displaying a video signal, the selector circuit 604 is turned off by the video mute signal from the CPU 101, and the selector circuit 604 receives the horizontal signal coming from the polarity unification / H loss prevention circuit 108. Select the synchronization signal H.

Next, when the CPU 101 outputs that the video signal has been switched and the horizontal frequency has been switched from higher to lower, the video mute signal is turned on, and the sector circuit 604 operates as the R-channel.
The output of the S flip-flop circuit 603 is selected.

At this time, if the horizontal period before the signal switching is n clock periods and the horizontal period after the switching is m clock periods,
The load data from the CPU 101 is controlled so as to increase by one count so that the carry output of the counter circuit 601 changes from a state where the carry output is output at n clocks to a state where the carry output is output at m clocks.

The carry output is delayed by a few clocks by the shift register circuit 602, and the carry output is directly input to the set terminal of the RS flip-flop circuit 603 and the reset terminal, and an appropriate pulse width is added. Then, when the carry output reaches the period of the m clock period, the video mute signal is turned off and stopped, and the polarity unification / H loss prevention circuit 10 is returned again.
Select output H of 8.

[0061] Figure 11 is an explanatory diagram for explaining the effect of the operation the protection of the horizontal deflection circuit according to f _H slowdown circuit 112 in FIG. 6.

FIG. 11A is a circuit diagram showing a general horizontal output circuit, and FIGS. 11B to 11D show the state of each part of the circuit shown in FIG. 11A.

Now, the frequency of the horizontal deflection pulse input in FIG.
f _H is the changed at time t ₁ from the high frequency f _H1 to the low frequency f _H2 as shown in FIG. 11 (b). If the horizontal deflection frequency f _H switched suddenly like a solid line in FIG. (B), the collector voltage V _cp of the horizontal output transistor T _rH shown in FIG. (A) is seen in FIG. (C) V
_The transition is made from _cp1 to _Vcp2 while showing transient characteristics as shown by the solid line.

At this time, although the collector voltage temporarily reaches V _cpH higher than V _{cp1, the} power supply voltage supplied to the horizontal output circuit (a) is changed from E _{B1 to} E _B2 as shown in FIG. It changes smoothly. For this reason, the loss in the horizontal output transistor _TrH may increase and may be damaged.

Therefore, the f _H slow down circuit 112 shown in FIG.
When the horizontal deflection frequency _switches from _fH1 to fH2,
If so gradually lowering the frequency, as shown by a dotted line in FIG. 11 (b), as seen in the collector voltage V _cp also FIG (c), gradually by the dotted line path from V _cp1 to V _cp2 Therefore, the horizontal output circuit can stably operate without increasing the loss of the horizontal output transistor _TrH .

FIG. 7 is a block diagram showing details of the waveform generation circuit 115 shown in FIG. In FIG. 7, reference numeral 701 denotes an HPLL circuit (faced lock loop circuit) for generating a clock pulse synchronized with the horizontal synchronization signal H; 702, an address generation circuit; 703, an output port;
Is a writable and erasable read-only memory E ² PROM, 705
Reference numerals 706 and 706 denote tristate buffer circuits, 707 denotes a readable / writable memory RAM, and 708 denotes an addition circuit.

The circuit operation of FIG. 7 will be described with reference to the operation conceptual diagram of FIG. The horizontal synchronization signal H sent from the polarity unification / H loss countermeasure circuit 108 is input to the HPLL circuit 701 and generates a clock pulse synchronized with the horizontal synchronization signal regardless of the horizontal synchronization frequency.

Here, the dotted line control signal BR input to the HPLL circuit 701
When the range of the horizontal synchronization frequency input by the signal obtained from the CPU 101 is wide, the constant inside the HPLL circuit 701 is switched by this control signal so that a clock pulse synchronized with the input synchronization signal is always generated stably. .

Next, the clock pulse thus generated is applied to an address generation circuit 702 to generate an address for driving a memory circuit. In an initial state of the waveform generation circuit 115, basic parabola waveform data is stored in the E ² PROM 704 in advance, and data is sequentially read out corresponding to each address. Here, since the clock pulse is always synchronized with the input synchronization signal as described above, the generated address signal is also synchronized with the synchronization signal. Therefore, the read-out waveform data also has a multi-frequency compatible circuit configuration that can always correspond to the synchronization signal regardless of the synchronization signal frequency.

As described above, the waveform data read from the E ² PROM 704 passes through the tristate buffer circuit 705 and is once written into the RAM 707, and also passes through the addition circuit 708 to the D / A conversion circuit 117 shown in FIG. Supplied.

At this time, the added data output from the output port 703 =
It is '0' to prevent data addition. The above state corresponds to the E ² PROM data waveform shown in FIG. In the figure, E ² always corresponds to the horizontal synchronization signal H.
The data (circled in the figure) of the PROM 704 is read to form a parabolic waveform, and there is no need to adjust the parabolic waveform even if the horizontal deflection frequency changes.

Next, in an actual display device, it is rare that the waveform data read from the E ² PROM 704 can be used as it is due to a variation in a cathode ray tube or the like, and thus requires adjustment. In this case, the control signal from CPU 101 is output port 703 as shown in FIG.
The data is extracted as addition data (CPU data) as shown in FIG. The adjustment is not performed for each address of the E ² PROM 704, but is performed at intervals obtained by appropriately dividing one cycle. This division processing and the like are performed by the CPU 101.

The added data (CPU data) is output at appropriate intervals as shown in FIG. 8C, and the data processed by the adding circuit 708 is as shown in FIG. 8D. ,
The adjusted waveform data is obtained.

This waveform data is supplied again to the E ² PROM 704 via the tri-state buffer 706, and the held data is rewritten. Control of the memory circuit and the like operates according to a control signal from the CPU 101.

FIG. 7 shows the horizontal direction of the screen, but the same configuration can be applied to the vertical direction. In this case, a vertical synchronization signal is input instead of the horizontal synchronization signal.

FIG. 9 is a block diagram showing another specific example of the waveform generating circuit as 115 ′. In the figure, 901 is an input / output port, 902
Is the CPU as the second microcomputer circuit (2)
A circuit, 903 is an E ² PROM, 904 is a RAM, and 905 is an output port. In FIG. 9, waveform data is created by using the second CPU 902.

Based on a control signal from the CPU 101 in the synchronous deflection control circuit 100, the CPU 2 circuit 902 reads data from the E ² PROM 903 storing the basic waveform data, and performs an arithmetic process so as to obtain optimal waveform data. Store in RAM904.

The arithmetic processing performed here performs multi-frequency corresponding processing based on the synchronization frequency data included in the control signal of the CPU 101,
Waveform data corresponding to the input synchronization signal is created.

The stored data is taken out via the output port 905 and written into the E ² PROM 903 again.

According to the configuration of FIG. 9, the CPU 101 is used for input / output of other adjustment data of the display device, and the CPU (2) circuit 902 is applied for arithmetic processing such as waveform processing. Can be performed. FIG. 9 is applicable to both the horizontal and vertical directions of the screen.

FIG. 10 is a block diagram showing another embodiment of the present invention as 100A. In FIG. 10, reference numeral 10A denotes a so-called one-chip microcomputer circuit MPU, which internally includes a memory circuit, a counter circuit, a timer circuit, and the like. Otherwise, the same reference numerals as those in FIG. 1 indicate the same functions.

In FIG. 10, the RAM 104, the synchronization detection circuit 107, and the vertical phase circuit 113 in FIG. 1 are incorporated in the MPU 10A.
It is controlled by a Souto method. In FIG. 10, the synchronous deflection control circuit 100 can be operated with a simpler configuration.

FIG. 12 is a block diagram showing still another embodiment of the present invention. In FIG. 12, 100B is a synchronous deflection control circuit (xtal is a clock generation circuit) according to the present invention, 101 is a control circuit (hereinafter, referred to as CPU) including a microcomputer, 103 is a read-only memory (hereinafter, ROM), 104 Denotes a readable / writable memory (hereinafter, RAM), and 105 and 106 denote input port (2) and input port (3) circuits.

Reference numeral 111 denotes a synchronization signal processing / frequency counter, which counts the frequency of the synchronization signal included in the input video signal, detects coincidence, and detects free running (a state in which the synchronization signal suddenly disappears is called free running). Therefore, if a horizontal sync pulse is missing during a vertical blanking period (a video signal indicating that there is no horizontal sync signal during a vertical sync signal in a computer graphic terminal or the like exists), it is corrected and freed. Synchronous signal processing and frequency counter that generates a pulse that replaces the horizontal synchronous signal when a run is detected so that no burden is placed on the deflection circuit, and performs all processing of the synchronous signal included in the input video signal, such as unifying the synchronous signal polarity. Circuit.

[0085] 109 separates from the synchronizing signal input video signal (video signal of green G), synchronous separation · H / V separation circuit further separated into a horizontal / vertical synchronization signal, 1112 f _H change detection · f _H Slow In a down circuit, if it is detected that the frequency of the synchronization signal has changed due to the switching of the input video signal, and if it is attempted to deal with it suddenly, the horizontal deflection circuit may be overloaded and the circuit elements may be damaged. since, furthermore, f _H change detection · f _H slowdown circuit to match the synchronization signal of the phase performs horizontal protection to prevent it.

Reference numerals 110, 111 and 114 denote output port (0), (1) and (2) circuits, and 116 denotes a digital-analog conversion (hereinafter referred to as D
/ A conversion) circuit, 121 to 133 are synchronous deflection control circuits 100B
FIG. 2 shows input / output terminals connecting between the display device and another part of the display device (mainly, a deflection circuit).

In FIG. 12, the ROM 103, the RAM 104, and the input / output port circuits 105, 106, 110, 111, and 114 mainly exchange information with the CPU 101 via an address bus, a data bus, and a control bus, and control their timing. This operation is similar to that of a temporary microcomputer circuit.

The video signal (green G video signal) to which the synchronization signal added from the input terminal 124 is added is separated by the synchronization separation / H / V separation circuit 109.
, The horizontal and vertical synchronizing signals are separated, and the separated synchronizing signals are synchronized signal processing / frequency counter circuit 1111
Is input to The horizontal / vertical sync separation signal is also input to the circuit 1111 from the input terminals 125 and 126.

Here, the synchronization signal input from the input terminals 125 and 126 may have a positive polarity or a negative polarity, and a horizontal synchronization signal is inserted into the synchronization signal of the signal input from the input terminal 124 during the vertical retrace period. There are some that have not been done (ones with missing).

Therefore, the synchronization signal processing / frequency counter circuit 11 in the next stage
By 11, the polarity of the synchronization signal is unified, the horizontal synchronization signal is omitted, the pulse that replaces the synchronization signal during free-run is created, and the completely regenerated synchronization signal is
Information required for identifying the screen display specifications such as the screen size and screen position of the input video signal, such as the frequency of the horizontal / vertical synchronization signal, is detected. The synchronization signal polarity information is supplied to the input port (3) circuit 106. After that, it is given to the CPU 101.

The CPU 101 recognizes the video signal currently given to the display device as a video signal having what kind of screen display specification based on the information, and determines a screen signal conforming to the video signal. After reading adjustment information for specifying such size and position from the ROM 103 and inputting it from the output port (2) circuit 114 to the D / A conversion circuit 116 and converting it into an analog amount, It is supplied to the deflection circuit of the display device to adjust the screen.

Regarding the vertical position of the screen, the position information read from the ROM 103 is supplied to the vertical phase circuit 113 via the output port (1) circuit 111, and the vertical synchronization signal VD (bar) is delayed based on the position information. Then, the resulting signals are supplied to the vertical deflection circuit as VD to perform vertical phase adjustment.

The f _H change detection / operation that operates to protect the horizontal deflection circuit
f _H slowdown circuit 1112 is previously mentioned many times, when the input video signal is switched, the operation when Specifically when the horizontal frequency is switched high to lower from the side.

[0094] This is because when the change towards suddenly lower the higher horizontal frequency, and increased loss in the horizontal deflection circuit, not shown in FIG. 12, because it may damage the circuit, f _H change detection · f _H
The slow down circuit 109 gradually lowers the horizontal synchronizing signal frequency applied to the horizontal deflection circuit, and finally matches the horizontal frequency after switching.

[0095] control of the f _H change detection · f _H slow-down circuit 1112 CPU101
Thus, the control information is passed through the output port (0) circuit 110 and f
It carried out by giving to _H change detection · f _H slowdown circuit 1112. Further, during the operation of the f _H change detection · f _H slowdown circuit 1112 sends the video image mute pulse to the video amplifier circuit, so that the circuit 1112 does not display the screen disturbances during operation.

The above is a case where the CPU 101 recognizes an input video signal and automatically performs adjustment control. However, there is a case where a video signal having a screen display specification that cannot be recognized by the CPU 101 exists. When the user of the display device wants to make an arbitrary adjustment, manual setting is possible using the input terminals 121 to 123.

At this time, the input terminal is set by switches attached to the display device main body (not shown in FIG. 12).
The setting information is performed through 121, 122, and 123, and the setting information is taken into the CPU 101 via the input port (2) circuit 105 and subjected to each adjustment control process.

Therefore, according to the present embodiment, various adjustment controls according to the screen display specifications of the input video signal of the multi-scan display device can be easily and automatically performed, and a function such as a horizontal protection operation is provided. Therefore, the usability is significantly improved.

FIG. 13 is a block diagram showing peripheral circuits mainly including a deflection circuit around the display device which receives the control signal from the synchronous deflection control circuit 100B shown in FIG.

In FIG. 13, reference numeral 201 denotes a horizontal phase control circuit (H.phase),
202 is horizontal AFC circuit, 203 is horizontal oscillation circuit (H.VCO), 204
Is a horizontal pre-drive circuit (H.PRE-DRIVE), 205 is a horizontal drive circuit (H.DRIVE), 206 is a horizontal deflection output circuit, 20
7 is a high voltage generation circuit, 208 is a vertical oscillation circuit (V.OSC), 209 is a vertical drive circuit (V.DRIVE), 210 is a vertical deflection output circuit, 212 is a video amplification circuit, 213 is a cathode ray tube, and 214 is user adjustment A circuit, 215 is a video signal input terminal, 216 is a horizontal deflection coil, 217 is a vertical deflection coil, and those having the same numbers as those in FIG. 12 show the same functions. The circuit operation of FIG. 13 is as follows.

The horizontal synchronization signal HD output from the synchronous deflection control circuit 100B shown in FIG.
The output terminal 131 from the synchronous deflection control circuit 100B is supplied to the cathode ray tube 213 so that the horizontal phase of the image displayed on the cathode ray tube 213 is adjusted so that the center of the screen of the cathode ray tube 213 matches the center of the image.
Is controlled by a horizontal phase adjustment signal H.phase via

After performing the phase control as described above, the synchronization signal is output to the horizontal AFC circuit 202, the horizontal oscillation circuit 203, the horizontal pre-drive circuit 204, and the horizontal drive circuit 20 similar to those of a normal display device.
After passing through 5, the signal is supplied to the horizontal deflection output circuit 206. The horizontal deflection output circuit 206 has an output terminal 1 from the synchronous deflection output circuit 100B.
The horizontal display size adjustment signal HSIZE via the output terminal 130 and the horizontal screen sensor adjustment signal HCENT via the output terminal 130 are controlled so as to optimize the display screen, and output a deflection current to the horizontal deflection coil 216.

The high voltage control signal output from the horizontal deflection output circuit 206 is supplied to a high voltage generation circuit 207 to generate a high voltage for the cathode ray tube 213 and to output a horizontal return signal to the horizontal AFC circuit 202.
Give HFB.

On the other hand, the vertical synchronization signal VD output from the synchronous deflection control circuit 100B is supplied to the vertical oscillation circuit 208 via the output terminal 128, and the circuit oscillates in synchronism with the synchronization signal VD. The oscillation output is supplied to a vertical deflection output circuit 210 via a vertical drive circuit 209. In the vertical deflection output circuit 210, adjustment is performed so as to obtain an optimum display screen by a vertical display size adjustment signal VSIZE via the output terminals 132 and 129 from the synchronous deflection control circuit 100B, and a vertical screen center adjustment signal VCENT.
A vertical deflection current is output to the vertical deflection coil 217.

Next, the video mute signal output from the output terminal 134 is output when the synchronous deflection control circuit 100B detects that the horizontal synchronization signal frequency input to the display device has been switched, and the video amplification circuit 212 The video blanking circuit operates within the circuit, and display is not performed on the cathode ray tube 213 for a predetermined period after the switching.

The user adjustment circuit 214 adjusts the image displayed on the cathode ray tube 213 to an optimal state when the video signal input to the display device is difficult to identify by the CPU 101 and is unknown. It is a circuit for performing, an adjustment circuit
Adjust with the setting switches in 214.

The adjustment data is supplied to the synchronous deflection control circuit 100B via the input terminals 121, 122, and 123 and registered in the memory in the circuit 100B. Therefore, when the same signal is input next time, the optimum image is adjusted without adjustment. Is obtained.

FIG. 14 is a block diagram showing details of the synchronization signal processing / frequency counter circuit 1111 in FIG.

In FIG. 14, 1301 is a differentiating circuit, 1302 is an OR circuit, 1303 is a free-run detecting circuit, 1304 is a counter circuit, and 1305 and 1307.
Is a latch (A) and (B) circuit, 1306 is a match detection circuit, 1308 is a magnitude comparison circuit, 1309 and 1312 are selector (A) and (B) circuits, 1310 is an inverter, 1311 is a pulse width generation circuit, and 1313 is EOR circuit.

The operation of the circuit shown in FIG. 14 will be described. The horizontal synchronizing signal Hsync input in FIG. 14 is differentiated by the differentiating circuit 1301 by one clock width of the clock whose falling part arrives from the CPU 101. A pulse generated by differentiating at the first falling part and a pulse generated by differentiating at the next falling part one cycle later are given to the counter circuit 304 via the selector (A) circuit 1309, and The clock is counted over one period.

In the latch (A) circuit 1305 of the synchronization signal processing circuit, the count value is latched as the cycle of the horizontal synchronization signal, and in the latch (B) circuit 1307, the latch is performed at the falling edge, and the horizontal synchronization signal has a positive portion. Is latched.

In the magnitude comparison circuit 1308 for determining the polarity, the cycle data latched by the latch (A) circuit 1305 as the cycle of the horizontal synchronizing signal is shifted down by one bit by a bit shift, that is, two minutes. Is compared with the clock count value of the positive portion of the input synchronization signal latched by the latch (B) circuit 1307. In other words, it identifies which of the positive and negative periods is longer.

Assuming that the bit-shifted periodic data of the latch (A) circuit 1305 is T1 and the count data of the latch (B) circuit 1307 is T2, the synchronization signal polarity is positive under the condition of (T1) <(T2). The magnitude comparison circuit 1308 outputs a high level, and (T1)
Under the condition of> (T2), the synchronization signal polarity is negative and a low level is output as a polarity determination signal.

Further, in the EOR circuit 1313, the polarity of the horizontal synchronization signal is unified by the polarity discrimination signal, and the selector (B) circuit
Output via 1312.

On the other hand, in the free-run detection circuit 1303, the counter circuit 13
When the count data output from 04 exceeds a certain constant, a low-level pulse is generated and supplied to the OR circuit 1302. In addition, the vertical synchronizing signal is an OR circuit
The signal is supplied to the selector 1302 and output to the selector (A) and (B) circuits 1309 and 1312 as a select signal.

The selector (A) circuit 1309 normally selects a pulse output from the differentiating circuit 1301, and is controlled by a low-level select signal supplied from the OR circuit 1302. ) The previous cycle data held in the circuit 1305 and the current count data being counted by the counter circuit 1304 are compared, and a low level is output when they do not match, and a high level is output when they match,
A signal inverted through the inverter circuit 1310 is selected.
In this way, a pulse is generated at the time of a free run, and compensation for a missing horizontal synchronizing signal is performed.

The signal selected by the selector (A) circuit 1309 is supplied to a pulse width generation circuit 1311, which outputs a pulse having one clock width of a clock arriving from the CPU 101 with a pulse width as a horizontal synchronization signal. .

The selector (B) circuit 1312 normally selects the horizontal synchronizing signal from the EOR circuit 1313 with uniform polarity. The horizontal synchronizing signal generated by the pulse width generating circuit 1311 is controlled by the low level select signal. Select the selector (B) circuit
The 1312 always outputs a horizontal synchronization signal reproduced in a safe form.

The operation of the synchronization signal processing / frequency counter circuit 1111 has been described above. In FIG. 14, the case where the horizontal synchronization signal is input has been described. Of course, the vertical synchronization signal can be operated with the completely same circuit configuration. In this case, the input of the vertical synchronizing signal for eliminating H loss in FIG. 14 is eliminated, the horizontal synchronizing signal is not the vertical synchronizing signal, and the clock is not actually from the CPU 101, but is actually replaced by the horizontal synchronizing signal and the vertical synchronizing signal is replaced. Performs signal cycle measurement operation.

FIG. 15 shows the f _H change detection / f _H slowdown circuit shown in FIG.
FIG. 11 is a block diagram showing details of 1112.

In FIG. 15, reference numeral 1401 denotes a decoder circuit, 1402 and 1403, 1404
Is a latch (1) and (2) and (3) circuits, 1405 is an addition circuit, 1406 and 1408 are magnitude comparison (1) and (2) circuits, 1407 is a subtraction circuit, and 1409 and 1410 are RS flip-flop circuits , 1411 and 1415, 1416, and 1418 are selector (1) and (2), (3), and (4) circuits, 1412 is a slowdown counter circuit, 1413 and 1414 are D flip-flop circuits, 1417 is a pulse width setting circuit, 1419 is an inverter circuit, 1420 and 1421 are OR circuits, 1422 is an AND circuit, 142
3 is a phase comparison circuit.

Referring to FIG. 15, the operation of the _fH change detection circuit including the upper half (the circuit portion S hatched inside) will be described.

The microcomputer address sent from the CPU 101 is a decoder
When the microcomputer address matches the address preliminarily assigned to the latch (1) circuit 1402 and the latch (2) circuit 1403 and further to the latch (3) circuit 1404, the latch circuit matches. Outputs a latch clock, and holds the microcomputer data sent from the CPU 101.

Here, the latch (1) circuit 1402 and the (2) circuit 1403
Are usually the same value, as shown in FIG.
This is data related to the count error included in the TH data indicating the cycle of the horizontal synchronization signal obtained by the synchronization signal processing / frequency counting circuit 1111. That is, the TH data for a certain horizontal synchronization signal is (Na) ≦ TH data ≦ (N +
a), (N, a: natural number), where a is the count error. Usually, the value of a is about 1 or 2 in decimal. The latch circuit (1) 1402 and the (2) circuit 1403 hold 2a as data.

Next, the value held in the latch (1) circuit 1402 is added to the TH data by the addition circuit 1405, and the cycle count value of the horizontal synchronization signal obtained by the synchronization signal processing / frequency counting circuit 1111 in FIG. H count data HC (range of H count data = 0 to N + a) is compared by magnitude comparison (1) circuit 1406,
If TH data <H count data, it is detected that the frequency which is the reciprocal of the cycle of the input horizontal synchronization signal has dropped.

Here, the addition operation is performed by the magnitude comparison (1) circuit 1406 by the count error a even when there is a horizontal synchronization signal such that TH data = Na and H count data = N + a. In order not to make a mistake, data 2a (double a) is given to the latch (1) circuit 1402, and frequency drop detection is performed every horizontal cycle.

That is, when TH data = N−a and H count data = N
+ A, the comparison result is TH data <H count data. However, since a is an error, N and N
Thus, it is correct to determine that TH data is equal to H count data. Therefore, since the data 2a is latched in the latch (1) circuit 1402 and added to the TH data, the TH data becomes (N−a + 2a = N + a) for comparison,
The result of the comparison with the H count data (N + a) is equal, and a correct comparison is made despite the error a.

When the frequency drop is detected in this way, a detection signal is output from the magnitude comparison (1) circuit 1406, and one of them is sent to the OR circuit 1402.
The other is supplied to the set terminal of the RS flip-flop circuit 1410. Thus, R-S output of the flip-flop circuit 1410 becomes high level, f _H slowdown circuit (the circuit portion in the circuit 1112 S performing an operation at the time of frequency drop
Later for the rest of) the providing operation start instruction (f _H slowdown circuit excluding the to.).

Also, the portion including the latch (2) circuit 1403, the subtraction circuit 1407, and the magnitude comparison (2) circuit 1408 detects that the horizontal synchronizing signal frequency (the reciprocal of the cycle) has risen, contrary to the above case. I do. Here, even when TH data = N + a and H count data = Na, subtraction of the TH data from the data held in the latch (2) circuit 1403 is performed so as not to make an erroneous detection.

In this way, when the frequency rise is detected, a detection signal is output from the magnitude comparison (2) circuit 1408 and supplied to the input terminal of the OR circuit 1420 that is different from the above. And the OR circuit 1420
Rather, when the frequency of the input horizontal synchronization signal drops or rises, the video mute signal is output to the video amplification circuit 212 shown in FIG.
, And blanking is applied to the video signal when the frequency changes, so that the disturbance of the video is not displayed on the display screen.

[0131] Hereinafter, the operation of the f _H slowdown circuit consisting of the lower half of FIG. 15 (portion excluding the circuit portion S).

In order to always keep the phase synchronized with the horizontal synchronizing signal, the selector (2) circuit 1415 normally outputs the horizontal synchronizing signal H output from the synchronizing signal processing / frequency counter counter circuit 111 in FIG.
D (bar) is a D flip-flop circuit 1414 and an OR circuit 1
At 421, a signal obtained by differentiating the falling edge by one clock width is selected and supplied to the slowdown counter circuit 1412, where the count is cleared and the phase is adjusted.

Therefore, first, when there is no change in the frequency of the horizontal synchronization signal input to the synchronous deflection control circuit according to the present invention, the selector (4) circuit 1418 outputs the horizontal signal from the synchronization signal processing / frequency counter circuit 1111. The sync pulse HD (bar) is output as it is. The output of the RS flip-flop circuit 1410 in the internal circuit is also at the low level, and the selector (1) circuit 1411 selects and outputs TH data which is the cycle data of the horizontal synchronization signal. The TH data selected and output by the selector (1) circuit 1411 is output to an inverter circuit.
It is inverted at 1419 to become a complement, and given to the slowdown counter circuit 1412 as preset data.

The synchronous signal processing / frequency counter circuit is provided by a differentiating circuit including a flip-flop circuit 1414 and an OR circuit 1421.
The horizontal synchronization pulse HD (bar) from 1111 is differentiated, and the obtained differential output pulse is supplied to a preset terminal of a slowdown counter circuit 1512 through a selector (2) circuit 1415. At this timing, the TH data Is taken into the slowdown counter circuit 1412 as preset data. The slowdown counter circuit 1412 counts an input clock and counts the counted value.
When it is equal to the data, a carry output RCO is output.

Thus, the counting operation of the slowdown counter circuit 1412 is synchronized with the horizontal synchronization signal.

Next, a case is considered where the input horizontal synchronization signal is switched and its frequency is reduced. In this case, the aforementioned f _H change detection circuit (circuit portion S) detects this, turns the output of R-S flip-flop circuit 1410 to the high level. Thereby, the selector (1) circuit 1411 and the selector (2) circuit 14
15. All selector (4) circuits 1418 are switched.

The selector (1) circuit 1411 stops selecting the TH data up to that point, and selects and outputs the data from the latch (3) circuit 1404. Immediately after switching of the selector (1) circuit 1411, the latch (3) circuit 1404 includes:
Indicates the synchronization signal period before the horizontal synchronization signal frequency decreases
The same data as the TH data is set and held from the CPU 101 side. Therefore, this data is taken into the slowdown counter circuit 1412 via the inverter 1419, and when the clock is counted for the period indicated by the TH data, the slowdown counter circuit 1412 inputs the clock as the carry output RCO. A pulse having the same phase and substantially the same cycle as the synchronization signal immediately before the switching of the synchronization signal is output.

When the pulse as the carry output RCO passes through the selector (3) circuit 1416, it is divided into two directions. One is that the output of the RS flip-flop circuit 1410 first changes to a high level at this time. As a result, the signal passes through the selector (2) circuit 1415 that has been switched and is supplied to the preset terminal of the slowdown counter circuit 1412, so that the slowdown counter circuit 1412 is given a timing to load preset data.

The pulse as the other carry output RCO that has passed through the other selector (3) circuit 1416 is supplied to the pulse width setting circuit 141.
Given substantially the same width as the synchronizing signal by 7, also earlier R-S flip-flop circuit selector output 1410 is switched by turned to high level (4) circuit 1418 street f _H thrown at this point The horizontal synchronization pulse HD (bar) as the output of the down circuit becomes slow.

On the CPU 101 side, the RS flip-flop circuit 1410
(I.e., the slowdown signal) is monitored, and when it is found that this has turned to a high level, it is determined that it is time to start the slowdown operation. That is, the CPU 101 starts an operation of updating the data held in the latch (3) circuit 1404 by +1 at an appropriate predetermined interval.

As a result, the data updated by +1 is fetched into the slowdown counter circuit 1412 via the selector (1) circuit 1411 and the inverter 1419, so that the pulse as the carry output RCO has a cycle of one clock. As a result, the period of the horizontal synchronizing pulse HD (bar) slow output from the selector (4) circuit 1418 becomes longer by one clock.

Since the CPU 101 has TH data indicating the cycle of the input horizontal synchronization signal after the switching of the horizontal synchronization signal, the data (latch (3 ) Output of the circuit 1404), and when they are equal to each other, the control signal C1 previously latched by the latch (4) circuit 1424 is switched from the low level to the high level.

Then, the AND circuit 1422 opens, and the output of the AND circuit 1422 controls the selection operation in the selector (3) circuit 1416. That is, the selector (3) circuit 1416 and the pulse width setting circuit 14
17. The phase matching operation such that the phase of the horizontal synchronization pulse HD (bar) slow output through the selector (4) circuit 1418 matches that of the input horizontal synchronization signal is performed by the selector (3) circuit 1416. , AND circuit 1422, phase comparison circuit 1423
This will be described below.

The selector (3) circuit 1416 selects and outputs one of the carry output RCO of the slowdown counter circuit 1412 and an output obtained by delaying the carry output RCO by one flip-flop 1413. Therefore, the flip-flop circuit 1414 and
The horizontal synchronizing pulse HD (bar) from the synchronizing signal processing / frequency counter circuit 1111 by the differentiating circuit consisting of the OR circuit 1421
Is compared in the phase comparison circuit 1423 with the output pulse from the selector (3) circuit 1416, and if they do not match, the mismatched output is the AND circuit 142.
The signal passes through 2 to the selector (3) circuit 1416, which controls the selector (3) circuit 1416 to select the output of the flip-flop 1413.

The output of the flip-flop 1413 is an output obtained by delaying the carry output RCO of the slowdown counter circuit 1412 by one clock, and this output is the selector (3) circuit 1413.
16. The data is added to the slowdown counter circuit 1412 via the selector (2) circuit 1415, and the data capture timing there is delayed, so that the carry output RCO of the slowdown counter circuit 1412 is converted into the differential pulse output from the differentiating circuit. It works to approach the phase. By repeating this, when the phase matches between the output pulse from the selector (3) circuit 1416 and the differentiated pulse, the phase comparison circuit 1423 detects this and outputs a match output.

The coincidence output passes through the AND circuit 1422 and reaches the selector (3) circuit 1416. After that, the selector (3) circuit 1416 selects not the output of the flip-flop 1413 but the carry output RCO of the slowdown counter circuit 1412. To control.

Thus, the selector (3) circuit 1416 and the pulse width setting circuit
1417, the phase of the horizontal sync pulse HD (bar) slow output through the selector (4) circuit 1418 matches that of the input horizontal sync signal, and at the end of the operation of the _fH slowdown circuit Even if the selector (4) circuit 1418 is switched to the side of the horizontal synchronization pulse HD (bar) from the synchronization signal processing / frequency counter circuit 1111, no synchronization deviation occurs, and preparation for smooth switching is completed. become.

The CPU 101 that has been informed of such a state by some method, or the CPU 101 has latched in the latch (4) circuit 1424 after a lapse of time that predicted that such a state has occurred. with turn control signal C1 to the low level, resets the D flip-flop 1410 brought output pulse from the latch (4) circuit 1424 as the control signal C2 turn its output to a low level, the operation of the f _H slowdown circuit Terminate.

As described above, by applying the present invention to a display device, a wide range of deflection system processing from waveform generation to horizontal protection can be realized by a digital circuit. Further, since most of the present invention is constituted by digital circuits, it is easy to implement an LSI, which is advantageous in terms of manufacturing cost, circuit scale, and reliability.

[0150]

【The invention's effect】

According to the present invention, it is possible to optimally correct side pin distortion, focus error, and the like in accordance with a change in display specifications.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing an entire display device incorporating a synchronous deflection control circuit according to the present invention.

FIG. 3 is a block diagram illustrating a specific example of a polarity unification circuit in FIG. 1;

FIG. 4 is an explanatory diagram of the circuit operation of FIG. 3;

FIG. 5 is a block diagram showing another specific example of the polarity unification circuit.

FIG. 6 is a block diagram showing details of an _fH slowdown circuit in FIG. 1;

FIG. 7 is a block diagram showing a specific example of a waveform generation circuit in FIG. 1;

FIG. 8 is a waveform chart showing the operation of the circuit of FIG. 7;

FIG. 9 is a block diagram showing another specific example of the waveform generation circuit.

FIG. 10 is a block diagram showing another embodiment of the present invention.

11 is a circuit diagram and an operation waveform diagram illustrating an effect of the circuit shown in FIG. 6;

FIG. 12 is a block diagram showing still another embodiment of the present invention.

13 is a block diagram showing the entire display device incorporating the synchronous deflection control circuit shown in FIG.

14 is a block diagram showing a specific example of a synchronization signal processing / frequency counter circuit in FIG.

15 is a block diagram showing a specific example of f _H change detection · f _H slowdown circuit in FIG.

[Explanation of symbols]

101 microcomputer circuit, 102 input port (1) circuit, 105 input port (2) circuit, 108 H
Omission countermeasure circuit, 112 ...... f _H slowdown circuit, 115 ...... waveform generating circuit, 1111 ...... synchronization signal processing and frequency counter circuit, 1112 ...... f _H change detection · f _H slowdown circuit.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-64-39170 (JP, A) JP-A-1-315788 (JP, A) JP-A-2-100468 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) G09G 1/00 G09G 1/16 H04N 3/26 H04N 3/27

Claims (8)

(57) [Claims] 1. An image display apparatus comprising: a correction waveform generating means for generating a correction waveform for correcting an image displayed on a screen based on an input video signal and a synchronization signal; A memory means for generating a correction waveform corresponding to the deflection frequency of the input video signal, wherein the memory means stores waveform data corresponding to a reference correction waveform; and a waveform data from the memory means based on the input synchronization signal. Reading means for reading the data, a control circuit for outputting correction data for correcting the waveform data read by the reading means, correction data from the control circuit, and the waveform data read by the reading means. And a D / A for converting the output signal of the arithmetic processing means into an analog signal and outputting the corrected waveform
Means for rewriting the memory means with the output signal of the arithmetic processing means as new waveform data. 2. An image display apparatus comprising: a correction waveform generator for generating a correction waveform for correcting an image displayed on a screen based on an input video signal and a synchronization signal. A control circuit for outputting correction data for correcting the shape of the correction waveform created by the correction waveform creation means; and a waveform data corresponding to a reference correction waveform obtained at a timing synchronized with the input synchronization signal. An arithmetic processing means for arithmetically processing the correction data output from the control circuit and outputting the corrected data; and a D / A for converting an output signal of the arithmetic processing means into an analog signal and outputting the analog signal as the correction waveform.
And an image display device. 3. The image display device according to claim 1, wherein said arithmetic processing means is an adding means for adding said waveform data and said correction data. 4. The image display apparatus according to claim 1, wherein the correction waveform is a parabolic waveform for focus correction applied to a focus electrode of a cathode ray tube for displaying an image. 5. The image according to claim 1, wherein the correction waveform is a parabolic waveform for side pin correction supplied to a deflection circuit for performing a deflection operation for displaying an image. Display device. 6. The image display device according to claim 1, wherein said control circuit is a CPU. 7. The apparatus according to claim 1, wherein the waveform data corresponding to the reference correction waveform is stored in a memory means, and the waveform data is obtained by reading out the waveform data from the memory means in synchronization with the input synchronization signal. Item 3. The image display device according to Item 2. 8. The image display device according to claim 1, wherein said memory means is an E ² PROM.