JP3060819B2 - Helical scanning type recording / reproducing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a helical scanning type recording / reproducing apparatus, which records a digital information signal supplied through a transmission line and which has been compressed in a time axis, and converts the digital information signal into a desired one during reproduction. The present invention relates to a helical scanning type recording / reproducing apparatus capable of performing reproduction by extending the time axis to a transmission rate.

[0002]

2. Description of the Related Art With the progress of video (audio) information encoding (digitization) technology and its compression technology, and the development of digital signal processing LSIs represented by microprocessors and digital signal processors, AV systems and communication systems have been developed. In addition, the integration of computer systems has become possible, and a system called multimedia has attracted attention. In one field of this multimedia,
For example, there is a cable television (CATV). This CA
TV is currently analog transmission, but it is expected that it will shift to digital transmission in the future. In that case, the supplied information (television signal) is the current analog NTSC
Not only uniform information such as signals, but also video and audio quality (information compression ratio) and data transmission rate can be set to some extent freely according to the viewer's request. It seems that not only television signals but also other digital information can be widely transmitted. The technical information on CATV can be found, for example, in the Journal of the Institute of Television Engineers of Japan, Vol. 47, no. 8 1993, “Special Edition: Technical Trends in Cable TV,” P1048-P
1087.

Further, as a compression method by digital signal processing of current video (moving picture) information, MPEG (Moving Picture I / O) using motion compensation and DCT (Discrete Cosine Transform) is used.
mageCoding Expert Group) method has been developed, and significant compression is becoming possible. In general, the compression ratio and quality in video information and the like conflict with each other, but they are used depending on the purpose and purpose. For example, in the case of the current television (NTSC) signal, the quality after compression is reduced to the quality equivalent to the VTR recording level. In this case, there is a report that transmission is possible at about 1.5 Mbps including a voice signal. Hereinafter, a television signal of about 1.5 Mbps transmission is referred to as a compressed television signal. Regarding the compression technology of video information, for example,
Vol. 47, no. 6 1993, “Special Edition: Digital Recording Technology and Its Applications, 1-2: Trends in Digital Video Technology and Digital Recording Technology”, P801-P806, and the same magazine, Vol. 47, no. 10 1993, “Trends in Digital Video Transmission Technology”, pp. 1269 to 1276. Information of a low transmission rate as described above is transmitted to a C channel having a band of about 6 MHz per channel, for example.
When transmitting using a transmission path such as ATV, 20 to 25
A transmission rate of about Mbps becomes possible, and if the above-mentioned compressed television signal is used, information of about 12 channels can be transmitted even if redundant data is included.

On the other hand, in a VTR for recording and reproducing digital information with respect to a transmission path such as the above CATV, for example, Nikkei Electronics, 1993.7.19 (No.5)
86) As described on page 66, the transmission rate in recording / reproducing is about 25 Mbps in a single head configuration even at the consumer level due to the development of a high recording density technology and an increase in the relative speed between a magnetic head and a tape. A digital VTR having a recording / reproducing transmission rate of about 50 Mbps in a (channel) configuration is technically feasible. Therefore, if a digital VTR having a recording / reproducing transmission rate of about 25 Mbps is used, it is possible to record as many as 12 channels of the above-described compressed television signal including redundant data and the like. The above-mentioned quality and data transmission rate show one specific example.

When video information or audio information is handled as a digital signal, the digital information can be transmitted or recorded without distinction from video, audio, programs and data handled by a computer, and any other digital information. That is, the transmission and recording of digital information can be processed irrespective of the type of information to be processed, and in the future CA
Using a transmission path such as a TV, it becomes possible to supply not only television signals but also all digital information such as programs and data handled by a computer.

[0006] However, according to the above technique, when recording a compressed television signal in which a plurality of channels are simultaneously transmitted, unless the viewer (VTR user) wants to record all the channels simultaneously, the transmission path and the VTR are required.
(Recording medium) cannot be used effectively and efficiently. That is, when recording one desired channel of a compressed television signal, unnecessary channel information is also transmitted and recorded together, and the utilization efficiency of the transmission path and VTR (recording medium) is 10% or less ( In the case of the above transmission rate). This means that even if only necessary channels are transmitted and recorded, the utilization efficiency of the transmission path and the VTR (recording medium) is similarly 10% or less. Further, in the transmission and recording of programs handled by computer equipment having a low transmission rate and their data, the efficiency is further reduced.

Therefore, in order to solve these problems, the data transmission rate is increased to a transmittable rate by means of time axis compression or the like irrespective of the type of information, making use of the characteristics of the digital signal and transmitting at the same transmission rate. It is possible to do. This is to increase the transmission rate of information having a low transmission rate by compressing the time axis, thereby shortening the transmission time. For example, the compressed television signal (1.
When transmitting at 5 Mbps, the time axis is compressed 12 times, and the transmission rate including redundant data is increased to 20 to 25 Mbps.
s, and for example, a one-hour program is transmitted and recorded in 1/12 for 5 minutes.

[0008]

However, in the information transmission by the transmission rate conversion by the time axis compression described above,
On the viewer (information receiver) side, time axis expansion processing opposite to the above time axis compression is required. When this time axis expansion processing is performed using a buffer memory (memory for temporarily storing data) or the like, an enormous memory capacity is required. For example, if a 60-minute program with a transmission rate of 1.5 Mbps is compressed for 1/12 time axis and transmitted at a transmission rate of 18 Mbps for 5 minutes, at least 1.5 Mbps
Therefore, a buffer memory of a data amount (about 5 Gbits) corresponding to 55 minutes at the transmission rate is required, resulting in a large-scale and expensive system. Further, it is necessary to increase the buffer memory as the program becomes longer. Also, the information of the same transmission rate by the time axis compression is transmitted to the viewer side by V
Recording on the TR can be easily realized by using the above-mentioned digital VTR. However, expansion of the time axis during reproduction requires an enormous buffer memory similar to the above.

An object of the present invention is to provide a helical scan capable of extending and reproducing the time axis to its original state without requiring a huge buffer memory when recording and reproducing digital information with a time axis compression ratio. The present invention provides a recording / reproducing device of the type.

[0010]

In order to achieve the above object, the present invention relates to a helical scanning type recording / reproducing apparatus, which firstly inputs a digital signal supplied to a recording system at the time of recording to a recording system; Means for adding a first error detection and correction code (external check code) to the signal in predetermined units, means for dividing the digital signal to which the error detection and correction code has been added into predetermined blocks, and adding an address signal Means for adding a second error detection and correction code (internal check code) to the digital signal to which the address signal has been added, and converting the digital signal subjected to the digital processing into a signal form suitable for magnetic recording and reproduction. Modulating means, and recording means for recording the modulated digital signal on a magnetic tape; Tape running means for reducing the playback tape running speed as compared with the tape running speed at the time of recording; means for detecting a playback signal from the magnetic tape; and demodulation means for returning the playback signal modulated at the time of recording to the original digital signal form. Means for extracting a correct reproduced digital signal by the second error detection and correction code, means for detecting an address signal, and memory means for storing the correct reproduced digital signal in a predetermined area on a memory according to the address signal. Means for correcting the reproduced digital signal for each predetermined unit stored in the memory means using the first error detection and correction code, and time axis extending means for reading out the reproduced digital signal after error correction at a predetermined transmission rate .

Further, as other means for achieving the above object, data amount detecting means for detecting the data amount of the reproduced digital signal stored in the memory means, and data amount detecting information of the data amount detecting means. And a tape running means for controlling the playback tape running speed in accordance with the condition.

[0012]

As a function of the means for realizing the above object, the digital signal input means selectively inputs only necessary information from the digital information signal supplied through the transmission line. The first and second error detection and correction code adding means detects a code error (error) of the digital signal generated in the recording / reproducing process and generates an error detection and correction code for correctly correcting the error data. The address signal adding means generates an address signal for clarifying a time series of the reproduced digital signal. The modulating means modulates the recorded digital signal by, for example, 8-10 conversion suitable for magnetic recording and reproduction. The recording means amplifies the modulated recording digital signal to a level suitable for magnetic recording and records the signal on a magnetic tape by a magnetic head. Then, the tape running means of the reproducing system performs the approximate time axis expansion by decreasing the reproducing tape running speed in comparison with the tape running speed at the time of recording according to the time axis compression ratio of the recording digital signal.
The reproduction signal detection means detects a signal recorded on the magnetic tape using a magnetic head. The demodulation means converts the digital signal modulated at the time of recording into the original signal form. The reproduced digital signal extracting means detects an error using the error detection and correction code added at the time of recording, and detects only a correct digital signal. The address signal detecting means detects the address signal and clarifies the order on the time axis of the reproduced digital signal. The memory means sequentially stores the reproduced digital signals according to the address signals. The error correcting means corrects the error of the reproduced digital signal for each predetermined unit stored in the memory means using the error detection correction code. The time axis decompression means reads the reproduced digital signal for which error correction has been completed at a predetermined transmission rate.

The data amount detecting means detects the data amount of the reproduced digital signal stored in the memory means. The tape running means controls the playback tape running speed in accordance with the data amount detection information of the data amount detection means, so that when outputting a digital signal at a desired transmission rate at the time of playback, a small-capacity memory ensures that there is no excess or shortage of data. Enables continuous output of digital signals.

By the above means and operation, when recording and reproducing digital information compressed at the time axis,
It is possible to reproduce at a desired transmission rate with the time axis expanded to the original state without requiring a huge buffer memory.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. First, before a detailed description of the helical scanning type recording / reproducing apparatus of the present invention, the use environment of this apparatus is shown in FIG.
This will be described more simply. FIG. 2 shows a use environment of the helical scanning type recording / reproducing apparatus. In FIG. 2, a broken line portion 30 indicates a transmission station system for supplying a digital information signal, 31 indicates a transmission path of a digital information signal, and a broken line portion 32 indicates a viewer (user) device having the helical scanning type recording / reproducing device. Shows the system. Transmitting station 30
Is, for example, a digital VTR 33 or a disk drive 3
4, or by using a semiconductor recording / reproducing device 35 using a large-capacity memory or the like to compress the time axis of the digital information signal and make the transmission rate the same regardless of the type of information.
It is supplied to the PCM encoder 36. PCM encoder 3
In No. 6, an error detection and correction code, an index signal (identification signal) such as a type of synchronization signal and information, time axis compression rate information, and the like are used to prevent adverse effects due to occurrence of a code error (error) in the transmission process of the digital information signal. The digital information signal is supplied to the modulation circuit 37 with the redundant data added. The modulation circuit 37 converts the digital information signal into an efficient signal form suitable for the characteristics of the transmission path 32 at the next stage, for example, multi-level QAM and outputs it. The digital information signal supplied via the transmission path 31 is expanded in the original time axis by the helical scanning type recording / reproducing device 38, and when the transmission information is a video and audio signal, it is further converted into an analog signal. The data is output to the television monitor 39 and can be viewed. On the other hand, when the transmission information signal is a program or data used for a computer device or the like, it is reproduced at a transmission rate suitable for the external device by an external command (control signal),
The information is supplied to a digital information device 40 such as a computer. Note that whether the digital information signal to be transmitted is a video signal or an audio signal, or a signal such as a program and data is determined by the PCM.
The detection can be easily performed by detecting the added index signal by the encoder 36.

The helical scanning type recording / reproducing apparatus of the present invention will be described in detail with reference to FIG. FIG. 1 is a block diagram showing a configuration of a helical scanning type recording / reproducing apparatus to which the present invention is applied. In FIG. 1, 1 is a magnetic tape, 2 is a drum (including a drum motor), 3a and 3b are magnetic heads,
4 is capstan, 5 is capstan motor, 6 is CT
L head, 7 to 12 are signal input or output terminals, 1
3 is a channel selector (tuner), 14 is a demodulation circuit, 15 is a PCM decoder, 16 is a digital signal processor (hereinafter referred to as DSP), 17 is a modulation circuit,
18 is a recording amplifier, 19 is a system controller, 20
Is a drum servo circuit, 21 is a CTL generation / detection circuit, 2
2 is a capstan servo circuit, 23 is a reproduction amplifier, 24
Is a demodulation circuit, 25 is a DSP, 26 is a memory, 27 is an index signal detection circuit, 28 is an MPEG decoder (information decompression circuit), and 29 is a DA converter. Hereinafter, operations during recording and reproduction will be described along the flow of signals.

In FIG. 1, an input information signal supplied via an input terminal 7 is supplied to a channel selector 13. The channel selector 13 selects an information signal of a desired channel according to a channel designation signal CH supplied from the system controller 19 and supplies the information signal to the demodulation circuit 14. The channel designation signal CH is supplied to the input terminal 8
Is set by a user command signal supplied via the.
The demodulation circuit 14 demodulates the input information signal modulated into a signal form suitable for the transmission path 32, converts the demodulated input information signal into an original digital signal, and supplies the digital signal to the PCM decoder 15. The PCM decoder 15 performs error detection and correction of the input digital information signal, supplies a digital information signal to the DSP 16 at the next stage, detects an index signal, and supplies the index signal to the system controller 19. Further, a synchronization signal for detecting a data block configuration is separated and supplied to the drum servo circuit 20. The system controller 19 to which the index signal has been supplied selects data necessary for reproduction such as information on the time axis compression ratio and information indicating the type of the recording information signal from the index signal, supplies the data to the DSP 16, and outputs the data. Although not shown, it is supplied to a display system via a terminal 9 to display the information of the index signal to the user. The DSP 16 includes a digital information signal supplied from the PCM decoder 15 and a system controller 19.
And an index signal required at the time of reproduction, which is supplied from the computer, is converted into a signal form suitable for magnetic recording and reproduction. That is, in order to cope with a code error in magnetic recording / reproducing, data blocking and addition of address data, and addition of strong error detection and correction codes such as interleaving and Reed-Solomon codes are performed. FIG. 3 shows an example of a block structure of the recording information signal. The digital information and the index signal input to the DSP 16 are arranged as shown in the lower part of FIG. 3 by using, for example, information recorded on one track (a track formed by one scanning by the magnetic head) as a unit.
After the outer check code is added in the vertical direction, the inner check code is added in the horizontal direction. In this case, the check code is generated for the data A and the address information and for the data B as shown in the upper part of FIG.
The recording information signal to which the error detection and correction code has been added as described above is supplied to the modulation circuit 17 with a block synchronization signal (hereinafter, referred to as SYNC) indicating the beginning of the block added before the address information. The modulation circuit 17 converts the recording information signal into, for example, 8-10 conversion or 8 conversion suitable for magnetic recording.
The signal is modulated into a digital signal such as -12 conversion and supplied to the recording amplifier 18 as a serial signal. The recording amplifier 18
The recording digital signal is amplified to a level suitable for magnetic recording, and is recorded on the magnetic tape via the magnetic heads 3a and 3b with an optimum recording current.

In general, when an error detection and correction code is generated in units of information recorded on one track as described above, the address signal added to each SYNC block also uses the information recorded in one track as a unit. In this embodiment, the address value is generated in units of information recorded on four tracks.
Specifically, M SYNs that generally constitute one track
While address values from 0 to M-1 are assigned to the C block, in the present embodiment, in units of 4 tracks, 0 to M-1 are assigned to the block of the first track and M to M are assigned to the block of the second track. Address values of 2M-1 are assigned to blocks of the third track, and 2M to 3M-1 are assigned to blocks of the fourth track, and addresses of 3M to 4M-1 are assigned to blocks of the fourth track. This means that two bits are added to an address generated in units of one track, and the two bits are added to 00, 01, 1
Counting in the track cycle of 0, 11, 00,... 2
It can be easily realized by using it as a bit counter. FIG. 4 is a schematic diagram showing the added 2-bit value and the track pattern to be recorded. The address generation in the four-track cycle is for correctly detecting the reproduced data when reproducing at a tape running speed lower during recording than during recording, and will be described in detail later. Perform at the operation. In this embodiment, the case where the time axis compression ratio of the recording digital information is 1/12 is set.

Here, the servo of the drum 2 and the capstan 4 during recording will be described. In this embodiment,
The case of helical scanning with 180 degrees facing two heads using an azimuth head is taken as an example, and the rotation frequency of the drum is 25.
In order to secure a recording transmission rate of about 30 Mbps, three times the frame frequency of the television signal (about 5400
rpm: three times the rotation frequency of a general household VTR). Therefore, the number of tracks formed in the field period of the television signal is three. Drum 2
The control of the capstan 4 is performed by the drum servo circuit 20 and the capstan servo circuit 22 according to the drum and capstan command signals DC and CC supplied from the system controller 19. FIG. 5 is a block diagram showing the internal configuration of the drum servo circuit 20 and the capstan servo circuit 22. In FIG.
0 is a drum servo circuit, and a broken line portion 22 is a capstan servo circuit. And 41-44 and 56-5
8 is an input terminal, 45, 46, and 59 are output terminals.
7, 60 are speed detection circuits, 48, 61 are speed target setting circuits, 49, 52, 62 are subtraction circuits, 50 is a phase detection circuit, 51 is a phase target setting circuit, 53 and 65 are addition and characteristic compensation circuits, 54 , 66 are DA converters, 55 and 67 are motor driver amplifiers (hereinafter referred to as MDA),
63 is an integrating circuit, and 64 is a switch.

First, the drum servo will be described. In FIG. 5, the DFG (Dr
am Frequency Generator) signal is supplied to the speed detection circuit 47. Although not shown, the DFG signal generating mechanism is a frequency signal generated in proportion to the rotation frequency of the drum 2. The speed detection circuit 47 detects the rotation speed of the drum 2 by measuring the period of the DFG signal, and supplies the speed detection information to the subtraction circuit 49. The drum command signal DC supplied from the system controller 19 via the input terminal 41 is supplied to the speed target setting circuit 48 and the phase target setting circuit 51. The speed target setting circuit 48 generates a rotation speed target of the drum 2 which is three times the frame frequency according to the drum command signal DC, and supplies the speed target information to the subtraction circuit 49. The subtraction circuit 49 subtracts the speed detection information and the speed target information, and supplies the difference, that is, speed error information, to the addition & characteristic compensation circuit 53.
On the other hand, the DPG (Dram P
The “hase generater” signal is supplied to the phase detection circuit 50. Although not shown, the DPG signal is a phase signal synchronized with the rotation of the drum 2 and having a predetermined phase relationship with the rotation phase of the magnetic head 3a or 3b. Phase detection circuit 50
Detects the rotation phase of the drum 2 by detecting the phase of the DPG signal, and supplies the phase detection information to the subtraction circuit 52. The phase target setting circuit 51 generates phase target information from the synchronization signal of the input information signal supplied from the PCM decoder 15 via the input terminal 42 during recording, and supplies the phase target information to the subtraction circuit 52. The phase target setting circuit 51 generates a CTL signal via an output terminal 45 through a control signal (hereinafter, referred to as a CTL signal) having a frequency obtained by multiplying the rotation frequency of the drum 2 in synchronization with the rotation phase of the drum 2. It is supplied to the detection circuit 21. In the present embodiment, the frequency multiplication rate of the CTL signal is set equal to the time axis compression rate of the recording information signal, and the frequency is 1080 Hz (30 Hz × 3 × 12).
The subtraction circuit 52 performs a subtraction between the above-described phase detection information and the phase target information, and adds the phase error information, which is a difference between the two, to the &
It is supplied to the characteristic compensation circuit 53. Addition and characteristic compensation circuit 53
Adds the speed error information and the phase error information, performs a characteristic compensation filter process such as phase delay compensation so as to obtain a desired servo characteristic, and supplies the result to the DA converter 54. The DA converter 54 includes an addition & characteristic compensation circuit 5
3 is converted to an analog signal and supplied to the MDA 55. The MDA 55 amplifies the power of the drum control signal and supplies it as a drum drive signal to the drum 2 via the output terminal 46, and rotates the drum 2 at a predetermined speed and a predetermined phase. Although the above-mentioned phase target information is generated using the synchronization signal of the input information signal, this is achieved by controlling the rotation of the drum 2 in accordance with the transmission rate of the input information signal, so that the input information signal can be generated without excess or shortage. It is something that can be recorded.

Next, the capstan servo will be described. In FIG. 5, CF supplied via input terminal 57
The G (Capsutan Frequency Generator) signal is supplied to the speed detection circuit 60. Although a CFG signal generating mechanism is not shown, it is a frequency signal generated in proportion to the rotation frequency of the capstan 4 like the DFG signal. The speed detection circuit 60 detects the rotation speed of the capstan 4 by measuring the period of the CFG signal, and supplies the speed detection information to the subtraction circuit 62. Capstan command signal C supplied from the system controller 19 via the input terminal 56
C is supplied to the speed target setting circuit 61. The speed target setting circuit 61 generates a rotation speed target of the capstan 4 according to the capstan command signal CC, and supplies the speed target information to the subtraction circuit 62. The subtraction circuit 62 performs a subtraction between the speed detection information and the speed target information, and supplies the difference of the speed error information to the addition & characteristic compensation circuit 65 and the integration circuit 63. The integration circuit 63 generates speed error integration information by sequentially accumulating the speed error information supplied from the subtraction circuit 62, and supplies the speed error integration information to the switch 64. The switch 64 is set to A during recording.
The speed error integration information, which is closed on the input terminal side and is the output of the integration circuit 63, is supplied to the addition & characteristic compensation circuit 65.
The addition & characteristic compensation circuit 65 adds the speed error information and the speed error integration information, performs a characteristic compensation filter process such as phase delay compensation so as to obtain a desired servo characteristic, and supplies the result to a DA converter 66. DA converter 6
6 converts the capstan control signal supplied from the addition & characteristic compensation circuit 65 into an analog signal and supplies the analog signal to the MDA 67. The MDA 67 amplifies the power of the capstan control signal and supplies it as a capstan drive signal to the capstan motor 5 via the output terminal 59, rotates the capstan 2 at a predetermined speed, and runs the magnetic tape 1 at a predetermined speed. Let it. The integrating circuit 63 is provided with an integral control system in addition to the speed system (proportional control system) so that the steady speed deviation becomes zero.

In the above recording operation, the CTL signal supplied from the phase target setting circuit 51 of the drum system is supplied to the CTL generation / detection circuit 21 shown in FIG. The level is converted to a level and supplied to the CTL head 6 to be recorded on a linear track on the magnetic tape. The above is the operation of the present apparatus during recording. Next, an operation at the time of reproduction which is important in the present invention will be described.

In FIG. 1, the magnetic head 3a or 3
The reproduction signal reproduced from the magnetic tape 1 at b is supplied to the demodulation circuit 24 after being sufficiently amplified by the reproduction amplifier 23. After demodulating the supplied reproduction information signal, the demodulation circuit 24 extracts a clock component, strobes the reproduction data using the clock, and converts the signal into a logic signal. Then, a demodulation process reverse to that at the time of recording is performed, and DSP2
5, a demodulated reproduced digital signal is supplied. DSP
The general operation of 25 is to detect an error in the reproduced digital signal.
Correction is performed, and deinterleaving is performed based on the address information to return to the original data permutation, which is supplied to the memory circuit. The operation of the DSP 25 will be described in detail with reference to FIGS. FIG. 6 is a block diagram showing a specific configuration example of the DSP 25. 6, 68 is an input terminal, 6
9 is an output terminal, 70 is a SYNC detection circuit, 71 is an inner check code decoder, 72 is an address detection circuit, 73 is a memory switching circuit, 74, 75, 79 80 are switches, 76
77 is a memory, and 78 is an outer check code decoder. In FIG. 6, a reproduced digital signal supplied through an input terminal 68 is supplied to a SYNC detection circuit 70. The SYNC detection circuit 70 detects the SYNC signal from the reproduced digital signal supplied as serial data, and clarifies the block configuration shown in the upper part of FIG. The block of the reproduced digital signal is supplied to the inner check code degoder 71. Inspection code degoder 71
Performs error detection and, if possible, error correction on the reproduced digital signal in block units using an inner check code. The reproduced digital signal determined to be correct by the inner check code degoder 71 is supplied to the switch 74 and the address detection circuit 72. The switch 74 distributes and supplies the reproduced digital signal to the memory 76 and the memory 77 in accordance with the control signal supplied from the memory switching circuit 73. Each of the memory 76 and the memory 77 has a capacity to store a reproduced digital signal corresponding to one track, which is a unit of error correction using an outer check code. The address detection circuit 72 extracts an address signal from the reproduced digital signal and supplies the address information to the memory switching circuit 73.
The memory switching circuit 73 controls switching of the switches 74, 75, 79, and 80 according to the address information.

The operation of the memory switching in an actual reproduction state will be described in detail with reference to FIGS. 7 and 8. FIG. 7 is a schematic diagram showing an example of a magnetic head scanning locus at the time of reproduction at 1/12 speed. In FIG. 7, squares with alphabets represent each track,
An oblique line on the track indicates a scanning trajectory of the magnetic head.
In this figure, the width of the magnetic head is equal to the width of the track, and the scanning trajectory of the magnetic head is T0 (+), T1 (-),
.., T26 (+), T27 (-). (+) And (-) indicate the azimuth of the scanning head. In this embodiment, since the tape traveling speed during reproduction is set to 1/12 of the tape traveling speed during recording, the tape movement corresponding to one track is performed during 12 head scanning periods. FIG. 8 is a schematic diagram showing the waveform of the reproduction envelope signal in the reproduction state shown in FIG. When the information of the track a is to be written to the memory 76, the reproduced digital signal whose track identification 2 bits of the address signal in the correctly reproduced block unit reproduced digital signal is 00 is supplied to the memory 76. Then, the switch 74 is closed to the A terminal side. Then, the correct digital signal reproduced from the lower part of the track a in the T2 (+) period shown in FIG. 8 is supplied to the memory 76, and is sequentially T4 (+) period, T6 (+) period, T8
Correct digital signals reproduced from the lower part to the upper part of the track a in the (+) period are supplied to the memory 76. In the above case, the same digital signal is supplied to the memory 76 in duplicate, but unless the supplied digital signal is an error signal,
There is no problem even if duplicate writing is performed, but there is an advantage that memory control is made easier. Then, a block in which a correct reproduced digital signal has not been finally written is determined as an error, and error correction is performed by a later outer check code. In the situation where the information of the track a is written in the memory 76 as described above, the other memory 77
From the writing of the information on the track z to the error correction processing of the reproduced digital signal on the track z by the outer check code,
The process shifts to writing information of track b via batch transfer of the reproduced digital signal to the memory 26 shown in the figure.

An important point in the above-mentioned transition of the signal processing is the start timing of the error correction processing using the outer check code.
In the present embodiment, the reproduced digital signal from the following track separated by one track from this timing is reproduced, and updating of the reproduced digital signal is terminated when it is determined that even one block is correct by error detection by the inner check code, The error correction using the outer check code is started. The means for determining that the reproduced digital signal from the following track separated by one track is correct is to detect a 2-bit address signal for track identification. Therefore, when the correct reproduction digital signal of the track b is obtained for the first time during the period T11 (-) in FIG. 8 and the track identification 2-bit address signal 01 is detected, the switches 75 and 80 shown in FIG. Is closed to the B terminal side according to the control signal supplied from the memory switching circuit 73. Then, the outer check code decoder 78
Is connected to the memory 77 and performs error correction of the signal written in the memory 77 by using the memory 77, that is, the reproduced digital signal from the track z by the outer check code. When the error correction by the outer check code is completed, an end signal is supplied to the memory switching circuit 73. As a result, the memory switching circuit 73 generates a control signal for closing the switch 79 to the B terminal side, and supplies the control signal to the switch 79. And
The error correction completion digital signal of the track z written in the memory 77 is transmitted to the switch 79 and the output terminal 6.
9 is supplied to the memory circuit 26 shown in FIG.
When the transfer of the reproduction digital signal of the track z is completed,
The track b is stored in the memory 77 from the period T13 (-) in FIG.
The information reproduced from is sequentially written. Similarly,
The reproduced digital signal of the track a written in the memory 76 is output at a timing at which, for example, a 2-bit address signal "10" for track identification reproduced from the track c is detected in the period T22 (+) in FIG. An error correction process using a check code is started. At this time, the switches 75 and 80 are closed to the A terminal side. Thereafter, the above-described digital processing in units of one track is performed at the timing of detecting a reproduction digital signal (a 2-bit address signal for track identification) from a subsequent track separated by one track.

A memory circuit 26 to which a reproduced digital signal whose error has been corrected by the processing of the DSP 25 is supplied.
According to an output transmission rate designation signal supplied from the system controller 19, a predetermined transmission rate, for example, 1.
The reproduced digital signal of 5 Mbps is transmitted to the MPEG decoder 2
8 and output terminal 10. MPEG decoder 2
Numeral 8 decompresses (expands) the compression by decoding if the reproduced signal is a compressed signal of the MPEG system according to the identification signal of the reproduced digital signal and the setting signal of the decoding system supplied from the system controller 19. The signal and the digital audio signal are supplied to the DA converter 29. The DA converter 29 converts the supplied digital video and audio signals into analog signals,
The signals are output via output terminals 11 and 12, respectively. In the case where the reproduced digital signal is a data signal used for a computer device or the like, the signal is converted to a predetermined transmission rate and then output via the output terminal 10.

The setting signal and the identification signal supplied from the system controller 19 to the memory circuit 26 and the MPEG decoder 28 include an index signal included in the reproduced digital signal and an index signal detecting circuit 27.
And is decoded by the system controller 19.

Next, servo control during reproduction will be described with reference to FIG. First, the drum servo will be described. In FIG. 5, the speed control of the drum 2 is performed by generating speed error information by the speed detection circuit 47, the speed target setting circuit 48, and the subtraction circuit 49 by the same processing as in the recording described above. In the phase control, since the synchronizing signal of the input digital information signal is not supplied during reproduction, the phase target setting circuit 51 shown in FIG. 5 uses a stable clock (not shown) generated by a crystal oscillator or the like. ,
A phase reference signal having a frequency three times the frame frequency of the television signal is generated, a phase target signal is generated based on the phase reference signal, and supplied to the subtraction circuit 52. The subtraction circuit 52 subtracts the phase detection information and the phase target information, and supplies the difference, that is, phase error information, to the addition & characteristic compensation circuit 53. The processing after the addition & characteristic compensation circuit 53 is the same as that at the time of recording.

In the tape running control at the time of reproduction, that is, the capstan control, it is necessary to control the tape running speed in accordance with the time axis compression ratio of the recorded digital information signal.

In the tape running control, that is, the capstan control at the time of reproduction, it is necessary to control the tape running speed in accordance with the time axis compression ratio of the recorded digital information signal. 5, the speed detection circuit 60 detects the rotation speed of the capstan 4 by measuring the period of the CFG signal, and supplies the speed detection information to the subtraction circuit 62. The speed target setting circuit 61 receives a capstan command signal C supplied from the system controller 19 via the input terminal 56.
In accordance with C, a rotation speed target of the capstan 4 is generated, and the speed target information is supplied to the subtraction circuit 62. The system controller 19 detects the time axis compression ratio information of the reproduced digital signal from the reproduced index signal, determines the speed target of the capstan 4 from this information, and supplies it to the speed target setting circuit 61 as a capstan command signal CC. Therefore, when the time axis compression ratio of the reproduced digital signal is 1/12, the target tape speed at the time of reproduction is set to 1/12 of the tape speed at the time of recording.

In order to make the tape speed at the time of reproduction equal to 1/12 of the tape speed at the time of recording, it is necessary to configure an integral control system of the speed. This is performed using the reproduction CTL signal. The integral control of the speed by the reproduction CTL signal
In the CTL generation / detection circuit 21 shown in FIG.
The phase comparison between the reproduced CTL signal detected from the L head 6 and the phase reference signal having a frequency three times the frame frequency of the television signal generated by the phase target setting circuit 51 shown in FIG. A phase error signal is generated. The phase error signal based on the reproduced CTL signal is supplied to the switch 64 via the input terminal 58 shown in FIG.
Supplied to The switch 64 is closed on the B terminal side during reproduction, and supplies the phase error signal generated from the reproduced CTL signal to the addition & characteristic compensation circuit 65. By the above operation, the tape running speed is controlled so that the reproduction CTL signal frequency becomes 1/12 of the recording CTL signal frequency.

As described above, according to the present embodiment, a time-axis-compressed digital information signal supplied via a transmission line is recorded, and a tape equal to the time-axis compression rate of the recorded information signal during reproduction is recorded. The digital signal is reproduced at the traveling speed and digital processing is performed in units of information recorded on one track. The detection completion timing of the intermittently reproduced one-track digital signal is set one track away from the detected track. By making a determination based on the detection of the reproduced digital signal of the succeeding track, the required digital signal of one track unit can be detected without omission, and the detected digital signal of one track unit is output at a desired transmission rate. Accordingly, it is possible to extend the time axis to the original state and reproduce the image without requiring a large-scale buffer memory.

Although the present embodiment has been described with reference to the case where the time axis compression ratio of the input (recorded) digital information signal is 1/12, the time axis compression ratio may be different. Although an integral control system for the tape speed at the time of reproduction is employed, for example, an ATF system using a pilot signal used in 8 mm video or the like may be used.

Next, a second embodiment will be described.
A major difference between the second embodiment and the previous embodiment is the tape running control during reproduction. Hereinafter, this will be described in detail with reference to FIG. FIG. 9 is a block diagram showing a configuration of a helical scanning type recording / reproducing apparatus to which the present invention is applied. FIG.
In FIG. 7, blocks denoted by the same reference numerals as the blocks shown in FIG. 1 have the same or similar functions as the blocks in FIG. The difference between the apparatus of FIG. 9 and the apparatus of FIG. 1 is that the CTL head 6 and the CTL
Although the detection circuit 21 is deleted, a data amount detection circuit 80 is newly provided. Hereinafter, the tape running control during reproduction in which the data amount detection circuit 80 plays an important role will be described in detail.

In the above embodiment, the tape running control during reproduction is performed using the CTL signal. In this case, the tape traveling speed during reproduction can be controlled more accurately than during recording. Specifically, for example, when the tape traveling speed at the time of reproduction is set to 1/12 of that at the time of recording as in the above embodiment, the frequency of the reproduction CTL signal is 1/12 of the frequency of the CTL signal at the time of recording. This is realized by controlling the tape running speed. On the other hand, in the second embodiment, the tape running control is performed so as to balance the reproduced digital signal amount and the output digital signal amount without using the CTL signal or the like. In FIG. 9, the operation at the time of recording is CTL
Other operations are the same as those of the embodiment shown in FIG. 1 except that the signal recording system is deleted, and the description thereof is omitted here. The operation at the time of reproduction is the same as that of the embodiment shown in FIG. 1 except for the newly provided data amount detection circuit 80 and capstan servo circuit 22, and the description thereof is omitted here. Hereinafter, the operations of the data amount detection circuit 80 and the capstan servo circuit 22 will be described in detail.

In FIG. 9, a reproduced digital signal subjected to error correction processing by the DSP 25 during reproduction is supplied to the memory circuit 26 in units of a reproduced digital signal corresponding to one track. At this time, the data amount information of the digital signal supplied to the memory circuit 26 is supplied to the data amount detection circuit 80. The memory circuit 26 converts the reproduced digital signal supplied from the DSP 25 into an MPEG decoder 28 and an output terminal 10 as a reproduced digital signal having a predetermined transmission rate, for example, 1.5 Mbps, in accordance with an output transmission rate designation signal supplied from the system controller 19. To supply. At this time, the data amount information of the time-axis-extended digital signal output from the memory circuit 26 is
It is supplied to the data amount detection circuit 80. As described above, the data amount detection circuit 80 to which the data amount information to be written to the memory circuit 26 and the data amount information to be read are supplied.
Generates a correction signal for controlling the tape traveling speed from the two data amount information and supplies it to the capstan servo circuit 22. FIG. 10 shows a specific configuration of the data amount detection circuit 81. 10, 82 and 83 are input terminals, 84 is an output terminal, 85 and 87 are subtraction circuits, 86 is a latch circuit,
88 is an offset data amount generation circuit, 89 is a limiter circuit, and 90 is a polarity inversion circuit. In FIG. 10, the write data amount signal and the read data amount signal of the memory circuit 26 supplied via the input terminals 82 and 83 are subtracted by the subtraction circuit 85. The difference signal of the data amount generated in the subtraction processing of the subtraction circuit 85 is
Supplied to The latch circuit 86 latches the differential signal of the data amount at a timing delayed by a predetermined time (Td) from the timing of writing the digital signal supplied from the DSP 26 to the memory circuit 26, for example. The difference signal of the latched data amount is subtracted from the offset data amount signal supplied from the offset data amount generation circuit 88 by a subtraction circuit 87 and supplied to a limiter circuit 89. The limiter circuit 89 limits the data amount difference signal obtained by subtracting the offset data amount within a predetermined range, and
To supply. The polarity inversion circuit 90 inverts the polarity of the data amount difference signal and supplies the inverted signal to the capstan servo circuit 22 shown in FIG. FIG. 11 shows a typical waveform example of the data amount difference signal output from the subtraction circuit 85 in FIG. In FIG. 11, (1) shows a case where the tape running speed during reproduction is correctly controlled,
(2) shows a case where the tape running speed is low, and (3) shows a case where the tape running speed is high. The arrow in the figure indicates the latch timing of the latch circuit 86. As can be seen from FIG. 11, the value of the data amount difference signal changes according to the tape running speed, and thus can be used as a correction signal for controlling the tape running speed. Note that the latch circuit 86 has a sawtooth waveform as it is when the data amount difference signal output from the subtraction circuit 85 is used as it is, and if this is used as a correction signal for controlling the tape running speed, the tape running is disturbed.
Used as smoothing means. The polarity inversion circuit uses the data amount difference signal (correction signal for controlling the tape running speed) as a negative feedback signal. The polarity inversion circuit 9
0 can be reduced by reversing the polarity of the subtraction circuit. Further, the correction signal for controlling the tape running speed is smoothed by the sample hold output using the latch circuit 86. This is, for example, an LPF (low-pass filter).
May be used to smooth the difference data amount. The capstan servo circuit 22 to which the correction signal for controlling the tape running speed is supplied has the above-described configuration shown in FIG. In the capstan servo circuit 22, the speed error signal generated by the speed detection circuit 60, the speed target setting circuit 61, and the subtraction circuit 62 is the same as in the previous embodiment. The correction signal for controlling the tape traveling speed supplied from the data amount detection circuit 81 via the switch 64 closed on the side is supplied to the addition & characteristic compensation circuit 65. The capstan control signal generated by the addition & characteristic compensation circuit 65, the DA converter 66, and the MDA 67 is supplied to a capstan motor 5 to rotate the capstan 4 to rotate the magnetic tape 1 to a desired speed, that is, to reproduce the reproduced digital signal on the time axis. The tape runs at a tape speed at which signals can be output continuously without any excess or shortage.

The reproduced digital signal output from the memory circuit 26 at a predetermined transmission rate is converted into an MPEG decoder 28
And output terminal 10 to be processed and output as in the previous embodiment.

As described above, according to this embodiment, the time-axis-compressed digital information signal supplied via the transmission line is recorded, and the time-axis compression ratio of the recorded information signal is adjusted during reproduction. When reproducing at the tape running speed, the data amount of the digital signal reproduced from the magnetic tape is compared with the data amount of the output digital signal amount at a predetermined transmission rate,
The tape running speed at the time of reproduction is controlled so that the difference between the two data amounts becomes a predetermined amount, and the reproduced digital signal is continuously and without a shortage at a desired time-axis expansion rate (transmission rate). Since the output can be performed, the time axis can be expanded to the original state and reproduced without requiring a large-scale buffer memory.

[0039]

As described above, according to the present invention, a digital information signal which is supplied via a transmission line and compressed on a time axis is recorded, and a large-scale buffer memory is required for reproduction. The digital information signal can be reproduced at a desired time-base expansion rate, that is, at a desired transmission rate.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a helical scanning type recording / reproducing apparatus of the present invention.

FIG. 2 is a configuration diagram showing a use environment of a helical scanning type recording / reproducing apparatus of the present invention.

FIG. 3 is a diagram showing an error detection correction code structure and a block configuration of a recording information signal.

FIG. 4 is a diagram showing an example of a track pattern recorded by the present apparatus.

FIG. 5 is a block diagram showing a configuration of a drum servo circuit and a capstan servo circuit.

FIG. 6 is a block diagram showing a configuration of a digital signal processor in a reproduction signal processing system.

FIG. 7 is a diagram showing a recording track pattern and a head scanning trajectory when a 1/12 double speed tape runs.

FIG. 8 is a diagram showing a reproduction envelope signal waveform at the time of tape running reproduction at a 1/12 speed.

FIG. 9 is a block diagram showing a configuration of a helical scanning type recording / reproducing apparatus of the present invention.

FIG. 10 is a block diagram illustrating a configuration of a data amount detection circuit.

FIG. 11 is a diagram showing a data amount difference signal waveform in the data amount detection circuit.

[Explanation of symbols]

 13: channel selector, 14, 24: demodulation circuit, 15: PCM decoder, 16, 25: digital signal processor, 17, 37: modulation circuit, 19: system controller, 20: drum servo circuit, 21: CTL generation / detection circuit 22, a capstan servo circuit, 26, 76, 77 a memory circuit, 27 an index signal detection circuit, 28 an MPEG decoder, 29, 54, 66 a DA converter, 47, 60 a speed detection circuit, 48, 61 Speed target setting circuit, 49, 52, 62, 85, 87 ... subtraction circuit, 50 ... phase detection circuit, 51 ... phase target setting circuit, 53, 65 ... addition & characteristic compensation circuit, 55, 67 ... motor driver amplifier, 63 ... Integration circuit, 64,74,75,79,80 ... Switch, 70 ... SYNC detection circuit Reference numeral 71: inner check code decoder 72: address detection circuit 73: memory switching circuit 78: outer check code decoder 81: data amount detection circuit 86: latch circuit 88: offset data amount generation circuit 89: limit Circuit, 90 ... polarity reversal circuit.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Akifumi Mibe 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Hitachi, Ltd. (58) Field surveyed (Int. Cl. ⁷ , DB name) G11B 15/467 G11B 20/18

Claims (6)

(57) [Claims] 1. A digital information signal compressed via a time axis, which is supplied via a transmission path, is recorded, and reproduced at a tape running speed different from that at the time of recording, so that the transmission rate of the digital information signal at the time of reproduction is set at the time of recording. In a helical scanning type recording / reproducing apparatus having a different configuration, a first error detection and correction code is added to a recording system by adding a first error detection and correction code for each predetermined unit to an input digital signal supplied via a transmission path. Code adding means, address signal adding means for dividing the digital signal to which the error detection and correction code has been added into predetermined blocks and adding an address signal, and a second error detection and correction code for the digital signal to which the address signal has been added. A second error detection and correction code adding means for adding a digital signal, a modulating means for converting a recording digital signal into a predetermined signal form, Recording means for recording the adjusted digital signal on a magnetic tape; and tape running means for running the magnetic tape at a first speed. The reproducing system is provided with a magnetic tape corresponding to the time axis compression ratio of the input digital signal. Tape running means for running at a second speed, playback signal detection means for detecting a playback signal from the magnetic tape, demodulation means for returning the modulated playback signal to the original digital signal form, and second error detection and correction Error detecting means for extracting a correct reproduced digital signal by a code; address detecting means for detecting an address signal; memory means for writing the correct reproduced digital signal to a predetermined area on a memory in accordance with the address signal; A signal for detecting a reproduced digital signal from a subsequent track separated by one track from the track on which the signal was recorded. Signal detection means, error correction means for correcting the reproduced digital signal for each predetermined unit written in the memory means using a first error detection and correction code, and reproducing the error-corrected reproduced digital signal for a predetermined unit. A time axis extending means for reading out at a transmission rate, stopping updating of a digital signal reproduced from the same track to the memory means in accordance with a detection signal of the signal detecting means, and a predetermined unit in the error correcting means. A helical scanning type recording / reproducing apparatus, wherein error correction processing of a reproduced digital signal is started for each of them. 2. A digital information signal compressed via a time axis, which is supplied via a transmission path, is recorded and reproduced at a tape running speed different from that at the time of recording. In a helical scanning type recording / reproducing apparatus having a different configuration, a first error detection and correction code is added to a recording system by adding a first error detection and correction code for each predetermined unit to an input digital signal supplied via a transmission path. Code adding means, address signal adding means for dividing the digital signal to which the error detection and correction code has been added into predetermined blocks and adding an address signal, and a second error detection and correction code for the digital signal to which the address signal has been added. A second error detection and correction code adding means for adding a digital signal, a modulating means for converting a recording digital signal into a predetermined signal form, Recording means for recording the adjusted digital signal on a magnetic tape; and tape running means for running the magnetic tape at a first speed. The reproducing system is provided with a magnetic tape corresponding to the time axis compression ratio of the input digital signal. Tape running means for running at a second speed, playback signal detection means for detecting a playback signal from the magnetic tape, demodulation means for returning the modulated playback signal to the original digital signal form, and second error detection and correction Error detecting means for extracting a correct reproduced digital signal by a code, address detecting means for detecting an address signal, memory means for writing the correct reproduced digital signal to a predetermined area on a memory according to the address signal, and memory means. Error correction for correcting an error in the written digital signal for each predetermined unit using the first error detection and correction code Means, and time axis extending means for reading out the reproduced digital signal subjected to the error correction at a predetermined transmission rate, wherein the magnetic head records the digital signal recorded by one scan.
A helical scanning type recording / reproducing apparatus wherein the address signal is generated in units of four track information amounts or more when the track information amount is used. 3. The helical scan according to claim 1, wherein the predetermined unit to which the first error detection and correction code is added is a digital signal corresponding to the one track information. Type recording and reproducing device. 4. When the time axis compression ratio of the input digital signal is 1 / N, the second tape running speed in the tape running means is set to 1 / N of the first tape running speed. 2. The method according to claim 1, wherein
3. The helical scanning type recording / reproducing apparatus according to item 2 or 3. 5. A digital information signal which is supplied via a transmission path and compressed on a time axis is recorded, and reproduced at a tape running speed different from that at the time of recording, so that the transmission rate of the digital information signal at the time of reproduction is different from that at the time of recording. In a helical scanning type recording / reproducing apparatus having a different configuration, a first error detection and correction code is added to a recording system by adding a first error detection and correction code for each predetermined unit to an input digital signal supplied via a transmission path. Code adding means, address signal adding means for dividing the digital signal to which the error detection and correction code has been added into predetermined blocks and adding an address signal, and a second error detection and correction code for the digital signal to which the address signal has been added. A second error detection and correction code adding means for adding a digital signal, a modulating means for converting a recording digital signal into a predetermined signal form, Recording means for recording the adjusted digital signal on a magnetic tape; and tape running means for running the magnetic tape at a first speed. The reproducing system is provided with a magnetic tape corresponding to the time axis compression ratio of the input digital signal. Tape running means for running at a second speed, playback signal detection means for detecting a playback signal from the magnetic tape, demodulation means for returning the modulated playback signal to the original digital signal form, and second error detection and correction Error detecting means for extracting a correct reproduced digital signal by a code, address detecting means for detecting an address signal, memory means for writing the correct reproduced digital signal to a predetermined area on a memory according to the address signal, and memory means. Data amount detecting means for detecting the data amount of the stored reproduced digital signal, and a predetermined unit stored in the memory means Error correcting means for correcting the reproduced digital signal of each of the digital signals by using a first error detection and correction code, and time axis extending means for reading out the reproduced digital signal subjected to the error correction at a predetermined transmission rate. A helical scanning type recording / reproducing apparatus, wherein the second magnetic tape speed in the tape running means is controlled according to the data amount detection information of the data amount detecting means. 6. A digital information signal compressed via a time axis, which is supplied through a transmission path, is recorded and reproduced at a tape running speed different from that at the time of recording. A recording means for recording an input digital signal supplied via a transmission path, a tape traveling means for traveling a magnetic tape at a first speed during recording, and a magnetic tape. Means for running at a second speed according to the time axis compression ratio of the input digital signal during reproduction, reproduction signal detection means for detecting a reproduction signal from a magnetic tape, and reading the detected reproduction digital signal on a memory. Memory means for writing to a predetermined area;
Data amount detection means for detecting the data amount of the reproduced digital signal stored in the memory means, wherein the second magnetic tape speed in the tape traveling means of the reproduction system is used as the data amount detection information of the data amount detection means. A helical scanning type recording / reproducing apparatus characterized in that the recording / reproducing apparatus is controlled according to the helical scanning type.