JP3001341B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit.

[0002]

2. Description of the Related Art As shown in the circuit diagram of FIG. 4A, a conventional semiconductor integrated circuit forming an oscillation circuit has an external input terminal 51, a control signal input terminal 52, and an output terminal 53 corresponding to: It is provided with current limiting resistors 32 and 38, an inverter 33, a transfer gate 34, and an inverting amplifier 35 including a PMOS transistor 36 and an NMOS transistor 37.

In FIG. 4A, when an operation test of the semiconductor integrated circuit is performed, the oscillation operation of the oscillation circuit is stopped, and a stable clock signal waveform is input from the outside. In this case, in order to stop the oscillation of the oscillation circuit, the transfer gate 34 used as a feedback resistor is turned off by the test mode signal input from the control signal input terminal 52. As a result, the inverting amplifier 35 has a function merely as an inverter, and the clock signal input from the external input terminal 51 is inverted by the inverting amplifier 35 and output to the output terminal 53.
Output.

[0004]

In the above-mentioned conventional semiconductor integrated circuit, a test clock signal input from the outside is supplied to the current limiting resistors 32 and 38 in the inverting amplifier 35, the PMOS transistors 36 and NM.
Due to the resistance component including the OS transistor 37, the wiring capacitance, and the like, a state having a relatively large time constant is obtained as shown in the following equation.

Τ ₁ = C · r ₁ (1) r ₁ : resistance component including current limiting resistance C: capacitance component of resistance + drain capacitance of MOS transistor 4 shown from being in (b) show waveforms of the input signal and the output signal by the time delay tau ₁ above. That is,
For the time delay tau ₁ value due to the influence of the time constant is large, in the case of performing the operation test of the semiconductor integrated circuit, there is a disadvantage that it is difficult to perform successfully the test.

[0006]

In a semiconductor integrated circuit according to a first aspect of the present invention, a source is connected to a high potential side power supply, and a drain is connected to a high potential side of a predetermined inverting amplifier.
An S transistor, a first current limiting resistor connected in parallel between the source and the drain of the first PMOS transistor, a source connected to the drain of the first PMOS transistor, and a gate connected to the signal input terminal A second PMOS transistor having a drain connected to the output terminal; a drain connected to the output terminal; a gate connected to the signal input terminal;
A first NMOS transistor that forms the inverting amplifier together with an OS transistor;
A second NMOS transistor having a source connected to the source of the MOS transistor, a gate connected to the control signal input terminal, and a source connected to the lower potential power supply;
A second current limiting resistor connected in parallel between the drain and the source of the MOS transistor, a PMOS side gate connected to the control signal input terminal, and an NMOS side gate connected to the gate of the first PMOS transistor A transfer gate inserted between the signal input terminal and the output terminal, and an inverter having an input side connected to the PMOS side gate of the transfer gate and an output side connected to the NMOS side gate of the transfer gate. It is characterized by comprising.

In a semiconductor integrated circuit according to a second aspect of the present invention, a first PMOS transistor having a source connected to the high potential side power supply and a gate connected to the signal input terminal, and a source having the first PMOS transistor connected to the signal input terminal. A second PMOS transistor connected to the drain, the drain connected to the output terminal, a first current limiting resistor connected in parallel between the source and the drain of the second PMOS transistor, and a drain connected to the output terminal A first NMOS transistor having a gate connected to a control signal input terminal, a second current limiting resistor connected in parallel between a drain and a source of the first NMOS transistor, and a drain connected to the first NMOS transistor. 1 is connected to the source of the NMOS transistor, the gate is connected to the signal input terminal, and the source is connected to the low potential side power supply. A second NMOS transistor and a PMOS gate are connected to the control signal input terminal, and an NMOS gate is connected to the gate of the second PMOS transistor, and a second NMOS transistor is connected between the signal input terminal and the output terminal. A transfer gate to be inserted and connected;
The input side is connected to the PMOS side gate of the transfer gate, and the output side is NM of the transfer gate.
And an inverter connected to the OS-side gate.

Further, in the semiconductor integrated circuit according to a third aspect of the present invention, the first PMOS transistor having a source connected to a high potential side power supply and a drain connected to a high potential side of a predetermined inverting amplifier; A first current limiting resistor connected in parallel between the source and the drain of the PMOS transistor; and a second PM having a source connected to the drain of the first PMOS transistor and a gate connected to the signal input terminal.
An OS transistor, a source connected to the drain of the second PMOS transistor, and a gate connected to the first PMOS transistor;
A third PMOS transistor connected to the gate of the MOS transistor and having a drain connected to the output terminal;
A second current limiting resistor connected in parallel between a source and a drain of the third PMOS transistor, a first NMOS transistor connected to a drain of the output terminal and a gate connected to a control signal input terminal, The first N
A third current limiting resistor connected in parallel between the drain and the source of the MOS transistor;
A second NMOS transistor having a gate connected to the signal input terminal and a drain connected to the source of the second NMOS transistor, and a gate connected to the control signal input terminal; , The source of which is connected to the lower potential side power supply, the third NM
An OS transistor; a fourth current limiting resistor connected in parallel between the drain and the source of the third NMOS transistor; a PMOS gate connected to the control signal input terminal; 2nd P
A transfer gate connected to the gate of the MOS transistor and inserted between the signal input terminal and the output terminal; an input side connected to the PMOS side gate of the transfer gate; and an output side connected to the NMOS side of the transfer gate And an inverter connected to the gate.

[0009]

Next, the present invention will be described with reference to the drawings.

FIG. 1A is a circuit diagram showing a first embodiment of the present invention. As shown in FIG. 1A, in the present embodiment, the PMOS transistors 1 and 6 and the current limiting resistors 2 and 9 correspond to the external input terminal 51, the control signal input terminal 52 and the output terminal 53, respectively. , Inverter 3 and
A transfer gate 4, an inverting amplifier 5 including a PMOS transistor 6 and an NMOS transistor 7,
And a MOS transistor 8.

In FIG. 1A, when an operation test of the semiconductor integrated circuit is performed, a high-level test mode signal is input from a control signal input terminal 52 to stop the oscillation operation of the oscillation circuit. . As a result, the transfer gate 4 becomes inactive and the circuit is cut off. As a result, the role of the transfer gate 4 as a feedback resistor is stopped, and the inverting amplifier 5 including the PMOS transistor 6 and the NMOS transistor 7 enters a state of simply functioning as an inverter. Further, by the input of the test mode signal, both the PMOS transistor 1 and the NMOS transistor 8 become active and are turned on. Therefore, the PMOS transistor 1
And NMOS transistor 8 is turned on, so that current limiting resistors 2 and 9
By being bypassed by the transistor, the combined resistance has a relatively small numerical value, and in the present embodiment, the following (2)
The time constant τ ₂ shown in the equation is interposed.

Τ ₂ = C · r ₁ · r ₂ / (r ₁ + r ₂ ) (2) r ₁ : resistance component including PMOS transistor 1 and current limiting resistor 2 r ₂ : NMOS transistor 8 Resistance component including the current limiting resistor 9 C: capacitance component of the resistor + drain capacitance of the MOS transistor The value of the time constant τ _{1 in} the equation (1) is compared with the value of the time constant τ _{2 in} the equation (2). As is apparent, the value of the time constant τ ₂ is much smaller than the value of the time constant τ ₁ , and therefore, the time delay due to the time constant τ ₂ is smaller than that of the above-described conventional example. Is extremely small. FIG. 1 (b)
Shows the operation waveforms of the input signal and the output signal due to the above time delay τ _2, and the time delay due to the influence of the time constant τ ₂ is suppressed to an extremely small amount. Obstacles in performing are avoided.

Next, a second embodiment of the present invention will be described.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention. As shown in FIG. 2, in the present embodiment, the inverter 10 and the PMOS transistor 1 correspond to the external input terminal 51, the control signal input terminal 52, and the output terminal 53.
1, the current limiting resistors 12 and 15, the transfer gate 13, the NMOS transistor 14, the PMO
An inverting amplifier 16 including an S transistor 17 and an NMOS transistor 18 is provided.

As is clear from comparison with FIG. 1A, the difference between this embodiment and the first embodiment is that a parallel circuit of the PMOS transistor 11 and the current limiting resistor 12 in FIG. The only difference is the position where the transistor 14 and the parallel circuit of the current limiting resistor 15 are inserted and connected. Accordingly, the high-level test mode signal input from the control signal input terminal 52 stops the transfer gate 13 from functioning as a feedback resistor, and the inverting amplifier 16 becomes a simple inverter. Both the PMOS transistor 11 and the NMOS transistor 14 are turned on,
The current limiting resistors 12 and 15 are bypassed by the MOS transistors to reduce the equivalent time constant to a small value and suppress the delay time to a small amount, thereby avoiding a failure in performing an operation test of the circuit. The operation is exactly the same as in the first embodiment, and a description thereof will be omitted.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention. As shown in FIG. 3, in the present embodiment, PMOS transistors 19 and 22 correspond to an external input terminal 51, a control signal input terminal 52, and an output terminal 53.
, Current limiting resistors 20, 23, 26 and 31, inverter 21, transfer gate 24, NMO
It comprises S transistors 25 and 30 and an inverting amplifier 27 including a PMOS transistor 28 and an NMOS transistor 29.

As is clear from the comparison with FIG. 2, the difference between the present embodiment and the second embodiment is that, in FIG. A parallel circuit of the resistor 20 is inserted and connected, and a parallel circuit of the NMOS transistor 30 and the current limiting resistor 31 is similarly connected to the ground side of the inverting amplifier 27. Also in the third embodiment,
As in the case of the second embodiment, the function of the transfer gate 24 as a feedback resistor is stopped by the high-level test mode signal input from the control signal input terminal 52, and the inverting amplifier 27 becomes a simple inverter. Further, by the input of the test mode signal, the PMOS transistors 19 and 22 and the NMOS transistors 25 and 30 are all turned on, and the current limiting resistor 2
0, 23, 26 and 31 are respectively bypassed by the MOS transistors connected in parallel, the equivalent time constant becomes a small value, and the delay time is suppressed to a small amount. The effect of avoiding a trouble in performing is exactly the same as in the first and second embodiments.

[0018]

As described above, according to the present invention, a MOS transistor is connected in parallel with a current limiting resistor, and a transfer resistor for forming a feedback resistor of an oscillation circuit via a predetermined test mode signal at the time of testing a circuit operation. The gate is cut off to stop the oscillation, and the MO connected in parallel
By setting the S-transistor to the ON state, equivalent resistance can be reduced, distortion between input / output signals during test and delay time can be reduced, and favorable test environment conditions for the semiconductor integrated circuit can be obtained. This has the effect.

[Brief description of the drawings]

FIG. 1 is a circuit diagram and an input / output signal waveform diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention.

FIG. 4 is a circuit diagram and an input / output signal waveform diagram showing a conventional example.

[Explanation of symbols]

1, 6, 11, 17, 19, 22, 28, 36 PM
OS transistors 2, 9, 12, 15, 20, 23, 26, 31, 32,
38 Current limiting resistor 3, 10, 21 Inverter 4, 13, 24, 34 Transfer gate 5, 16, 27, 35 Inverting amplifier 7, 8, 14, 18, 25, 29, 30, 37 NM
OS transistor

Claims (3)

(57) [Claims] A first PMOS transistor having a source connected to a high-potential power supply and a drain connected to a high-potential side of a predetermined inverting amplifier; and a parallel connection between a source and a drain of the first PMOS transistor. A second PMOS transistor having a source connected to the drain of the first PMOS transistor, a gate connected to the signal input terminal, and a drain connected to the output terminal; A first NMOS transistor having a drain connected to the output terminal and a gate connected to the signal input terminal to form the inverting amplifier with the second PMOS transistor; and a drain connected to a source of the first NMOS transistor. , The gate is connected to the control signal input terminal, and the source is connected to the low potential side power supply. And NMOS transistors of the second current limiting resistor connected in parallel between the drain and the source of the second NMOS transistor, connected PMOS-side gate is the control signal input terminal,
An NMOS side gate connected to the gate of the first PMOS transistor, a transfer gate inserted and connected between the signal input terminal and the output terminal; and an input side connected to the PMOS side gate of the transfer gate; The output side is the NM of the transfer gate
And an inverter connected to the OS-side gate. 2. A first PMOS transistor having a source connected to a high potential side power supply and a gate connected to a signal input terminal, a source connected to a drain of the first PMOS transistor, and a drain connected to an output terminal. Second PM connected
An OS transistor, a first current limiting resistor connected in parallel between the source and the drain of the second PMOS transistor, a first current limiting resistor having a drain connected to the output terminal, and a gate connected to the control signal input terminal. An NMOS transistor, a second current limiting resistor connected in parallel between the drain and source of the first NMOS transistor, a drain connected to the source of the first NMOS transistor, and a gate connected to the signal input terminal. A second NMOS transistor having a source connected to the low-potential-side power supply; a PMOS-side gate connected to the control signal input terminal;
An NMOS side gate connected to the gate of the second PMOS transistor, a transfer gate inserted and connected between the signal input terminal and the output terminal; and an input side connected to the PMOS side gate of the transfer gate; The output side is the NM of the transfer gate
And an inverter connected to the OS-side gate. 3. A first PMOS transistor having a source connected to a high-potential power supply and a drain connected to a high-potential side of a predetermined inverting amplifier; and a parallel connection between a source and a drain of the first PMOS transistor. A first current limiting resistor, and a second PMOS transistor having a source connected to the drain of the first PMOS transistor and a gate connected to the signal input terminal.
A third PMOS transistor having a source connected to the drain of the second PMOS transistor, a gate connected to the gate of the first PMOS transistor, and a drain connected to the output terminal; A second current limiting resistor connected in parallel between the source and the drain of the third PMOS transistor; a first NMOS transistor having a drain connected to the output terminal and a gate connected to a control signal input terminal; A third current limiting resistor connected in parallel between a drain and a source of one NMOS transistor; a second current limiting resistor having a drain connected to the source of the first NMOS transistor and a gate connected to the signal input terminal;
A third NMOS transistor having a drain connected to the source of the second NMOS transistor, a gate connected to the control signal input terminal, and a source connected to the low potential side power supply.
A transistor; a fourth current limiting resistor connected in parallel between the drain and the source of the third NMOS transistor; and a PMOS gate connected to the control signal input terminal;
An NMOS side gate is connected to the gates of the first and second PMOS transistors, and a transfer gate inserted and connected between the signal input terminal and the output terminal; and an input side is connected to the PMOS side gate of the transfer gate. Connected and the output side is the NM of the transfer gate.
And an inverter connected to the OS-side gate.