JP2858622B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a MOSFET (Metal Oxide Semiconductor Field Ef).
fect Transistor).

[0002]

2. Description of the Related Art A power supply voltage of a MOSFET tends to decrease as the device is miniaturized, and accordingly, a threshold voltage must be reduced. However, if the impurity concentration of the substrate is increased to prevent the punch-through phenomenon, the threshold voltage also increases. Therefore, impurities of the conductivity type opposite to that of the substrate are introduced into the surface of the substrate, and the apparent appearance is increased. The threshold voltage was lowered. However, in this case, there is a problem that the apparent threshold voltage decreases, but the drain current (leakage current) value when the gate voltage is 0 V increases.

Accordingly, the present inventor has disclosed in Japanese Patent Application No. Hei.
In the application No. 7, by burying a region having a conductivity type opposite to the conductivity type of the well under the gate, the gate voltage required to lower the drain current value by one digit in the region below the threshold voltage is reduced. A semiconductor device having a reduced S coefficient and a method of manufacturing the same have been proposed. This semiconductor device is shown in FIG. 11 and will be described briefly.

In this MOSFET, there is a region I having the same conductivity type as that of the substrate 1 below the gate electrode 5, and below the region I,
There is a region II having the opposite conductivity type to the substrate 1. Further, between the region II and the source region 2 and between the region II and the drain region 3, there are regions III having the same conductivity type as the substrate 1, respectively. Note that the substrate 1 is a region IV. Therefore, if the substrate 1 is p-type, the regions I, III, and IV are p-type, and the region II, the source region 2, and the drain region 3 are n-type. When the substrate 1 is n-type, the conductivity types are opposite to each other.

The width W1 of the region I in the depth direction is smaller than the sum of the width Wg of the depletion layer caused by the gate voltage and the width Wj1 of the depletion layer caused by the junction of the region II (W1 <Wg + W).
j1), the width W2 in the depth direction of the region II is arbitrary. As a result, region I is in an inverted state during operation, becomes a channel region in charge of carrier conduction, and the threshold voltage of this MOSFET is controlled by the impurity concentration of region I. Further, since the region II has a pn junction with the region I, the region I is depleted by this junction. Therefore, the region II helps to deplete the region I when a voltage is applied to the gate electrode 5, and reduces the apparent capacitance as seen from the gate electrode 5. At the same time, the threshold voltage is reduced.

[0006]

SUMMARY OF THE INVENTION The above-mentioned Japanese Patent Application No. Hei.
In the '08867 application, the density of the region II and the width in the depth direction may be set to arbitrary values. However, if the density of the region II is made sufficiently high and the width in the depth direction is made sufficiently large, the region II can be obtained. Is not depleted, the depletion layer of the channel in the region I stops in the region II, and there is a problem that the electric field of the gate electrode does not spread any more and the capacitance does not sufficiently decrease. Accordingly, an object of the present invention is to provide a semiconductor device that can be sufficiently reduced in capacity by manufacturing under the condition that the region II is completely depleted, whereby the depletion layer extends to the substrate (region IV). And

[0007]

As a means for achieving the above object, a gate electrode formed on a semiconductor substrate having a first conductivity type with a thin gate insulating film interposed therebetween, and a gate electrode formed below the gate insulating film. A source region and a drain region having a second conductivity type provided on both sides of the gate electrode, wherein the gate insulating film, the source region, and the drain region are provided below the gate insulating film. A second region having a second conductivity type formed in the substrate so as not to be in contact with the substrate; and a second region having a first conductivity type formed between the gate insulating film and the second region. A first region formed between the second region having the first conductivity type and the source region and the drain region, and a depletion layer width formed by the source region; Pn with area A third region having a width larger than the sum of the width of the depletion layer formed by the combination and the width of the depletion layer formed when a voltage is applied to the gate electrode. The width of the second region is smaller than the total width of the depletion layer formed in the first region by the pn junction with the second region, and the width of the second region is smaller than the total width of the depletion layer.
A semiconductor device is provided which is smaller than the sum of the width of a depletion layer formed in the second region by an n-junction and the width of a depletion layer formed by a pn junction with the substrate to be a fourth region. What you want to do.

[0008]

As a result of various experiments, the present inventor has found that the region II is completely depleted by changing the amount of impurities to be introduced when forming the region II, and sometimes not. It turns out. Therefore, if the region II is completely depleted with an appropriate amount of implanted impurity, the S coefficient decreases and the capacity of the semiconductor device can be sufficiently reduced. Hereinafter, this will be described in detail in Examples.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to explain one embodiment of the semiconductor device of the present invention, a MOS device as shown in FIG.
An FET was manufactured and experiments were performed. MO whose configuration is shown in FIG.
The SFET is a MOSFET having an LDD structure,
Its characteristics are described in the serial number 40501060 filed earlier.
No. "Semiconductor device" (filed on Nov. 9, 1993).

The structure of this MOSFET will be briefly described. Non-conductive side spacers 16 are provided on both sides of the gate electrode 15, and have the same conductivity type as the substrate 11 under the gate electrode 15 via the gate oxide film 14. There is a region I having.
Then, there is a region II having a conductivity type opposite to that of the substrate 11 therebelow. A region III having the same conductivity type as the substrate 11 is provided between the region II and the source region 12 and between the region II and the drain region 13. Further, an LDD region 17 is formed between the region I and the source region 12 and between the region I and the drain region 13. Note that the substrate 11 is a region IV. Therefore, if the substrate 11 is p-type, the regions I, III, and IV are p-type,
The region II, the source region 12, the drain region 13, and the LDD region 17 are n-type. When the substrate 11 is n-type, the conductivity types are opposite to each other.

FIG. 2A shows a method of manufacturing this MOSFET.
This will be described together with (F). First, as shown in FIG. 1A, a gate oxide film 14a having a thickness of 500 A (angstrom) is formed on the surface of a p-type substrate 11 having an impurity concentration of 1.5 × 10 ¹⁶ cm ⁻³ , which is a region IV. This gate oxide film 14a
B (boron) is injected into the substrate 11 through the injection voltage 25 KeV,
After injection at an injection amount of 4 × 10 ¹² cm ⁻² , P (phosphorus) is
When implantation is performed with an implantation voltage of 0 KeV and an appropriate implantation amount, a layer 18 in which B is implanted as a region I is formed below the gate oxide film 14a, and a layer 18 in which P is implanted as a region II is implanted thereunder. Layer 19 is formed. The heat treatment of the impurity is performed simultaneously with the heat treatment for activating the source region 12 and the drain region 13 described later, thereby forming the regions I and II.

Then, as shown in FIG.
After the implantation, the gate oxide film 14a is removed, the gate oxide film 14 is reattached, a polysilicon thin film is formed, and this is etched to form a gate electrode 1 of 0.4 μm.
5 is formed. Further, as shown in FIG. 2C, B is implanted into the depth position where the region II was formed at an implantation voltage of 40 KeV and an implantation amount of 5 × 10 ¹² cm ⁻² by using the gate electrode 15 as a mask, and the region III was implanted. To form After that, as shown in FIG. 3D, the gate electrode 15 is used as a mask and the injection voltage 25 is applied.
As is implanted with KeV at an implantation amount of 4 × 10 ¹³ cm ⁻² , an n ⁻ layer 20 serving as the LDD region 17 is formed on the surface side of the layer 18 into which B has been implanted.

Then, as shown in FIG. 1E, a side spacer 16 is formed. This side spacer 16
It can be formed by forming an SiO ₂ film over the entire surface and performing anisotropic etching such as RIE. In this state, as shown in FIG. 4F, the gate electrode 15 and the side spacer 16 are used as a mask, and the injection voltage is 50 KeV.
As is implanted at a dose of 1 × 10 ¹⁵ cm ⁻² to form an n ⁻ layer 2
The source region 12 and the drain region 13 are formed outside the lower side of the side spacer 16 in the layer 18 into which 0 and B are implanted. Finally, by performing a heat treatment at 900 ° C. for 40 minutes, the MOSFET as shown in FIG. 1 can be manufactured.

FIG. 3 is a sectional view showing the impurity concentration of the MOSFET thus manufactured. Note that the gate width in the direction perpendicular to the paper is 30 μm, and
The impurity implantation amount of phosphorus (P) implantation when forming
× 10 ¹² cm ^-2 . As shown in the figure, the region I, the source region 12 and the drain region 13
Formed up to a depth of 0.1 μm from the surface,
The regions II and III are formed to a depth below 0.2 μm.

FIG. 4 is a graph showing an impurity profile in the depth direction of the channel portion.
The vertical axis of this graph is a logarithmic representation of the impurity concentration, and the horizontal axis is the depth. 3 and FIG. 3, the peak formed up to a depth of 0.1 μm corresponds to the region I
Indicates the concentration of the p-type impurity of the following 0.1 to 0.2.
It can be seen that the peak between μm indicates the concentration of the n-type impurity in the region II, and the portion deeper than that indicates the concentration of the p-type impurity in the substrate 11 (region IV). It can be confirmed that the region is formed.

FIG. 5 shows a potential profile when the gate electrode 15 is at 0V. The vertical axis in the figure is voltage, and the horizontal axis is depth. From the figure, it can be seen that the voltage changes from the surface to a depth of about 0.35 μm (depletion layer), which indicates that the n-type region II
It can be seen that the depletion layer also spreads to the portion 11 and reaches the substrate 11 (region IV).

FIG. 6 shows a drain current-gate voltage characteristic when the drain voltage is 0.05 V, and FIG. 7 shows a logarithmic representation of the drain current. From FIG. 6, it can be seen that the threshold voltage is a small value of about 0.4 V, and from the slope of the graph of FIG.
It turns out that it is 0.3 mV / dec. This value is the normal MO
Despite being extremely small as compared to the SFET and having a low threshold voltage, the leakage current, which is the drain current when the gate electrode 15 is 0 V, is about 25.1 pA, which is very low at 1 pA or less per 1 μm of gate width. Has a small value.

However, when the impurity implantation amount of phosphorus at the time of forming the region II is 5 × 10 ¹² cm ⁻² , as can be seen from the potential profile when the gate electrode 15 is at 0 V shown in FIG. It can be seen that the voltage is stable between 0.1 and 0.2 μm, and that the depletion layer does not reach the substrate 11. As a result, when examining the S coefficient, it was about 110 mV / d
It was a very large value of ec.

On the other hand, if the impurity implantation amount of phosphorus at the time of forming the region II is 3 × 10 ¹² cm ⁻² , as can be seen from the potential profile when the gate electrode 15 shown in FIG. Although the voltage changes between 0.1 and 0.3 μm, the voltage is stable near the depth of 0.05 μm, and the region II is depleted, but the region I is not completely depleted. You can see that. As a result, the characteristic is a normal M
It was the same as the OSFET, and the S coefficient was a deteriorated value of about 90 mV / dec.

Here, the horizontal axis indicates the amount of phosphorus to be implanted when forming the region II, and the vertical axis indicates the S coefficient. As shown in FIG. 10, the S coefficient is obtained at a certain phosphorus injection amount. Is low, it can be seen that there is an optimum injection amount for obtaining a MOSFET having a low threshold voltage and a low leakage current. In the case of this MOSFET, (3.6 to
4.4) × 10 ¹² cm ⁻² . The range of the implantation amount is a range of the amount in which the region I and the region II are completely depleted. At this time, the S coefficient becomes a low value and the MOS
The capacity of the FET is reduced. The sum of the depths of the region I and the region II is smaller than the depth (width) of the depletion layer.

Therefore, the conditions of each region in the MOSFET which is one embodiment of the semiconductor device of the present invention shown in FIGS. 1 and 3 are as follows. The width W in the depth direction of the region I
1 is the depletion layer width Wg due to the gate voltage and the p of the regions I and II.
It is smaller than the sum of the width Wj1a of the depletion layer formed in the region I by the n-junction (W1 <Wg + Wj1a). Area II
The width W2 in the depth direction of the region is determined by the pn junction of the regions I and II.
II is smaller than the sum of the depletion layer width Wj1b formed in II and the depletion layer width Wj2 due to the pn junction of the regions II and IV (W2
<Wj1b + Wj2). The width W3 in the depth direction of the region III is
The width in the depth direction W2 of II is made larger (W3> W2).
The lateral width W13 of the region III is determined by the depletion layer width Wd of the source region 12 of the region II and the depletion layer width Wj3 of the junction between the region II.
(W13> Wd + Wj3). Further, as a desirable condition, the substrate concentration N4 in the region IV is made lower than the concentrations N1, N2, and N3 in all the other regions I, II, and III (N4 <N1, N2, and N3).

Then, according to these conditions, the following is obtained. The region I is in an inverted state during operation and becomes a channel region in charge of carrier conduction. The threshold voltage of the MOSFET is controlled by the impurity concentration of the region I. Region II is composed of region I and substrate 11 (region I
V) and pn junction, respectively, so that region I and region II
This junction and the vicinity of the surface of the region IV are depleted by this junction. Therefore, the region II promotes depletion when a voltage is applied to the gate electrode 15 and reduces the apparent capacitance seen from the gate electrode 15. At the same time, the threshold voltage is reduced.

The region III prevents the depletion layer of the source region 12 from expanding and the region II from conducting to the source region 12. Further, the region III connects the region I and the region IV to stabilize the potential of the region I. The impurity concentration of the region IV determines the capacitance of the source region 12 and the drain region 13. Since the punch-through is prevented in the region III, the impurity concentration in the region IV can be determined without taking this into account. The impurity concentration in the region IV is reduced to reduce the capacitance of the source region 12 and the drain region 13.

[0024]

According to the semiconductor device of the present invention, the width of the first region is set in the first region by the pn junction between the width of the depletion layer formed when a voltage is applied to the gate electrode and the second region. The width of the second region is smaller than the sum of the width of the depletion layer formed, and the width of the second region is smaller than the width of the depletion layer formed in the second region by a pn junction with the first region. Pn with substrate to be
Since the width is smaller than the sum of the width of the depletion layer due to the junction, the depletion layer extends to the substrate, and the capacity of the semiconductor device can be sufficiently reduced. As a result, there is an effect that the leakage current becomes low at a low threshold voltage.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of a semiconductor device of the present invention.

FIGS. 2A to 2F are process diagrams showing an example of a method for manufacturing a semiconductor device.

FIG. 3 is a cross-sectional view showing one embodiment of the semiconductor device of the present invention.

FIG. 4 is a graph showing an impurity profile in a depth direction of a channel portion.

FIG. 5 is a graph showing a potential profile when an impurity implantation amount of phosphorus is set to 3.8 × 10 ¹² cm ⁻² .

FIG. 6 is a graph showing drain current-gate voltage characteristics.

FIG. 7 is a graph showing drain current-gate voltage characteristics.

FIG. 8 is a graph showing a potential profile when an impurity implantation amount of phosphorus is set to 5 × 10 ¹² cm ⁻² .

FIG. 9 is a graph showing a potential profile when an impurity implantation amount of phosphorus is set to 3 × 10 ¹² cm ⁻² .

FIG. 10 is a graph showing a relationship between an impurity implantation amount of phosphorus and an S coefficient.

FIG. 11 is a configuration diagram showing a conventional example.

[Explanation of symbols]

Reference Signs List 1,11 substrate 2,12 source region 3,13 drain region 4,14,14a gate insulating film 5,15 gate electrode 16 side spacer 17 LDD region 18B implanted layer (region I) 19P implanted layer (region II) 20 n ^- layer

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 29/78

Claims (1)

(57) [Claims] 1. A gate electrode formed on a semiconductor substrate having a first conductivity type with a thin gate insulating film interposed therebetween, and second conductive layers provided below the gate insulating film and on both sides of the gate electrode. Source and drain regions having a mold;
A second region having a second conductivity type formed in the substrate below the gate insulating film so as not to contact the gate insulating film and the source region and the drain region. A first region having a first conductivity type and formed between the gate insulating film and the second region; and a second region having a first conductivity type and the second region. A depletion layer width formed by the source region and a pn region between the second region and a depletion layer formed between the source region and the drain region, respectively.
A third region having a width larger than the sum of the width of the depletion layer due to the junction; and a width of the depletion layer formed when a voltage is applied to the gate electrode. The width of the second region is smaller than the sum of the width of a depletion layer formed in the first region due to the pn junction with the second region, and the width of the second region is smaller than that of the first region.
A width of a depletion layer formed in the second region by a pn junction with the region and a width of a depletion layer by a pn junction with the substrate to be a fourth region. Semiconductor device.