JP2785075B2 - Pulse delay circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse delay circuit used for various pulse circuits.

[0002]

2. Description of the Related Art It is conventionally known to use a semiconductor circuit as a pulse delay circuit for delaying a pulse signal by a desired time. By continuously connecting, for example, a circuit called a gate of a semiconductor circuit to a desired number of stages, a delay time corresponding to the number of connected stages can be obtained.

On the other hand, when the scale of the apparatus is increased, such as an IC test apparatus, there is a disadvantage that the entire power consumption increases. Therefore, for the purpose of reducing the power consumption of the device, it is conceivable that the entire device is configured by a MOS type IC. The MOS type IC consumes a small amount of power regardless of whether the switch element is on or off, and consumes the most power when the switch element is inverted from on to off or from off to on. With such characteristics, power consumption can be reduced if the entire device is constituted by a MOS-type IC.

[0004]

When the circuit of the entire device is constituted by a MOS IC for the purpose of reducing the power consumption of the device, and especially when the delay circuit is constituted by a MOS IC, the MOS circuit is described above. As described above, since power is consumed every time the on / off inversion operation is performed, the temperature inside the IC tends to increase in proportion to the inversion operation.

[0005] For this reason, if the input pulse signal to be delayed during operation is missing, the temperature inside the IC fluctuates, which causes a disadvantage that the delay time fluctuates. SUMMARY OF THE INVENTION It is an object of the present invention to suppress a fluctuation in power consumption inside an IC and prevent a delay time from fluctuating even when the number of pulses to be delayed fluctuates when a delay circuit is constituted by a MOS type IC. It is an object of the present invention to provide a pulse delay circuit.

[0006]

According to the present invention, a MOS type I is provided.
In the delay circuit constituted by C, the power consumption is in the same semiconductor chip as the MOS type IC constituting the delay circuit.
A delay circuit comprising a pseudo-circuit that performs the same operation as a delay circuit, and a pulse correction circuit that detects a missing tooth of a pulse signal to be delayed and provides the pseudo-circuit with a number of pulses corresponding to the missing tooth. It is.

According to the configuration of the present invention, when the pulse applied to the delay circuit is missing, the number of pulses corresponding to the missing is applied to the pseudo circuit. As a result, fluctuations in power consumption in the semiconductor chip of the MOS IC constituting the delay circuit can be suppressed, and fluctuations in the delay time can be prevented.

[0008]

FIG. 1 shows an embodiment of the present invention. In the drawing, reference numeral 1 denotes a MOS type IC. The MOS type IC 1 operates in the same manner with respect to the delay circuit 2 and the delay circuit 2 in terms of power consumption.
And a pseudo circuit 3 which is formed. Delay circuit 2 performs an operation of delaying pulse signal P _B (FIG. 2B) applied to input terminal 5 for a predetermined time and outputting it to output terminal 6.

In the present invention, a pulse correction circuit 4 is provided.
The pulse correction circuit 4 detects that the input pulse signal P _B to be inputted to the delay circuit 2 and missing teeth, an operation which gives the number of pulses corresponding to the number of pulses missing teeth pseudo circuit. The pulse correction circuit 4 includes two D-type flip-flops 4A and 4B, a delay element 4C for delaying the reference clock P _A (FIG. 2A) for a predetermined time, and an output signal P _D of the D-type flip-flop 4B (FIG. 2D). Is controlled by opening and closing,
An AND gate 4D for taking out the signal P _E (FIG. 2E) delayed by the delay element 4C, and receiving an input pulse P _B by D
And an inverter 4E that informs the type flip-flop 4A.

[0010] The data input terminal D of the D-type flip-flop 4A give H logic voltage and the trigger input terminal providing a reference clock P _A shown in Figure 2A. The reset terminal of the D-type flip-flop 4A has an inverter 4E.
Providing an input pulse signal P _B through. The data input terminal D of the next-stage D-type flip-flop 4B, provides an output terminal of the front stage D-type flip-flop 4A, the trigger input terminal, provides a reference clock P _A.

With this configuration, the D in the preceding stage
Type flip-flop 4A, every time the reference clock P _A is input, reads the H logic applied to data input terminal D. Simultaneously, the D-type flip-flop. 4A D-type flip-flop 4A for the input pulse signal P _B is input to the reset terminal every time the input pulse signal P _B is input is reset.

Therefore, in the state where the input of the input pulse signal P _B is continued (period T ₁ shown in FIG. 2), the reset of the preceding D-type flip-flop 4A is repeated by the input pulse signal P _B. Therefore, the next stage D-type flip-flop 4
B while the input pulse P _B is continuously input has no read no chance logic H, the D-type flip-flop 4B
The output of is maintained at logic L, as shown in the period T ₁ shown in FIG. Therefore, the AND gate 4D is maintained in the closed state.

On the other hand, when the input pulse signal P _B is extracted (the period T ₂ shown in FIG. ₂ ), the D-type flip-flop 4A in the preceding stage is not reset only during the period of the missing tooth. Therefore preceding D in synchronism with the rising of the next-stage D-type flip-flop 4B In the period T ₂ are reference clock P _A
It reads the H logic output of the type flip-flop 4A and outputs a pulse P _D to its output.

When the pulse P _D is output, the AND gate 4D is controlled to be opened, and a pulse P _E delayed for a predetermined time by the delay element 4C is extracted and output as a pulse P _F. Pulse P _F outputted from the AND gate 4D corresponds to the number of pulses input pulse signal P _B were missing by omission teeth. That is, in the example shown in FIG. 2 one pulse P _F from the AND gates 4D if the input pulse signal P _B is one pulse as shown by the dotted line and missing teeth is output.

[0015] Since the pulse P _F number corresponding to the input pulse signal P _B tooth disconnect this way AND gate 4D is output, applied to the delay circuit 2 by inputting the pulse P _F pseudo circuit 3 the number sum of the pulses applied to the number and the pseudo circuit 3 pulses is constant as far as a relatively long synchronization in a unit time (2-3 cycles of the reference clock P _a). A pulse B shown in FIG. 2G indicates a pulse input to the delay circuit 2, and A indicates a pulse input to the pseudo circuit 3. Total M = 10 of these pulses A and B are approximated to the number N = 11 of the reference clock P _A shown in FIG. 2H.

[0016]

As described above, according to the present invention, the sum of the numbers of pulses input to the delay circuit 2 and the pseudo circuit 3 is constant within a unit time. Therefore the amount of power consumed by the delay circuit 2 and the pseudo circuit 3 is suppressed to a constant value irrespective of the teeth disconnect the input pulse signal P _B. Therefore, even if generated omission teeth prematurely input pulse signal P _B to be delayed according to the present invention, the input pulse signal P _B produced by the toothless
Is supplemented by the pseudo circuit 3. As a result, the power consumption in the MOS type IC 1 is maintained at a constant value, the temperature in the semiconductor chip forming the delay circuit 2 and the pseudo circuit 3 is maintained at a constant value, and the delay time of the delay circuit 2 does not fluctuate. become.

Therefore, a delay circuit is constituted by using a MOS type IC, and even if the number of incoming input pulse signals P _B fluctuates,
A delay circuit in which the delay time does not change can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a waveform chart for explaining the operation of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 MOS type IC 2 Delay element 3 Pseudo circuit 4 Pulse correction circuit 5 Input terminal 6 Output terminal

Claims (1)

(57) [Claims] 1. A. First Embodiment B. A delay circuit that delays an input pulse signal by a MOS semiconductor circuit for a predetermined time; It is provided in a semiconductor chip constituting the MOS type semiconductor circuit and has the same power consumption as the delay circuit.
B. a pseudo-circuit that operates ; A pulse correction circuit for detecting a missing tooth of an input pulse signal applied to the semiconductor circuit and providing a number of pulses corresponding to the missing tooth to the pseudo circuit.