JP2771155B2 - Recording device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a recording apparatus, and more particularly, to an apparatus for recording a video signal by forming a plurality of tracks on a recording medium.

[0002]

2. Description of the Related Art FIG. 5 is a diagram showing a schematic configuration of a conventional general digital video tape recorder (DVTR).

Referring to FIG. 5, an operation at the time of recording will be described first. The input image signal is converted into digital data by the A / D converter 30 and redundant data is deleted by the encoder 31 using the correlation of the images.

[0004] Next, an error correction code (ECC) as an error countermeasure for a recording medium is encoded by an ECC encoding circuit 32.
Then, digital code modulation 33 is performed so as to obtain a signal spectrum distribution suitable for magnetic recording and reproduction. Thereafter, recording is performed on the magnetic tape 36 via the recording amplifier 34 and the recording head 35.

At the time of reproduction, video data recorded on a magnetic tape 36 is reproduced through a reproduction head 37, a head amplifier 38, and a digital demodulator 30. In the signal at this stage, a code error relating to the recording medium due to dust, scratches and the like described above has occurred. Therefore, the ECC decoder 40 performs processing such as error correction. Next, redundant information such as a synchronization signal is added, and the decoder 41 almost completely restores the input information. Finally, the analog image signal similar to the input image information can be restored by the D / A converter 42.

[0006] In recent years, many DVTRs having the above-described configuration have been developed, but most of these recording track patterns constitute a single screen with a plurality of tracks as shown in FIG. For example, the first field in the track T ₁ through T ₃ in FIG. 6, the track T ₄ through T ₆ the video signals of the second field are recorded.

In general, the number of tracks formed for one field of video signal is generally an integral number. This is due to the advantage of taking into account the DVTR synchronous operation, splicing, editing, and variable speed playback.

[0008]

In recent years, the technology of high-efficiency encoding of image data has been developed at a rapid pace mainly in the field of communications such as video conference systems and TV telephones.

[0009] In consideration of the above points, a high-efficiency image coding technique developed in the communication field is applied to the D-code.
It is possible to extend the recording time of a VTR even a little, and it is expected to be practiced in the future.

However, in order to record data which has been further compressed by high-efficiency coding at as high a density as possible,
The screen switching position of video data recorded on a recording medium may not be constant on a recording track. In this case, it becomes extremely difficult to input / output the video data of the DVTR in units of fields or frames. this is,
As described above, this leads to difficulties such as synchronous operation, splicing and editing of the DVTR.

On the other hand, if one field and one frame of video data are always recorded on an integral number of tracks, for example, one field of video data is compressed until it can be recorded on 2.1 tracks. Even if you can do it,
Eventually, three tracks must be prepared for one field of video data, which hinders high-density recording.

The present invention has been made under such a background, and when a plurality of synchronous blocks are formed from input video data and recorded on a recording medium, a screen switching position on a track can be easily identified. The purpose is to:

[0013]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems and to achieve the object, the present invention is an apparatus for recording video data by forming a large number of tracks on a recording medium. Means for dividing each screen into a plurality of blocks, means for generating identification data indicating the block corresponding to the screen switching portion of the video data, and a block corresponding to the screen switching portion among the plurality of blocks. Recording processing means for adding the identification data and adding synchronization data to the plurality of blocks to generate a plurality of synchronization blocks and obtaining recording data including the plurality of synchronization blocks; And a recording means for recording the recording data so that the screen switching position differs between the tracks.

(Operation) With this configuration,
When recording video data as multiple sync blocks,
Regardless of where the screen switching position is on the track, this can be easily identified.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments.

FIG. 1 is a diagram showing a schematic configuration of a digital data recorder as one embodiment of the present invention, FIG. 2 is a diagram showing an arrangement of cylinders and heads of the data recorder of this embodiment, and FIGS. (B) and (c) are diagrams for explaining the recording format of the present embodiment, and FIG. 4 is a diagram showing a memory space of the present embodiment.

In FIG. 1, reference numeral 1 denotes an input terminal for a digital signal to be recorded. Reference numeral 2 denotes a clock generator, and the clock generated by the clock generator 2 is frequency-divided by the frequency divider 4 at a frequency division ratio set in advance according to the data amount of input data. The memory control circuit 5 includes the clock generator 2
The write clock and the write enable signal are supplied to the RAM 7 using the output clock of (1) as a write clock. In this way, data indicating the input digital signal is written into the RAM 7. The drum control circuit 8 controls the rotation of the drum so that the (200/3) Hz rectangular wave signal output from the drum rotation detector 13 and the (200/3) Hz signal output from the frequency divider 4 are synchronized. I do.

The digital data recorder (DD) of this embodiment
R) includes three adjacent heads Ha and H, as shown in FIG.
The magnetic tape 21 is wound around a rotary drum 20 having three heads Hd, He, and Hf which rotate with a phase difference of 180 ° with respect to b, Hc and 180 ° or more. Then, recording is performed on the magnetic tape by the total of six heads.

The heads Ha, Hb, and Hc are configured to rotate while being shifted from each other by a predetermined distance in the direction of the rotation axis, and the shift amount is set according to the recording track pitch.
The same applies to the heads Hd, He, Hf.

Now, the rotational speed of the head is set to 4000 rpm,
Assuming that the input data is image data having a vertical synchronization frequency of 60 Hz, the head is set to 10/9 for one vertical synchronization cycle.
It will rotate. Since the head is mounted in the configuration shown in FIG. 2, the track pattern on the tape is shown in FIG.
As shown in (c), recording / reproduction of data is performed for six tracks per rotation.

FIG. 3A shows a recording data format for one track in the present embodiment, in which a data string is formed one line at a time from the upper left to the upper right in FIG.
It becomes serial data for the track. FIG. 3B simply shows this, and the left-to-right direction of the data sequence of this one track matches the oblique direction from the lower right to the upper left of each track in FIG. 3C. .

In this case, if the line indicated by (A) in FIG. 3A is the vertical synchronization position of the input image data,
The recording data area shown in FIG.
(C) also corresponds to an area. In this embodiment, since the vertical synchronization position appears every 10/9 rotations of the head, the vertical synchronization position is set in the tape width direction as shown in the positions (B) and (C) of FIG. It is not a fixed position, and it is difficult to determine on which track the track exists.

In FIG. 3 (a), one line of data is divided in half in the horizontal direction on the tape, and a sub-block (Sub Block) 0 and a sub-block (Sub B) are respectively provided.
As a lock 1, a parity C 1 of an error correction code for correcting a data error on the tape is added. Further, just before Sub Blocks 0 and 1, a sync pattern Sync for block synchronization and ID data for block identification are added by the ID word adding circuit 10 in FIG. Vertically 85 to further enhance error correction
Parity C2 of error correction code for 4 lines per line
Is added. The ID data includes a block number indicating the position of the vertical line where the block exists in the format shown in FIG. V data indicating whether or not the current block is the first block from the vertical synchronization position. These block numbers and V data are the clock output from the clock generator 2, P
Based on the clock output from the LL circuit 6 and the vertical synchronizing signal of the input image signal from the terminal 9, the memory control circuit 5
Is formed.

The memory control circuit 5 supplies a read enable signal and a read address to the RAM 7 using the clock output from the PLL circuit 6 as a read clock, so that reading from the RAM 7 is performed. The data read from the RAM 7 is distributed to the three recording systems in data block units, and the above-described C1, C2 parity and Sync are stored.
Error correcting encoders (ECC, EN) 11a, 1
1b, 11c, and a digital modulator (MOD) 12
a, 12b, 12c, switches SW1, SW2, SW3
Is supplied to each head via the R terminal. As shown, heads Ha and Hd, heads Hb and He, heads Hc and Hf
Are print heads of the same system.

Next, the reproducing system will be described. Reproduction signals of three systems reproduced by each head are provided by switches SW1 and SW
2. Digital demodulator (DEM) via P terminal of SW3
After demodulation at 14a, 14b and 14c, error correction decoders (ECC, DE) 15a, 15b and 15c perform C1, C
Error correction by two parity is performed, and RA
It is written to M7 '.

FIG. 4 is a diagram showing a data storage area of the RAM 7 '. The horizontal direction corresponds to data for exactly one track. Each data shown in FIG. 4 ~, (A) ~ (C)
Are also indicated by the same symbols in FIG. 3 (c).

Now, consider a case where data is output in synchronization with an external vertical synchronizing signal during reproduction, for example. At this time, the vertical synchronizing position (A) is I indicating the block number in the reproduction signal.
It can be known from the D data and the V data included therein. That is, the line number containing the V data, that is, the horizontal offset amount shown in FIG. 4A can be recognized. Accordingly, the object is achieved by sequentially reading out the RAM 7 'shown in FIG. 4 by adding the offset amount (a) as a read address in synchronization with the external vertical synchronizing signal.

That is, the block number is extracted by the ID word extraction circuit 16 in FIG. 1, and the write address of the memory is controlled. The offset amount (A) is extracted by the memory control circuit 5 'from the V data extracted at the same time. An external vertical synchronizing signal for reading is input from a terminal 9, and in synchronism therewith, reading is performed from the address of the offset amount (a), whereby reproduction signal data synchronized with the external vertical synchronizing signal is output from a terminal 17.

In the above embodiment, for simplicity of explanation, the RAM 7 in the recording system and the RAM 7 'in the reproducing system are described.
However, in practice, the memory control circuits 5, 5 'may be commonly used.

In the above-described embodiment, since a video signal synchronized with any external vertical synchronizing signal can be reproduced, operations such as synchronous operation and editing of two DVTRs can be easily performed.

Lastly, a brief description will be given of a case where the above-described embodiment is applied to splice shooting. When the pause switch is pressed, data is stored in the RAM 7 'as shown in FIG. At this time, it is assumed that the RAM is shared with the RAM 7 of the recording system. The tape is once rewound for a predetermined length, and is conveyed at a speed for normal recording and reproduction while performing tracking control.

Next, a signal recorded at the timing when each head starts tracing three tracks including (A) in FIG.
The data is not read from the RAM 7 until the read timing comes, and the data to be recorded is read from the RAM 7 at the address according to the block number after the above timing. At this time, if data is written in synchronization with the vertical synchronizing signal of the input image signal from the address according to the offset amount (a) described above, the continuous shooting can be performed.

In order to make the video data to be recorded correspond to an arbitrary screen switching position on the track, the write address may be offset.

[0034]

As described above, according to the present invention, identification data indicating a block corresponding to a screen switching portion of input video data is generated, and this identification data is added to a block corresponding to the screen switching portion to generate a plurality of synchronization data. Recording data consisting of blocks is obtained, and this recording data is recorded on a large number of tracks so that the screen switching position differs between tracks. Therefore, this can be easily performed regardless of the screen switching position on the track. Can be identified.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic configuration of a digital data recorder as an embodiment of the present invention.

FIG. 2 is a diagram showing the arrangement of cylinders and heads of the digital data recorder of FIG.

FIG. 3 is a diagram for explaining a recording format of the data recorder in FIG. 1;

FIG. 4 is a diagram showing a data storage space of a RAM in FIG. 1;

FIG. 5 is a diagram showing a general configuration of a conventional DVTR.

FIG. 6 is a diagram showing a recording pattern on a tape by the DVTR of FIG. 5;

[Explanation of symbols]

 Reference Signs List 1 input terminal 5, 5 'memory control circuit 7, 7' RAM 9 vertical synchronization signal input terminal 10 ID word adding circuit 16 ID word extracting circuit 21 magnetic tape

Claims (3)

(57) [Claims] 1. An apparatus for recording video data by forming a large number of tracks on a recording medium, comprising: means for dividing each screen of input video data into a plurality of blocks; Means for generating identification data indicating the corresponding block, and adding the identification data to a block corresponding to the screen switching portion among the plurality of blocks, and adding synchronization data to the plurality of blocks. Recording processing means for generating a plurality of synchronous blocks and obtaining recording data comprising the plurality of synchronous blocks, forming a large number of tracks on a recording medium, and recording the recording data so that a screen switching position differs between the tracks. A recording device comprising: recording means for recording. 2. The recording apparatus according to claim 1, wherein the identification data indicates a first block after screen switching. 3. The recording apparatus according to claim 1, wherein said recording processing means includes error correction coding means for adding redundant data to said plurality of blocks and performing error correction coding.