JP2747306B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a semiconductor device having a structure in which a plurality of field-effect transistors are connected in parallel, with a view to preventing glitches, and connecting a plurality of transistors in parallel to increase the effective channel width. In the semiconductor device having the above structure, the channel lengths of the plurality of transistors to which the gate electrodes are commonly connected are set to different values.

[Industrial applications]

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a structure in which a plurality of field effect transistors are connected in parallel.

A buffer in a semiconductor integrated circuit chip has a waveform shaping function for steeping an edge of an input signal waveform and outputting the signal. Among them, a field effect transistor (hereinafter simply referred to as a transistor) is provided in parallel for speeding up. It is known to increase the channel width by connecting.

In the buffer having such a configuration, the on-resistance value of the buffer becomes small, and it is important to prevent a large current from flowing into the ground line.

[Conventional technology]

FIG. 5 is a plan view of an example of a configuration of a conventional semiconductor device. In the figure, reference numerals 11a, 11b, 11c, and 11d denote polysilicon gate electrodes having the same channel length, which are arranged so that their longitudinal directions are parallel to each other, and the polysilicon electrode 12
The gate electrodes 11a and 11b are connected by a, and the gate electrodes 11c and 11d are connected by the polysilicon electrode 12b. The channel lengths of the gate electrodes 11a to 11d are La to Ld.

13a, 13b, 13c, 13d and 13e are gate electrodes 11a, respectively.
P-type diffusion layer formed on the substrate using
Reference numerals 4a, 14b, 14c, 14d, and 14e denote N-type diffusion layers formed on the substrate using the gate electrodes 11a to 11d as masks, respectively. If the substrate of this semiconductor device is, for example, N-type,
A P-well is formed before the region surrounding the mold diffusion layers 14a to 14e.

The above gate electrodes 11a to 11d, electrodes 12a and 12b, N-type diffusion layer 13
An oxide film is formed on each of the P-type diffusion layers 14a to 14e, and an aluminum electrode is formed on the oxide film.
15, 16, 17 and 18 are each coated.

Thus, the first P-channel transistor having the P-type diffusion layers 13a and 13b as a source region and a drain region, respectively, and the first P-channel transistor having the gate electrode 11a, and the P-type diffusion layers 13b and 13c as a drain region and a source region, respectively. 11b
A p-type diffusion layer 13c and 13d as a source region and a drain region, respectively,
A third P-channel transistor having the gate electrode 11c and a fourth P-channel transistor having the gate electrode 11d using the P-type diffusion layers 13d and 13e as a drain region and a source region, respectively, are formed.

Similarly, two adjacent N-type diffusion layers among the N-type diffusion layers 14a to 14e
First to fourth N-channel transistors each having any one of the gate electrodes 11a to 11d are formed using the type diffusion layer as a source region or a drain region.

Further, the electrode 15 is connected to the gate electrodes 11a to 11d through contact holes opened in the oxide film, respectively,
16 is P serving as a source region through another contact hole
The electrode 17 is connected to the diffusion layers 13a, 13c and 13e, and the electrode 17 is an N-type diffusion layer serving as a source region through another contact hole.
They are connected to 14a, 14c and 14e, respectively. Further, the electrode 18 is a P-type diffusion layer serving as a drain region through a contact hole.
13b, 13d, and N-type diffusion layers 14b and 14d, respectively.

Therefore, the equivalent circuit of the circuit configuration shown in FIG. 5 is as shown in FIG. 6, and the first to fourth P-channel transistors P _{1 to} P ₄ and the first to fourth N-channel transistors N ₁ to N ₄ and are provided corresponding pair of transistors Pi and Ni (however, i = 1 to 4) is a single CMOS inverter formed drains and gates are respectively connected, a total of four In this configuration, a CMOS inverter is connected in parallel to the input terminal 20 and also connected in parallel to the output terminal 21.

Thus, by connecting the P-channel transistors P _{1 to} P ₄ in parallel and connecting the N-channel transistors N _{1 to} N ₄ in a column, the drains of the transistors P _{1 to} P ₄ and N _{1 to} N ₄ can be reduced. The source-to-source resistance is smaller than that of one transistor, and the apparent channel width is increased. Thereby, the resistance when the transistor is turned on becomes small.

Since the above conventional semiconductor device period input voltage is low to the input terminal 20 (electrode 15) of the transistor P ₁ to P ₄ are each turned on, the transistor N ₁ to N ₄ is respectively off, the output terminal 21 a high level voltage is taken in, also the period of the input voltage is high, the transistor P ₁ to P ₄ are each turned off, the transistor N ₁ to N ₄ is respectively turned on, the low level to the output terminal 21 The voltage is taken out.

The semiconductor device having such a configuration constitutes a buffer that inverts the phase of an input signal input to the input terminal 20 to the output terminal 21 and outputs the inverted signal, and as described above, the channel width of the transistors P _{1 to} P ₄ and N _{1 to} N ₄ Is apparently large, the on-resistance becomes small, the switching is performed steeply, and the speed is increased.

[Problems to be solved by the invention]

Here, in the above-mentioned conventional semiconductor device, when a voltage as shown in FIG.
Albeit for a short time when transitioning from the low level to the high level, the transistors P ₁ to P ₄ and N ₁ to N ₄ is turned respectively on, then the transistor N ₁ to N ₄ is turned off from on, the output The voltage is slightly delayed with respect to the input voltage as shown in FIG.

However, in the conventional semiconductor device, as shown in FIG. 5, since the channel lengths La, Lb, Lc and Ld are all equal, the threshold values of the transistors P _{1 to} P ₄ and N _{1 to} N ₄ are set. When the voltages are the same and the input voltage transitions from the low level to the high level, the transistors P _{1 to} P ₄ and N _{1 to} N ₄
Are turned on at the same time, and the on-resistance value is small because the channel width is large. Therefore, as shown in FIG.
A large current flows instantaneously to the GND potential electrode 17 (Vss terminal).

For this reason, when the wiring resistance of the electrode 17 is large, there is a problem that a glitch in which the GND voltage at the electrode 17 changes greatly as shown in FIG.

The present invention has been made in view of the above points, and has as its object to provide a semiconductor device capable of preventing glitches.

[Means for solving the problem]

FIG. 1 shows a principle configuration diagram of the present invention. In the figure, 1 ₁ to 1 _n
Are gate electrodes, whose longitudinal directions are arranged in parallel with each other. This as the n gate electrode 1 ₁ to 1 mask _n, P-type diffusion layer 2 and the N-type diffusion layer 3 Togaotto s are formed. Thus, n-number of P-channel transistor P ₁ to P _n are formed by the gate electrode 1 ₁ to 1 _n and P-type diffusion layer 2, and n by the gate electrode 1 ₁ to 1 _n and the N-type diffusion layer 3 N-channel transistors N _{1 to} N _n are formed.

Since the gate electrode 1 ₁ to 1 _n are connected respectively to each other,
n number of P-channel transistor P ₁ to P _n are connected in parallel to the common gate electrode, and also N-channel transistor N ₁ to N _n are connected in parallel.

In such a semiconductor device having a structure in which a plurality of transistors P _{1 to} P _n and N _{1 to} N _n are connected in parallel to increase the channel width, the present invention provides a method for controlling the channel length L of each of the transistors P ₁ and N _1.
1 , the channel lengths L _{2 of} the transistors P ₂ and N ₂ ,..., And the channel lengths L _n of the transistors P _n and N _n are different from each other.

[Action]

Transistor channel length and its gate threshold voltage
The relationship with _VTH is as shown in FIG. 2, and a short channel effect occurs in which the gate threshold voltage _VTH changes as the channel length becomes shorter.

The present invention has been made focusing on this short channel effect. In FIG. 1, the channel lengths L _{1 to} L _n are L ₁ <L ₂ <
L ₃ <... <because the relation of L _n, lowest gate threshold voltage of the transistor P ₁ and N ₁ is equal to or less than the transistor P ₂
N _2, P ₃ and N _3, ... sequentially gate threshold voltage becomes higher at the, transistor P _n and N _n indicates the respective maximum gate threshold voltage.

Therefore, even when each the same gate input voltage to the transistor P ₁ to P _n and N ₁ to N _n is applied, the corresponding pair of transistors P _K and N _K (although, k = 1 to n) is the same timing in but turned on or off, while the transistors P ₁ to P _n, and thus to be sequentially on or off at different timings between the n ₁ to n _n.

Therefore, the current that flows when the corresponding pair of transistors P _K and N _K is turned on simultaneously, so that it is possible to temporally distributed among n pairs of transistors.

〔Example〕

FIG. 3 shows a plan view of the configuration of one embodiment of the present invention. 5, the same components as those in FIGS. 1 and 5 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate. The third embodiment shown in the figure is the case where n = 4, the fifth gate electrode as compared with the conventional apparatus shown in FIG. 1 _1, 1 _2, 1 ₃ and 1 each channel length of ₄ L _1, L _2, L ₃ and
It is characterized in that L ₄ is different from each other as shown by the inequality L ₁ <L ₂ <L ₃ <L ₄ . However, the equivalent circuit itself is the same as the circuit shown in FIG. 6, and has a configuration in which the CMOS inverters of FIGS. 1 to 4 are connected in parallel.

Next, the operation of this embodiment will be described. Fig. 3 Electrode
Assuming that the gate input voltage shown in FIG. 4A is applied to FIG. 15, the phase is inverted by the above-described first to fourth CMOS inverters, and the electrode 18 shown in FIG. ) Is output.

Here, in the process of gate input voltage rises from the low level to a high level, first the transistors P ₁ and N ₁ that most gate threshold voltage at the point slightly input voltage than the low level becomes higher with a lower gate electrode 1 ₁ Are turned on at the same time. Thus, a current flows in this case electrodes 17, it is because it is only the current flowing through the transistors P ₁ and N ₁ respectively through, the current value is small.

Then transistor P _2, further comprising next gate threshold voltage lower gate electrode 1 ₂ when the input voltage increases slightly
And N ₂ is turned on each at the same time. At this time, a transistor
P ₁ is because it is immediately before the OFF or OFF, the transistors P ₂ and N ₂ respectively current flows through the electrode 17, also transistors P ₁ and N ₁ when the transistor P ₁ is still on at this point Current flows even if they pass through But,
Since the other transistors N ₃ and N ₄ are each off, the current value flowing through the electrode 17 is smaller than that of the conventional one.

Further the input voltage rises slightly, then transistor P ₃ and N ₃ the gate threshold voltage has a lower gate electrode 1 ₃
Are turned on at the same time. Therefore, current to the electrodes 17 to flow through the transistor P ₃ and N _3, but because this time at least the transistors P ₁ and P ₄ are each turned off, again the current as transistor P ₂ and N ₂ is s respectively turned on at this point The value is smaller than before.

Then, the input voltage the transistor P ₄ and N ₄ are turned on simultaneously with the gate electrode 1 ₄ having the largest gate threshold voltage in the vicinity immediately after increased to a predetermined high level, at least the transistors P ₁ and P because ₂ is turned off in each this time, also the transistor P ₃ and N ₃ are as it respectively turned on, the current value flowing between the electrodes 17 is small as compared with the prior art.

Thereafter, all of the transistors P _{1 to} P ₄ are turned off and all of the transistors N _{1 to} N ₄ are turned on, so that no current flows through the electrode 17.

Therefore, from the above, the current flowing into the electrode 17 is the fourth
As shown in FIG. 4C, the instantaneous current value is much smaller than in the prior art, so that even if the wiring resistance of the electrode 17 is large, the GN
As shown in FIG. 4 (D), the D voltage changes only by an extremely small value as compared with the prior art.

Note that the channel lengths are sequentially increased from left to right as shown in FIG. 1 and FIG. 3, but the order is not important. In short, the channel lengths of the transistors constituting the different CMOS inverters are different from each other. It should just be.

〔The invention's effect〕

As described above, according to the present invention, a current flowing when a plurality of transistors are turned on can be temporally dispersed among the plurality of transistors. It has features such as being able to suppress instantaneous large current due to resistance, prevent the level of the GND potential from rising, that is, prevent glitches, and contribute to improving the performance of the semiconductor integrated circuit.

[Brief description of the drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is an explanatory diagram of the short channel effect, FIG. 3 is a plan view showing the structure of one embodiment of the present invention, and FIG. FIG. 5 is a plan view showing an example of a conventional configuration, FIG. 6 is a circuit diagram of an example of a buffer, and FIG. 7 is a time chart for explaining the operation of FIG. In the figure, ₁₁ to 1 _n are gate electrodes, 2 is a P-type diffusion layer, 3 is an N-type diffusion layer, P _{1 to} P _n are P-channel transistors, N _{1 to} N _n are N-channel transistors, and L _{1 to} L _n indicates the channel length.

Continuation of front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 27/08 H01L 29/78

Claims (1)

(57) [Claims] A plurality of transistors (P _{1 to} P _n : N _{1 to} N _n )
Are connected in parallel to increase the effective channel width, wherein the plurality of transistors (P _{1 to} P _n : N _{1 to} N _n ) to which gate electrodes ( ₁₁ to 1 _n ) are commonly connected are connected. ) For each channel length (L ₁
To L _n ) are set to values different from each other.