JP2690613B2 - Method and apparatus for forming multilayer film - Google Patents
Method and apparatus for forming multilayer filmInfo
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- JP2690613B2 JP2690613B2 JP27048190A JP27048190A JP2690613B2 JP 2690613 B2 JP2690613 B2 JP 2690613B2 JP 27048190 A JP27048190 A JP 27048190A JP 27048190 A JP27048190 A JP 27048190A JP 2690613 B2 JP2690613 B2 JP 2690613B2
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- Prior art keywords
- layer
- film
- multilayer film
- forming
- film forming
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Description
【発明の詳細な説明】 [産業上の利用分野] 本発明は、多層膜構造の半導体装置の多層膜を、複数
の成膜室で連続的に成膜する多層膜成膜方法、及びその
装置に関し、特にプラズマCVD法を用いて成膜を行う多
層膜成膜方法、及びその装置に関するものである。TECHNICAL FIELD The present invention relates to a multilayer film forming method for continuously forming a multilayer film of a semiconductor device having a multilayer film structure in a plurality of film forming chambers, and an apparatus therefor. In particular, the present invention relates to a multilayer film forming method and an apparatus for forming a film using a plasma CVD method.
[従来の技術] プラズマCVDによる多層膜連続成膜技術は、アモルフ
ァスシリコン(a−Si)を用いた光導伝型光センサー、
太陽電池、TFTなどの作製にとって重要な技術である。[Prior Art] The continuous film formation technology of a multilayer film by plasma CVD is an optical transmission type optical sensor using amorphous silicon (a-Si),
This is an important technology for manufacturing solar cells, TFTs, etc.
第5図は、従来の多層膜成膜装置を模式的に示す図で
あるが、同装置は図に示すように、ゲートバルブ46によ
り遮断されて独立した各処理室41〜45より構成されてい
る。FIG. 5 is a diagram schematically showing a conventional multi-layer film forming apparatus. As shown in the figure, the apparatus is composed of independent processing chambers 41 to 45 which are shut off by a gate valve 46. There is.
この装置において、まずトレーにのせたガラス基板を
ロード室41から導入し、真空引きした後、42,43,44の各
成膜室で、順次多層膜を形成し、アンロード室45にて大
気に戻して、取出しを行うことにより、多層膜構造の半
導体装置を作製することができる。In this apparatus, first, a glass substrate placed on a tray is introduced from the load chamber 41, and after evacuation, a multilayer film is sequentially formed in each of the film forming chambers 42, 43, and 44, and the unloading chamber 45 is opened to the atmosphere. Then, the semiconductor device having a multilayer film structure can be manufactured by taking out the semiconductor device again.
[発明が解決しようとする課題] しかしながら、従来技術では、多層膜中のある一つの
層の処理時間が突出して長い場合、タクトタイムは、こ
の時間に律速されるため、全体の処理時間を短縮するこ
とが難しかった。[Problems to be Solved by the Invention] However, in the conventional technique, when the processing time of a certain layer in the multilayer film is extremely long, the tact time is limited by this time, so that the entire processing time is shortened. It was difficult to do.
また、膜厚の大きい層や、膜の内部応力の大きい層
や、膜の密着性が悪い層などでは、成膜を重ねるにつれ
て、成膜室内壁や、電極面等に付着した膜が剥離し、基
板上にゴミとして付着し、製品の歩留りを低下させる原
因となるという問題があった。Also, in layers with large film thickness, layers with large internal stress of the film, layers with poor film adhesion, etc., the film adhered to the inner wall of the film formation, the electrode surface, etc. peels off as the film formation is repeated. However, there is a problem in that it adheres to the substrate as dust and reduces the yield of products.
また、成膜室内のゴミを少なくするため、頻繁に成膜
処理を中断して、成膜室内壁や、電極に付着した膜を除
去しなければならず、効率も良くなかった。Further, in order to reduce dust in the film forming chamber, it is necessary to frequently interrupt the film forming process to remove the film adhered to the inner wall of the film forming chamber and the electrodes, which is not efficient.
[課題を解決するための手段及び作用] 本発明は、前記課題を解決するための手段として、 多層膜構造を有する半導体装置の該多層膜を、複数の
成膜室で連続的に成膜する多層膜成膜方法において、 前記多層膜の内、少なくとも1つの層を、2つ以上の
前記成膜室で分割して連続的に成膜することを特徴と
し、 前記2つ以上の成膜室で分割して連続的に成膜する層
が、前記多層膜の内で、 成膜時間が最も短い層を除く層、 及び/又は内部応力が最も小さい層を除く層、 及び/又は内部応力×膜厚が最も小さい層を除く層、 及び/又は前記成膜室内でゴミの発生の最も少ない層
を除く層、 であることを特徴とし、 前記多層膜は、少なくとも窒化ケイ素とアモルファス
シリコンを含むことを特徴とする多層膜成膜方法を提供
するものである。[Means and Actions for Solving the Problems] As a means for solving the above problems, the present invention continuously forms the multilayer film of a semiconductor device having a multilayer film structure in a plurality of film forming chambers. In the multi-layer film forming method, at least one layer of the multi-layer film is divided into two or more film forming chambers for continuous film formation, and the two or more film forming chambers are formed. Among the above-mentioned multi-layered films, the layers that are continuously divided and divided are layers excluding the layer having the shortest film formation time, and / or layers excluding the layer having the smallest internal stress, and / or the internal stress × A layer excluding a layer having the smallest film thickness, and / or a layer excluding a layer in which the least amount of dust is generated in the deposition chamber, wherein the multilayer film contains at least silicon nitride and amorphous silicon. To provide a method for forming a multilayer film characterized by
更にまた、本発明は、多層膜構造を有する半導体装置
の該多層膜を、複数の成膜室で連続して成膜する多層膜
成膜装置において、 前記多層膜の内、少なくとも1つの層の前記成膜室
が、連続した2室以上で構成されていることを特徴と
し、 前記連続した2室以上の成膜室が、前記多層膜の内
で、 成膜時間が最も短い層を除く層、 及び/又は内部応力が最も小さい層を除く層、 及び/又は内部応力×膜厚が最も小さい層を除く層、 及び/又は前記成膜室内でゴミの発生の最も少ない層
を除く層、 の成膜室であることを特徴し、 前記多層膜は、少なくとも窒化ケイ素とアモルファス
シリコンを含むことを特徴とする多層膜成膜装置によ
り、前記課題を解決しようとするものである。Furthermore, the present invention provides a multilayer film forming apparatus for continuously forming the multilayer film of a semiconductor device having a multilayer film structure in a plurality of film forming chambers, wherein at least one layer of the multilayer films is formed. The film forming chamber is configured by two or more continuous film forming chambers, and the two or more continuous film forming chambers are layers except the layer having the shortest film forming time in the multilayer film. , And / or a layer excluding a layer having the smallest internal stress, and / or a layer excluding a layer having an internal stress × a smallest film thickness, and / or a layer excluding a layer in which the least dust is generated in the deposition chamber, It is a film forming chamber, and the above-mentioned problem is solved by a multilayer film forming apparatus characterized in that the multilayer film contains at least silicon nitride and amorphous silicon.
本発明によれば、処理時間の長い成膜室を2室以上設
け、単一の層を分割して成膜することによって、タクト
タイムを減少させることができ、スループットの向上を
計ることができる。According to the present invention, the tact time can be reduced and the throughput can be improved by providing two or more film forming chambers having a long processing time and dividing a single layer to form a film. .
また膜厚の大きい膜や、膜の内部応力の大きい膜や、
密着性の悪い膜などの、成膜室内壁や、電極面から剥離
し易く、成膜室内にゴミの発生の多い膜の成膜室を2室
以上設け、成膜処理を分割することによって、剥離した
膜によるゴミの発生を減少させ、製品歩留の向上を計る
ことができる。Also, a film with a large film thickness, a film with a large internal stress of the film,
By providing two or more film-forming chambers for films that are easily adhered to the inner wall of the film-forming chamber, such as a film having poor adhesion, or which easily generate dust, and by dividing the film-forming process, It is possible to reduce the generation of dust due to the peeled film and improve the product yield.
[実施例] 以下、本発明の実施例について図を参照しながら説明
を述べる。[Examples] Hereinafter, examples of the present invention will be described with reference to the drawings.
(実施例1) アモルファスシリコンTFT一体型光導伝センサーを作
製する場合の実施例1について述べる。(Example 1) Example 1 in the case of manufacturing an optical transmission sensor integrated with an amorphous silicon TFT will be described.
まず、これらの半導体装置の各層の代表的膜厚と、処
理時間と、膜の内部応力値を以下の表に示す。First, the typical film thickness of each layer of these semiconductor devices, the processing time, and the internal stress value of the film are shown in the following table.
この例では、i層の処理時間が3時間と長く、タクト
タイムはこれに律速されるため、3時間となる。 In this example, the processing time of the i layer is as long as 3 hours, and the takt time is rate-controlled by this, which is 3 hours.
また膜の[内部応力×膜厚]値は、絶縁層、i層が大
きく、成膜回数の増加と共に、成膜室内壁や電極からの
膜剥れが増加し、これが基板上に落下することにより、
製品歩留りが低下する。そこで、この時点で成膜室内に
付着した膜を除去する作業を行うのであるが、従来この
間の成膜回数は20〜40回程度である。The value of [internal stress x film thickness] of the film is large in the insulating layer and i-layer. As the number of times of film formation increases, film peeling from the inner wall of the film formation chamber and electrodes increases, and this falls on the substrate. Due to
Product yield decreases. Therefore, at this point, the work of removing the film adhering to the film forming chamber is carried out, but conventionally the number of film formings during this period is about 20 to 40 times.
そこで、本実施例では、第1図のように、絶縁層の成
膜室を2室(12(a),12(b))、i層の成膜室を2
室(13(a),13(b))とすることにより、i層の成
膜時間を1.5時間ずつとして、タクトタイムは1.5時間と
し、また膜除去までの成膜回数は、従来の約2倍の40〜
80回とすることができた。この結果、従来型よりも、多
くの生産量を確保することができた。Therefore, in this embodiment, as shown in FIG. 1, two insulating layer deposition chambers (12 (a), 12 (b)) and two i layer deposition chambers are provided.
By setting the chambers (13 (a), 13 (b)), the film formation time for the i layer is 1.5 hours each, the tact time is 1.5 hours, and the number of film formations until film removal is about 2 times that of the conventional method. Double 40 ~
I was able to do it 80 times. As a result, it was possible to secure a larger production volume than the conventional type.
(実施例2) アモルファスシリコンTFTを作製する場合の実施例2
について、以下に説明する。(Example 2) Example 2 in the case of manufacturing an amorphous silicon TFT
Will be described below.
これらの半導体装置の各層の膜厚、処理時間、膜の内
部応力×膜厚値の一例を、以下の表に示す。The following table shows an example of the film thickness of each layer of these semiconductor devices, processing time, and internal stress of the film × film thickness value.
この例では、絶縁層の[内部応力×膜厚]値が大き
く、絶縁層成膜室における膜剥れが成膜回数の増加と共
に増大し、製品歩留りの低下を引き起こす。通常はこの
時点で成膜室内に付着した膜を除去する作業を行うが、
従来この間の成膜回数は30回程度である。 In this example, the value of [internal stress × film thickness] of the insulating layer is large, and film peeling in the insulating layer film forming chamber increases with an increase in the number of times of film formation, causing a reduction in product yield. Normally, at this point, work to remove the film adhering to the deposition chamber is performed.
Conventionally, the number of film formations during this period is about 30 times.
そこで、本実施例では、第2図のように、絶縁層の成
膜室を,22(a)及び22(b)の2室として、成膜を行
うようにした。これにより膜除去までの成膜回数を、従
来の約2倍の60回程度とすることができた。またこの結
果、従来型よりも膜除去作業による装置停止時間が相対
的に短くなり、多くの生産量を確保することができるよ
うになった。Therefore, in the present embodiment, as shown in FIG. 2, the film formation chamber for the insulating layer is set to two chambers 22 (a) and 22 (b) for film formation. As a result, the number of times of film formation until the film was removed was doubled to about 60 times. As a result, the apparatus down time due to the film removing work is relatively shorter than that of the conventional type, and a large amount of production can be secured.
(実施例3) アモルファスシリコンTFT一体型光導伝センサーを作
製する場合の実施例3について、以下に説明する。(Example 3) Example 3 in the case of producing an amorphous silicon TFT integrated optical transmission sensor will be described below.
このような半導体装置の各層の膜厚、処理時間と、内
部応力×膜厚処理時間の一例を以下の表に示す。The following table shows an example of the film thickness of each layer of such a semiconductor device, the processing time, and the internal stress × film thickness processing time.
この例では、i層の処理時間が2時間と長く、タクト
タイムは、従来これに律速されて2時間となる。 In this example, the processing time for the i layer is as long as 2 hours, and the takt time is 2 hours, which is conventionally limited by this.
そこで、本実施例では、第3図に示すように、i層成
膜室を33(a),33(b)の2室とし、各室で1時間ず
つ成膜を行うようにした。このようにすることによっ
て、タクトタイムは1時間となり、全体的な処理時間は
短縮され、従来の方法、装置に比べ、多くの生産量を確
保できるようになった。In view of this, in this embodiment, as shown in FIG. 3, the i-layer film forming chamber was set to two chambers 33 (a) and 33 (b), and film formation was performed for 1 hour in each chamber. By doing so, the tact time was reduced to 1 hour, the overall processing time was shortened, and a large amount of production could be secured as compared with the conventional method and apparatus.
(実施例4) アモルファスシリコンTFT一体型光導伝センサー作製
時に、各層の膜剥れを改善するための本発明の実施例4
について、以下に説明する。(Example 4) Example 4 of the present invention for improving film peeling of each layer at the time of manufacturing an optical transmission sensor integrated with an amorphous silicon TFT
Will be described below.
下表は、P−CVD 20バッチ目の膜剥れに起因する不
良率の一例を示すものである。The table below shows an example of the defective rate due to film peeling of the 20th batch of P-CVD.
また、また第6図は、従来方式でのバッチ数と不良率
との関係をグラフに表わした図であるが、同図に示すよ
うに20バッチをこえると、i層成膜室の膜剥れによる不
良は急激に増加する。 Also, FIG. 6 is a graph showing the relationship between the number of batches and the defect rate in the conventional method. As shown in FIG. 6, when 20 batches are exceeded, film peeling in the i-layer deposition chamber is performed. Defects due to this increase rapidly.
そこで、本実施例では、第4図に示すように、i層成
膜室を53(a)53(b)53(c)の3室とし、各層均等
の膜厚(本実施例では2000Åずつ)で成膜を行った。Therefore, in this embodiment, as shown in FIG. 4, the i-layer deposition chamber is set to three chambers of 53 (a) 53 (b) 53 (c), and the film thickness of each layer is equal (in this embodiment, 2000 Å each). ) Was used to form a film.
この結果20バッチ目のi層の成膜室の膜剥れによる不
良率は、第7図の、本実施例のバッチ数と不良率の関係
を示すグラフに示されるように、3%となり、歩留の向
上がはかれた。As a result, the defective rate due to film peeling in the film forming chamber of the i-th layer of the 20th batch was 3% as shown in the graph of FIG. The yield was improved.
このように本実施例によれば、従来のものに比べ、よ
り多くのバッチ回数、高歩留での生産が可能となる。As described above, according to this embodiment, it is possible to perform the production with a larger number of batches and a higher yield than the conventional one.
[発明の効果] 以上説明した様に、本発明によれば、多層膜構造を有
する半導体装置の、成膜時間の大きな層、成膜室内にゴ
ミの発生の多い層を複数の成膜室で分割して成膜するこ
とにより、 タクトタイムを短縮できる、 成膜室内に付着した膜の剥離が減少し、基板上に付着
するゴミが減少し、製品歩留りが向上する、 成膜室内壁や電極等の治具のクリーニングまでの成膜
回数を増やすことができ、処理機番の投入量を増大でき
る、 等の効果が得られる。[Effects of the Invention] As described above, according to the present invention, in a semiconductor device having a multilayer film structure, a layer having a long film formation time and a layer having a large amount of dust in the film formation chamber can be formed in a plurality of film formation chambers. By dividing the film formation, the tact time can be shortened, peeling of the film adhered in the film formation chamber is reduced, dust adhering to the substrate is reduced, and product yield is improved. It is possible to increase the number of times of film formation until the cleaning of the jig such as, and to increase the input amount of the processing machine number.
第1〜4図は、それぞれ本発明の実施例1〜4の装置と
方法を示す模式図である。 第5図は、従来例の装置と方法を示す模式図である。 第6図は、従来のP−CVDでのバッチ数と膜剥れによる
不良率の関係を示す図。 第7図は、本発明の実施例4のP−CVDでのバッチ数と
膜剥れによる不良率の関係を示す図。 11,21,31,41,51……試料のロード室 12(a),12(b),22(a),22(b),32,42,52……絶
縁層成膜室 13(a),13(b),23,33(a),33(b),43,53
(a),53(b),53(c)……i層成膜室 14,24,34,44,54……n+層成膜室 15,25,35,45,55……試料のアンロード室 16,26,36,46,56……ゲートバルブ1 to 4 are schematic views showing the apparatus and method of Examples 1 to 4 of the present invention, respectively. FIG. 5 is a schematic diagram showing a conventional apparatus and method. FIG. 6 is a diagram showing the relationship between the number of batches in conventional P-CVD and the defect rate due to film peeling. FIG. 7 is a diagram showing the relationship between the number of batches in P-CVD and the defect rate due to film peeling in Example 4 of the present invention. 11,21,31,41,51 …… Sample loading chamber 12 (a), 12 (b), 22 (a), 22 (b), 32,42,52 …… Insulating layer deposition chamber 13 (a ), 13 (b), 23,33 (a), 33 (b), 43,53
(A), 53 (b), 53 (c) …… i layer deposition chamber 14,24,34,44,54 …… n + layer deposition chamber 15,25,35,45,55 …… Unload chamber 16,26,36,46,56 …… Gate valve
Claims (6)
を、複数の成膜室で連続的に成膜する多層膜成膜方法に
おいて、 前記多層膜の内、少なくとも1つの層を、2つ以上の前
記成膜室で分割して連続的に成膜することを特徴とする
多層膜成膜方法。1. A multilayer film forming method for continuously forming the multilayer film of a semiconductor device having a multilayer film structure in a plurality of film forming chambers, wherein at least one layer of the multilayer film is 2 A method for forming a multilayer film, characterized in that the film formation is performed continuously by dividing in one or more film forming chambers.
成膜する層が、前記多層膜の内で、 成膜時間が最も短い層を除く層、 及び/又は内部応力が最も小さい層を除く層、 及び/又は内部応力×膜厚が最も小さい層を除く層、 及び/又は前記成膜室内でゴミの発生の最も少ない層を
除く層、 であることを特徴とする請求項1に記載の多層膜成膜方
法。2. A layer formed by continuously dividing the film in two or more film forming chambers is a layer of the multilayer film except a layer having the shortest film forming time, and / or an internal stress A layer excluding the smallest layer, and / or a layer excluding the layer having the smallest internal stress × thickness, and / or a layer excluding the layer in which the least amount of dust is generated in the deposition chamber. Item 2. The method for forming a multilayer film according to Item 1.
モルファスシリコンを含むことを特徴とする請求項1に
記載の多層膜成膜方法。3. The method for forming a multilayer film according to claim 1, wherein the multilayer film contains at least silicon nitride and amorphous silicon.
を、複数の成膜室で連続して成膜する多層膜成膜装置に
おいて、 前記多層膜の内、少なくとも1つの層の前記成膜室が、
連続した2室以上で構成されていることを特徴とする多
層膜成膜装置。4. A multilayer film forming apparatus for continuously forming the multilayer film of a semiconductor device having a multilayer film structure in a plurality of film forming chambers, wherein at least one layer of the multilayer film is formed. The membrane chamber
A multi-layer film forming apparatus characterized by comprising two or more continuous chambers.
層膜の内で、 成膜時間が最も短い層を除く層、 及び/又は内部応力が最も小さい層を除く層、 及び/又は内部応力×膜厚が最も小さい層を除く層、 及び/又は前記成膜室内でゴミの発生の最も少ない層を
除く層、 の成膜室であることを特徴とする請求項4に記載の多層
膜成膜装置。5. The two or more continuous film forming chambers are layers except the layer having the shortest film forming time in the multilayer film, and / or the layer excluding the layer having the smallest internal stress, and / or Or a layer excluding a layer having a minimum internal stress x a film thickness, and / or a layer excluding a layer in which the least amount of dust is generated in the film formation chamber. Multilayer film forming apparatus.
モルファスシリコンを含むことを特徴とする請求項4に
記載の多層膜成膜装置。6. The multilayer film forming apparatus according to claim 4, wherein the multilayer film contains at least silicon nitride and amorphous silicon.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27048190A JP2690613B2 (en) | 1990-10-11 | 1990-10-11 | Method and apparatus for forming multilayer film |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27048190A JP2690613B2 (en) | 1990-10-11 | 1990-10-11 | Method and apparatus for forming multilayer film |
Publications (2)
Publication Number | Publication Date |
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JPH04147614A JPH04147614A (en) | 1992-05-21 |
JP2690613B2 true JP2690613B2 (en) | 1997-12-10 |
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JP27048190A Expired - Lifetime JP2690613B2 (en) | 1990-10-11 | 1990-10-11 | Method and apparatus for forming multilayer film |
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JP (1) | JP2690613B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH11121754A (en) * | 1997-10-14 | 1999-04-30 | Sanyo Electric Co Ltd | Device and method for manufacturing thin-film transistor |
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1990
- 1990-10-11 JP JP27048190A patent/JP2690613B2/en not_active Expired - Lifetime
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JPH04147614A (en) | 1992-05-21 |
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