JP2634609B2 - Data transfer device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device suitably implemented in various electronic devices that perform serial data transfer such as various in-vehicle electronic devices.

Prior Art FIG. 6 is a block diagram showing a configuration of a typical prior art. With reference to FIG. 6, the present prior art includes an arithmetic processing device 1 such as a micro computer and a digital signal processing device (DSP, hereinafter abbreviated as signal processing device) 2. The signal processing device 2 is provided with a buffer register 3. The buffer register 3 includes a data register 4, an address register 5, and a command register 6. Data transfer is performed from the arithmetic and control unit 1 by combining commands, addresses, and body data as a unit.

The contents of the command register 6 are analyzed by the command decoder 7 and the corresponding signal is sent to the gate control circuit 8.
And controls opening and closing of various gates (not shown) provided in the signal processing device 2.

The contents of data register 4 and address register 5 are input / output between data bus 9 and address bus 10.
Output processing is performed, and the corresponding storage content of the memory 11 is read out by the address given from the address bus 10 and output to the data bus 9. The data on the data bus 9 is stored in a data buffer 12 for transmission and transmitted to the arithmetic and control unit 1.

In the transmission / reception of data between the arithmetic and control unit 1 and the signal processing unit 2, the control line 13 shown in FIG. 6 is a control line which goes low when the signal processing unit 2 is ready to receive data. When it is impossible, it becomes high level.

FIG. 7 is a timing chart for explaining the operation state of the prior art. The operation of the prior art will be described with reference to FIG. In FIG. 7, the symbols,
,... Indicate processing steps. In a read cycle SR starting from time t1 in FIG.
When ▼ becomes low level, data transmission / reception between the arithmetic and control unit 1 and the signal processing unit 2 is started. Next, as shown in FIG. 7 (2), the data is a data 14 comprising a command 15, an address 16 and dummy body data 17.
Is transferred. When data transfer is completed, command 15
Are analyzed by the command decoder 7.

The reason why the dummy body data 17 is required is that the data transferred between the arithmetic and control unit 1 and the signal processing unit 2 is fixed to the format of the command, address and body data as described above. It is. That is, in the read cycle SR, the address 16 where the data 18 to be read by the signal processing device 2 is stored and the read command 15 are transmitted. Accordingly, dummy body data 17 is added.

When the preparation of the data is completed in the signal processing device 2 at time t2 and the control signal ▼ becomes low level again, the data 18 specified by the address 16 is transmitted from the signal processing device 2 to the arithmetic and control device 1. . At this time, the data is transferred by the clock signal output from the arithmetic and control unit 1 to the line 30.
Performed by CK. When a series of processing is completed, the control signal ▼ becomes “L” level, and the write cycle SW is started at time t3 in FIG. As shown in FIG. 7 (2), the data 14, including the command 15, the address 16, and the main body data 19, is transmitted from the arithmetic and control unit 1 to the signal processing unit 2, and the command 15 indicating the writing of data is transmitted to the command decoder 7. The main data 19 is written to the corresponding address in the memory 11 using the address and data.

Problems to be Solved by the Invention The prior art as described above is advantageously performed in the transfer mode, that is, when there are many types of commands 15, but the command to be executed is only a read command and a write command. If the type is small, a command word must be sent for each data transfer,
There is a problem that the data length becomes excessively long and the transfer time becomes long. Such a problem is not solved even if the number of bits of the command 15 is reduced. That is, the transfer of the command 15 is performed, for example, in units of 8 bits, and does not reduce the transferred command 15. Furthermore, in both writing and reading of data,
Since data of the same format (the same number of bits) must be transferred, there is a drawback that the transfer time becomes longer.

An object of the present invention is to solve the above-mentioned problems and to provide a data transfer device capable of significantly improving the data transfer speed and reducing the data length to be transferred.

Means for Solving the Problems The present invention relates to a data transfer device that includes a control device and a processing device and transfers serial data between them, and a signal line provided between the control device and the processing device. A signal line for instructing the processing device or the control device in one of a data read operation state and a write operation state in accordance with the level of a signal output from the control device or the processing device; When the data consists of multiple types of components, the target address is transferred after the data to be written when performing a write operation, and only the target address is transferred when performing a read operation. A data transfer device characterized by the following.

The present invention is a method for mutually transferring data between a control device and a processing device, and a signal line is provided between these devices. Either a data read operation state or a data write operation state is instructed to the processing device or the control device by the level of a signal output from the control device or the processing device on this signal line.

Thus, the read operation and the write operation performed between the control device and the processing device do not need to transmit corresponding commands to each other, and are identified only by the level of the signal line. Further, since only the minimum number of bits is transferred at the time of data writing / reading, the data length to be transferred can be reduced, data transfer can be performed efficiently, and the transfer speed can be significantly improved. In addition, since the address can be read from the same position of the transfer register regardless of the time of writing or reading, the configuration can be simplified without the need for a switching circuit or the like.

Embodiment FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. This embodiment includes an arithmetic and control unit 21 and a digital signal processing unit (DSP, hereinafter abbreviated as signal processing unit) 22 realized by, for example, a microcomputer.

The arithmetic and control unit 21 includes a transmission register 23 and a reception register 24.
The write data DW is output from the transmission register 23 to the signal processing device 22, and the read data DR is input to the reception register 24 from the signal processing device 22.

The signal processing device 22 includes an address register 25 in which an address and data forming the write data DW are stored, a transfer register 27 including a data register 26, and another data register 50 for outputting internal data. The contents of the transfer register 27 are
Address register 29 and data register 30
Is stored in The contents of the address register 29 and the data register 30 are transmitted and received between the address bus 31 and the data bus 32 of the signal processing device 22.

The signal processing transmission device 22 includes a gate control unit 33 for various logic gates (not shown) provided in the signal processing device 22.
Is provided. Further, for example, a binary counter 34 for counting the clock signal CK supplied from the arithmetic and control unit 21 is provided. The outputs of the binary counter 34 are decoders 35 and 36
Are given in parallel. The outputs of the decoders 35 and 36 are input to, for example, one input terminals of two-input AND circuits 37 and 38, respectively.

The AND circuit 38 has a control signal for instructing the signal processing device 22 in a read operation state or a write operation state based on a difference between a high level and a low level from the arithmetic and control unit 21 via a signal line 39 as described later. R / is entered.
The signal obtained by inverting the control signal R / by the inverting circuit 40 is input to the other input terminal of the AND circuit 37. AND circuit 37,3
The output of 8 is input to the OR circuit 41, and the output of the OR circuit 41 is the address register 29 and the data register 30.
As a latch control signal.

FIG. 2 and FIG. 3 are block diagrams showing an example of the configuration of the decoders 35 and 36. In this embodiment, regarding data transferred between the arithmetic and control unit 21 and the signal processing unit 22, the address data is 16 bits, the main body data is 24 bits, and the data length is 40 bits. Description will be made assuming a certain case. The decoder 35 uses, for example, the output of the lower 6 bits (b5, b4, b3, b2, b1, b0) of the binary counter 34 as shown in FIG. This lower 6
The output of the bit is input to the AND circuit 48 via the signal lines 42 to 47 from the lower bit side. Signal lines 42, 43, 4
The inverting circuits 49 to 52 are interposed in 4, 46, respectively. The output of the AND circuit 48 becomes high level because the lower 6 bits of the binary counter 34 are (b5, b4, b3, b2, b1, b0) = (1, 0, 1, 0, 0, 0) ... This is the case of (1), which is equivalent to 40 in decimal.

The decoder 36 also has a basically similar configuration, and uses the lower 5 bits of the binary counter 34. The contents of each bit are input to the AND circuit 58 from the lower bit side via the signal lines 53 to 57. At this time, inverting circuits 59 to 62 are interposed in the signal lines 53 to 56, respectively. Such a decoder 36
The output of the AND circuit 58 becomes high level by the output when the lower 5 bits are (b4, b3, b2, b1, b0) = (1, 0, 0, 0, 0) (2) It is. This is equivalent to 16 in decimal.

FIG. 4 is a timing chart for explaining the operation of this embodiment. The operation of the present embodiment will be described with reference to the above drawings. .. In FIG. 4 indicate processing steps as in the conventional example. In a read cycle SR starting from time t11 in FIG. 4, the control signal R /
Is set to a high level, and an instruction to read data from the signal processing device 22 is issued. Next, as shown in FIG. 4A, the chip select signal 信号 is set to the low level, and the signal processing device 22 is selected.

The arithmetic processing unit 21 starts transferring the address in the signal processing unit 22 where the data to be read is stored to the signal processing unit 22, as shown in FIG. 4 (4). Here, the signal processing device 22 sets the transfer permission signal ▼ to a high level as shown in FIG.
Prohibit transfer from. When the transfer of the address data 63 is completed, the signal processing device 22 reads the internal data of the address, and at the time when the preparation for output to the arithmetic and control unit 21 is completed, at time t12, sets the transfer enable signal ▲ ▼ to low level. Then, the transfer inhibition state is released.

Based on the clock signal CK from the arithmetic and control unit 21,
As shown in FIG. 4 (5), data is read from the signal processing device 22 to the arithmetic and control unit 21. When the data transfer is completed, at time t13, the transfer permission signal ▼ is set to the low level, and the transfer prohibited state is released again. Thus, the data reading process is completed.

Next, in the write cycle SW, the control signal R / is set to low level, indicating that the operation is a write operation from the arithmetic and control unit 21 to the signal processing unit 22.

Next, as shown in FIG. 4 (4), the arithmetic and control unit 21 sends out the address data 65 following the main data 64 to be stored in the signal processing unit 22. When the transmission of the address data 65 is started, the transfer permission signal ▼ on the signal processor 22 becomes high level, and the transfer is disabled. When the transfer of the address data 65 is completed, the transfer enable signal
▼ becomes low level, and the transfer is possible. Subsequently, both the chip select signals ▼ and ▼ are set to the high level on the arithmetic and control unit 21, and the data writing is completed.

At this time, as shown in FIG. 1, the AND circuit 38 is selected while the control signal R / is at the high level. That is, in order to perform data transfer, the clock signal output from the arithmetic and control unit 21 is counted by the binary counter 34, and the output is counted by the decoders 35 and 36 as described with reference to FIGS. Is output to During the read cycle SR, the decoder 36 is selected by the AND circuit 38.
As described with reference to FIG. 3, the binary counter 34
At the stage when 16 bits have been counted, the output of the AND circuit 58 is switched to the high level, and the data is latched into the buffer register 28.

FIG. 5 shows how the address and data are set in the register. FIG. 5 (1) shows the data read operation, and FIG. 5 (2) shows the data write operation.

Thus, from the address register 25 to the buffer register
When transferring the address to the address 29, it is sufficient to always read the address from the same position, and a switching circuit or the like is not required.

At this time, in the 16 bits, only the address data 63 is transferred, so that the address data stored in the address register 25 is latched in the address register 29 of the buffer register 28. The read operation of the internal memory after the time t12 is performed by the thus latched address data.

On the other hand, in the write cycle SW, the control signal R / is at the low level, and thus the decoder
35 is selected. At this time, when the 40-bit counting operation of the binary counter 34 is completed, a latch control signal is output to the buffer register 28. In such a case, the fourth
Body data 64 and address data 65 after time t3 in the figure
The transfer of the address data 65 is completed when the transfer of the address data 65 is completed.
A latch operation to 28 will be performed.

As described above, according to the present embodiment, the command 15 described in the related art can be deleted from the transfer data, and the dummy body data 17 can also be deleted. Thereby, the data length required for the transfer is significantly reduced, the transfer speed is improved, and the transfer efficiency is also significantly improved.

The configurations of the decoders 35 and 36 are not limited to the configuration examples shown in FIG. 2 and FIG.

Effects As described above, according to the present invention, the read operation and the write operation performed between the control device and the processing device do not need to mutually transmit corresponding commands, and are distinguished only by the level of the signal line. Is done. Also, when an address is taken out from the transfer register to the buffer register, it is only necessary to always read the address from the same position, and no hardware for switching is required, and the configuration can be simplified. Further, the data length to be transferred can be reduced, the data transfer can be performed efficiently, and the transfer speed can be significantly improved.

In particular, according to the present invention, the data and the address are transferred during the write operation, and only the address is transferred during the read operation. Therefore, the data length to be transferred can be reduced, and thus the data transfer can be performed. An excellent effect of being able to perform efficiently is achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of one embodiment of the present invention, FIG. 2 is a block diagram showing a configuration example of a decoder 35, FIG. 3 is a block diagram showing a configuration example of a decoder 36, and FIG. FIG. 5 is a timing chart for explaining the operation of the embodiment, FIG. 5 is a diagram showing the relationship between the data transfer order and registers, FIG. 6 is a block diagram showing the configuration of a conventional example, and FIG. This is a timing chart. 21 arithmetic operation control device, 22 signal processing device, 23 transmission register, 24 reception register, 27 transfer register,
28… Buffer register, 34… Counter, 35,36 ……
Decoder, CK: Clock signal, R /: Control signal

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shoji Fujimoto 1-2-28 Goshodori, Hyogo-ku, Kobe City, Hyogo Prefecture Inside Fujitsu Ten Limited (72) Inventor Katsuma Yasui 1 Goshodori, Hyogo-ku, Kobe City, Hyogo Prefecture No. 2-28, Fujitsu Ten Limited

Claims (1)

(57) [Claims] A data transfer device including a control device and a processing device for mutually transferring serial data between the control device and the processing device, wherein a signal line provided between the control device and the processing device is a control device or a processing device. Such a signal line for instructing either a data reading operation state or a writing operation state to a processing unit or a control unit according to the level of a signal output from the processing unit is provided, and the serial data includes a plurality of types of constituent parts. A data transfer device for transferring a target address next to data to be written when performing a write operation, and transferring only a target address when performing a read operation. .