JP2024057500A - Semiconductor Device - Google Patents

Abstract

To provide a semiconductor device which can reduce the cost and can increase the heat releasing property.SOLUTION: A semiconductor device 101 includes at least two semiconductor chips 11, 12 with different potentials having drain electrodes 11a and 12a in a first surface and source electrodes 11b and 12b in a second surface opposite to the first surface. The semiconductor device 101 includes: a first substrate 20 and a second substrate 30 to which the semiconductor chips are separately equipped; a third substrate 50 electrically connected to the semiconductor chips; and a sealing resin unit 90 for integrally sealing the semiconductor chips and the substrates. The first and second substrates have equipped coppers 21, 31 equipped with the semiconductor chips, heat releasing coppers 22 and 32 for releasing heat from the semiconductor chips; and insulating layers 23, 33 for insulating the equipped coppers and the heat releasing coppers. The heat releasing coppers are exposed from the sealing resin unit at the surface opposed to the surface facing the insulating layer. The equipped coppers are thicker than the heat releasing coppers.SELECTED DRAWING: Figure 1

Description

This disclosure relates to a semiconductor device.

Patent Document 1 discloses a heat dissipation circuit board in which copper plates are laminated with an insulating layer in between, and a semiconductor device including multiple semiconductor elements mounted on the heat dissipation circuit board. The heat dissipation circuit board is made up of a copper plate, which is the mounting surface on which the semiconductor elements are mounted, and a copper plate, which is the heat dissipation surface in thermal contact with a cooler, laminated with an insulating layer in between. In addition, the thickness of the copper plate, which is the mounting surface on which the semiconductor elements are mounted, of the heat dissipation circuit board is the same as or thicker than the thickness of the copper plate, which is the heat dissipation surface in thermal contact with the cooler.

JP 2019-204869 A

However, some semiconductor devices are configured with two semiconductor elements that are not at the same potential. In this case, the semiconductor device of Patent Document 1 has the problem that the cost is high because the heat dissipation circuit board needs to be processed by cutting, etching, or the like.

One disclosed objective is to provide a semiconductor device that can reduce costs while improving heat dissipation.

The semiconductor device disclosed herein comprises:
A semiconductor element (11, 12) having a first electrode (11a, 12a) provided on one surface and a second electrode (11b, 12b) provided on the opposite surface of the first surface, the semiconductor element having two or more different potentials;
Two or more wiring boards (20, 30) on which semiconductor elements are individually mounted;
A wiring member (50) that electrically connects each semiconductor element;
a sealing resin portion (90) that integrally seals the semiconductor element, the wiring board, and the wiring member;
Each wiring board has a mounting metal plate (21, 31) which is a mounting portion of each semiconductor element and is connected to a first electrode, a heat dissipation metal plate (22, 32) which dissipates heat generated from the semiconductor element, and an insulating layer (23, 33) which is disposed between the mounting metal plate and the heat dissipation metal plate and which electrically insulates the mounting metal plate and the heat dissipation metal plate,
The heat dissipating metal plate has a surface opposite to the surface facing the insulating layer exposed from the sealing resin portion,
The mounting metal plate is characterized in that it has a thickness greater than that of the heat dissipating metal plate.

In this way, the semiconductor device has a wiring board on which each semiconductor element is individually mounted, so there is no need to process the wiring board by cutting or other methods to mount semiconductor elements with different potentials. This allows the semiconductor device to be manufactured at low cost.

In addition, the thickness of the mounting metal plate, which is disposed closer to the semiconductor element than the insulating layer, of the wiring board is thicker than the heat dissipation metal plate. Therefore, the semiconductor device can improve the dissipation of heat generated by the semiconductor element compared to a configuration in which the heat dissipation metal plate is thicker than the mounting metal plate.

The various aspects disclosed in this specification employ different technical means to achieve their respective objectives. The claims and the reference characters in parentheses in this section are illustrative of the corresponding relationships with the embodiments described below, and are not intended to limit the technical scope. The objectives, features, and advantages disclosed in this specification will become clearer with reference to the detailed description that follows and the accompanying drawings.

1 is a cross-sectional view showing a schematic configuration of a semiconductor device according to an embodiment. FIG. 2 is a plan view showing a schematic configuration of a lead frame in the embodiment. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2 . FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 2 . 1 is a perspective view showing a schematic configuration of a semiconductor device according to an embodiment; 1 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a first modified example. FIG. 11 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a second modified example.

Below, several embodiments for implementing the present disclosure will be described with reference to the drawings. In each embodiment, parts corresponding to matters described in the preceding embodiment may be given the same reference numerals, and duplicated descriptions may be omitted. In each embodiment, when only a part of the configuration is described, the other parts of the configuration may be applied by referring to the other embodiment described previously.

In the following, the three mutually orthogonal directions are referred to as the X direction, the Y direction, and the Z direction. The plane defined by the X direction and the Y direction is referred to as the XY plane. The view from the Z direction is also referred to as a planar view. Therefore, the planar view can be considered as a plan view when viewed from the Z direction.

(Embodiment)
A semiconductor device 101 according to the first embodiment will be described with reference to FIGS. 1 to 5. As shown in FIGS. 1 and 2, the semiconductor device 101 includes semiconductor chips 11 and 12, a first substrate 20, a second substrate 30, terminals 41 to 45, a third substrate 50, terminals 61 to 63, solders 71 to 78, a bonding wire 80, and a sealing resin portion 90. The semiconductor device 101 can be applied to, for example, an inverter in a power conversion device. The inverter is configured to include upper and lower arm circuits for three phases. The circuit configuration of the inverter can be, for example, that described in Japanese Patent Application Laid-Open No. 2022-126905. FIG. 1 corresponds to a cross-sectional view taken along line I-I in FIG. 5.

The semiconductor device 101 constitutes, for example, an upper and lower arm circuit for one phase. In this embodiment, an example is adopted in which one high-side switch 11 and one low-side switch 12 are directly connected. However, the present disclosure can also be adopted in a configuration in which multiple high-side switches 11 are connected in parallel and multiple low-side switches 12 are connected in parallel.

Note that FIG. 2 shows the state before the positive terminal 41, negative terminal 42, output terminal 43, signal terminal 44, and gate terminal 45, which are parts of the lead frame 1, are divided. Also, FIG. 5 shows the state after the sealing resin part 90 is provided and before the lead frame 1 is divided.

<Semiconductor chips 11, 12>
1, the semiconductor device 101 includes a high-side switch 11 and a low-side switch 12 as the semiconductor chips 11, 12. In other words, the semiconductor device 101 includes two or more semiconductor chips 11, 12 having different potentials. The high-side switch 11 and the low-side switch 12 have the same configuration. Therefore, when there is no need to distinguish between the high-side switch 11 and the low-side switch 12, the high-side switch 11 will be used in the description. The high-side switch 11 and the low-side switch 12 correspond to semiconductor elements.

The high-side switch 11 is formed by forming an element on a semiconductor substrate made of silicon (Si), a wide band gap semiconductor having a wider band gap than silicon, or the like. Examples of wide band gap semiconductors include silicon carbide (SiC), gallium nitride (GaN), _gallium oxide ( _Ga2O3 ), and diamond. The high-side switch 11 is sometimes called a semiconductor element.

The plate thickness direction of the high-side switch 11 coincides with the Z direction. The elements formed in the high-side switch 11 have a vertical structure so that the main current flows in the Z direction. IGBTs, MOSFETs, diodes, etc. can be used as vertical elements. In this embodiment, a MOSFET that constitutes one arm is formed as the vertical element. The high-side switch 11 has a gate electrode (not shown).

The high-side switch 11 has main electrodes of the element on both sides in the plate thickness direction, i.e., the Z direction. Specifically, as main electrodes, it has a drain electrode 11a on one side and a source electrode 11b on the opposite side. On the other hand, the low-side switch 12 has a drain electrode 12a on one side and a source electrode 12b on the opposite side as main electrodes. The drain electrodes 11a and 12a correspond to first electrodes. The source electrodes 11b and 12b correspond to second electrodes.

The high-side switch 11 has a generally rectangular shape in plan view. The high-side switch 11 has a number of pads formed on the opposite surface at positions different from the source electrode 11b. The source electrode 11b and the pads are each exposed from a protective film (not shown) on the opposite surface of the semiconductor substrate. The source electrode 11b is formed on a portion of the opposite surface of the high-side switch 11. The drain electrode 11a is formed over almost the entire surface of one surface.

The pad is an electrode for signals. The pad is electrically separated from the source electrode 11b. For example, the pad is formed at the end opposite the formation region of the source electrode 11b in the Y direction. The pad includes at least a gate pad for a gate electrode. It may also include a signal pad for a temperature sensing diode for detecting the temperature of either the semiconductor chip 11 or 12 (here, the low-side switch 12) for current sensing. As shown in FIG. 1, the low-side switch 12 has a signal pad and a signal terminal 44 connected via a bonding wire 80. The high-side switch 11 and the low-side switch 12 have a gate pad and a gate terminal 45 connected via a bonding wire 80.

<Terminals 61 to 63>
The first terminal 61, the second terminal 62 and the joint terminal 63 are conductive blocks mainly made of metal. These terminals 61 to 63 are part of the wiring of the semiconductor device 101.

The first terminal 61 is disposed on the source electrode 11b of the high-side switch 11. One end of the first terminal 61 is connected to the source electrode 11b by solder 72. The other end of the first terminal 61 is connected to the first mounting copper 51a by solder 73.

The second terminal 62 is disposed on the source electrode 12b of the low-side switch 12. One end of the second terminal 62 is connected to the source electrode 12b by solder 75. The other end of the second terminal 62 is connected to the second mounting copper 51b by solder 76.

One end of the joint terminal 63 is connected to the mounting copper 31 by solder 77. The other end of the joint terminal 63 is connected to the first mounting copper 51a by solder 78. The mounting copper 31, the first mounting copper 51a, and the second mounting copper 51b will be explained later.

<First Substrate 20, Second Substrate 30>
1, the first substrate 20 is a wiring substrate on which the high-side switch 11 is mounted. The first substrate 20 includes a mounting copper layer 21, a heat dissipation copper layer 22, and an insulating layer 23. The first substrate 20 includes the mounting copper layer 21, the insulating layer 23, and the heat dissipation copper layer 22 laminated in this order. The mounting copper layer 21 contacts the insulating layer 23 on a surface facing the insulating layer 23. The heat dissipation copper layer 22 contacts the insulating layer 23 on a surface facing the insulating layer 23.

The mounting copper 21 is a part of the wiring composed mainly of copper. The mounting copper 21 may have a plating film on its surface. The mounting copper 21 is a plate-shaped member, unlike a thin film. Therefore, the mounting copper 21 can be called a metal plate or a copper plate. The mounting copper 21 is a mounting portion of the high-side switch 11 and is connected to the drain electrode 11a. The mounting copper 21 is connected to the drain electrode 11a by solder 71. The mounting copper 21 is connected to the positive terminal 41, which is one of the main terminals. The mounting copper 21 corresponds to a mounting metal plate. The mounting copper 21 has a plate thickness greater than that of the heat dissipation copper 22. The mounting copper 21 has a plate thickness of, for example, 0.8 mm or more. The plate thickness can also be called a length along the Z direction. The positive terminal 41 corresponds to a first main terminal. It can be said that the positive terminal 41 is connected to the mounting copper 21 on which the high-side switch 11, which is connected to the first mounting copper 51a described later, is mounted.

The heat dissipating copper 22 is made of the same material as the mounting copper 21. The surface of the heat dissipating copper 22 opposite the surface facing the insulating layer 23 is exposed from the sealing resin part 90. The heat dissipating copper 22 is a member that dissipates heat generated from the high-side switch 11. In other words, the heat dissipating copper 22 receives heat from the high-side switch 11 via the insulating layer 23 and dissipates the heat to the outside of the sealing resin part 90. The heat dissipating copper 22 corresponds to a heat dissipating metal plate. Note that the mounting copper 21 and the heat dissipating copper 22 can be made of materials mainly composed of metals other than copper.

The insulating layer 23 is disposed between the mounting copper 21 and the heat dissipation copper 22, and is a material that electrically insulates the mounting copper 21 from the heat dissipation copper 22.

The second substrate 30 is a wiring substrate on which the low-side switch 12 is mounted. The second substrate 30 has mounting copper 31, heat dissipation copper 32, and an insulating layer 33, and is configured in the same manner as the first substrate 20. The mounting copper 31 has the same configuration as the mounting copper 21. The heat dissipation copper 32 has the same configuration as the heat dissipation copper 22. The insulating layer 33 has the same configuration as the insulating layer 23.

The mounting copper 31 is connected to the drain electrode 12a by solder 74. The mounting copper 31 is connected to the joint terminal 63 by solder 77. Furthermore, the mounting copper 31 is connected to the output terminal 43, which is one of the main terminals.

As shown in FIG. 1, the side of the mounting copper 21, 31 is provided with a convex V-cut portion 24, 34. In other words, the side of the mounting copper 21, 31 can be said to be V-shaped. The side of the mounting copper 21, 31 can also be said to be V-cut. Furthermore, in the Z direction, the apex of the convex shape of the mounting copper 21, 31 is located closer to the mounting surface of the semiconductor chip 11, 12 than the contact surface with the insulating layer 23, 33. The V-cut portion 24, 34 is provided around the entire periphery of the side of the mounting copper 21, 31.

As a result, the semiconductor device 101 can reduce peeling of the sealing resin portion 90 around the semiconductor chips 11 and 12 and stress on the solders 71 and 74. The mounting copper 21 and 31 may have a shape in which the cross-sectional area along the XY plane increases from the insulating layer 23 and 33 side toward the semiconductor chips 11 and 12 side. This also allows the semiconductor device 101 to achieve the same effect.

As shown in FIG. 1, the heat dissipation copper 22, 32 are provided in the areas excluding the edges of the insulating layers 23, 33. That is, the heat dissipation copper 22 is provided in a part of the insulating layer 23 when viewed in a plan view from the Z direction. Furthermore, the heat dissipation copper 22 is provided in a position excluding the annular outer periphery of the insulating layer 23. It can be said that the part of the insulating layer 23 that surrounds the heat dissipation copper 22 is provided as a creeping portion 25. The creeping portion 25 is a portion for ensuring insulation between the mounting copper 21 and the heat dissipation copper 22. In other words, the creeping portion 25 is a portion for ensuring a creeping distance between the mounting copper 21 and the heat dissipation copper 22.

Similarly, the heat dissipation copper 32 is provided at a position other than the annular outer periphery of the insulating layer 33. Therefore, it can be said that the portion of the insulating layer 33 surrounding the heat dissipation copper 32 is provided as a creeping portion 35. The creeping portion 35 is a portion for ensuring insulation between the mounting copper 31 and the heat dissipation copper 32.

<Third Substrate>
1 , the third substrate 50 is disposed on the semiconductor chips 11 and 12. The third substrate 50 is disposed opposite the source electrodes 11b and 12b. The third substrate 50 is a wiring member that electrically connects the high-side switch 11 and the low-side switch 12.

The third substrate 50 includes a first mounting copper 51a, a second mounting copper 51b, a heat dissipation copper 52, and an insulating layer 53. The first mounting copper 51a and the second mounting copper 51b are in contact with the insulating layer 53 on the surface facing the insulating layer 53. The heat dissipation copper 52 is in contact with the insulating layer 53 on the surface facing the insulating layer 53. Thus, the third substrate 50 has the first mounting copper 51a (second mounting copper 51b), the insulating layer 53, and the heat dissipation copper 52 stacked in this order.

As shown in FIG. 1, the first mounting copper 51a and the second mounting copper 51b are provided on the same surface of the insulating layer 53. However, as shown in FIG. 5, the first mounting copper 51a and the second mounting copper 51b are not in contact with each other, but are arranged at a distance. In this way, the third substrate 50 is provided with the first mounting copper 51a and the second mounting copper 51b as a single substrate. The first mounting copper 51a and the second mounting copper 51b are made of the same material as the mounting copper 21.

The first mounting copper 51a has a rectangular shape in a plan view. The first mounting copper 51a is provided from the opposing region of the source electrode 11b to the opposing region of the mounting copper 31.

The first mounting copper 51a is connected to the source electrode 11b of the high-side switch 11. More specifically, the first mounting copper 51a is connected to the first terminal 61 by solder 73. The first terminal 61 is then connected to the source electrode 11b. Thus, the first mounting copper 51a is connected to the source electrode 11b via the first terminal 61.

The first mounting copper 51a is connected to the mounting copper 31. More specifically, the first mounting copper 51a is connected to the joint terminal 63 by solder 78. The joint terminal 63 is connected to the mounting copper 31. Thus, the first mounting copper 51a is connected to the mounting copper 31 via the joint terminal 63. The high-side switch 11 corresponds to one semiconductor element. The first mounting copper 51a corresponds to the first wiring board.

The second mounting copper 51b has a shape that partially surrounds the first mounting copper 51a in a plan view. The second mounting copper 51b is integrally formed with a portion adjacent to the first mounting copper 51a in the X direction and two portions adjacent to the first mounting copper 51a in the Y direction. Therefore, the second mounting copper 51b has a shape in which a portion of the ring is cut off as an electrical path.

The second mounting copper 51b is connected to the source electrode 12b of the low-side switch 12. More specifically, the second mounting copper 51b is connected to the second terminal 62 by solder 76. The second terminal 62 is connected to the source electrode 12b. Thus, the second mounting copper 51b is connected to the source electrode 12b via the second terminal 62. The second mounting copper 51b has the second terminal 62 connected to a portion adjacent to the first mounting copper 51a in the X direction. The second mounting copper 51b has the negative terminal 42 connected to two portions adjacent to the first mounting copper 51a in the Y direction.

The low-side switch 12 corresponds to another semiconductor element. The second mounting copper 51b corresponds to the second wiring board. The negative terminal 42 corresponds to the second main terminal.

The heat dissipation copper 52 is made of the same material as the mounting copper 21. The surface of the heat dissipation copper 52 opposite the surface facing the insulating layer 53 is exposed from the sealing resin part 90. The heat dissipation copper 52 is a member that dissipates heat generated from the semiconductor chips 11, 12. In other words, the heat dissipation copper 52 receives heat from the semiconductor chips 11, 12 via the insulating layer 53 and dissipates the heat to the outside of the sealing resin part 90. The heat dissipation copper 52 has a V-cut part 54 on its side, similar to the mounting copper 21, 31.

The mounting copper 51a, 51b and the heat dissipation copper 52 may be made mainly of a metal other than copper. In the third substrate 50, the heat dissipation copper 52 is thicker than the mounting copper 51a, 51b. However, the heat dissipation copper 52 and the mounting copper 51a, 51b may have the same thickness. Furthermore, the mounting copper 51a, 51b may be thicker than the heat dissipation copper 52.

The insulating layer 53 is disposed between the mounting copper 51a, 51b and the heat dissipation copper 52, and is a member that electrically insulates the mounting copper 51a, 51b from the heat dissipation copper 52.

<Sealing resin portion 90>
The sealing resin portion 90 integrally covers the semiconductor chips 11, 12, the first substrate 20, the second substrate 30, the terminals 41 to 45, the third substrate 50, the terminals 61 to 63, the solders 71 to 78, and the bonding wires 80. This enables the semiconductor device 101 to protect the semiconductor chips 11, 12, etc. from the external environment.

In addition, the surface of each of the heat dissipation coppers 22, 32, and 52 opposite the surface facing each of the insulating layers 23, 33, and 53 is exposed from the sealing resin portion 90. This allows the semiconductor device 101 to improve its heat dissipation properties.

As shown in FIG. 5, the terminals 41 to 45 are partially exposed from the sealing resin part 90, and the remaining parts are covered by the sealing resin part 90. The positive terminal 41, the negative terminal 42, and the gate terminal 45 on the high-side switch 11 side protrude in the same direction from the sealing resin part 90. The output terminal 43, the gate terminal 45 on the low-side switch 12 side, and the signal terminal 44 protrude in the same direction from the sealing resin part 90. The positive terminal 41 and the output terminal 43 protrude in the opposite direction from the sealing resin part 90.

As described above, the semiconductor device 101 has a configuration in which the semiconductor chips 11 and 12 are sandwiched between the first substrate 20, the second substrate 30, and the third substrate 50. Therefore, the semiconductor device 101 has a double-sided heat dissipation structure.

<Production Method>
A manufacturing method of the semiconductor device 101 will be described with reference to Figures 2, 3, 4, and 5. First, as shown in Figure 2, the lead frame 1 having the terminals 41 to 45 integrally formed thereon, the first substrate 20, and the second substrate 30 are prepared. The lead frame 1 is placed on a pedestal together with the first substrate 20 and the second substrate 30. At this time, the lead frame 1 is positioned by the positioning pin 200. The lead frame 1 is also provided with a through hole 411 as a reference hole. The positioning pin 200 is also passed through the through hole 411. As a result, the lead frame 1 is positioned with respect to the first substrate 20 and the second substrate 30.

At this time, as shown in FIG. 3, one end of the positive terminal 41 of the lead frame 1 is placed on the mounting copper 21. Also, one end of the output terminal 43 of the lead frame 1 is placed on the mounting copper 31. The negative terminal 42 is connected to the first mounting copper 51a. Therefore, as shown in FIG. 4, the negative terminal 42 is separated from the mounting copper 21.

With the lead frame 1 positioned as described above, one end of the positive terminal 41 is connected to the mounting copper 21 by ultrasonic bonding. Similarly, one end of the output terminal 43 of the lead frame 1 is connected to the mounting copper 31 by ultrasonic bonding.

The negative terminal 42 is then connected to the first mounting copper 51a. The signal terminal 44 and the gate terminal 45 are connected to the pads of the semiconductor chips 11 and 12 via bonding wires 80. Then, as shown in FIG. 5, a sealing resin part 90 is formed to integrally cover the semiconductor chips 11 and 12, the first substrate 20, the second substrate 30, the terminals 41 to 45, the third substrate 50, the terminals 61 to 63, the solders 71 to 78, and the bonding wires 80. The terminals 41 to 45 are separated from the frame part of the lead frame in which the sealing resin part 90 is formed.

＜Effects＞
The semiconductor device 101 includes a first substrate 20 and a second substrate 30 on which the semiconductor chips 11 and 12 are individually mounted as wiring substrates. Therefore, the semiconductor device 101 does not need to process the wiring substrate by cutting or the like in order to mount the semiconductor chips 11 and 12 having different potentials. Therefore, the semiconductor device 101 can be manufactured at low cost.

In addition, the first substrate 20 and the second substrate 30 have mounting copper 21, 31 that is thicker than the heat dissipation copper 22, 32. Therefore, the semiconductor device 101 can improve the dissipation of heat generated from the semiconductor chips 11, 12 compared to a configuration in which the heat dissipation copper 22, 32 is thicker than the mounting copper 21, 31.

In the semiconductor device 101, the third substrate 50 on the source electrodes 11b and 12b side is constructed as an integrated body as described above. Therefore, in the semiconductor device 101, the wiring from the positive terminal 41 to the output terminal 43 and the wiring from the output terminal 43 to the negative terminal 42 can be opposed to each other. In addition, the semiconductor device 101 can reduce the loop from the positive terminal 41 to the negative terminal 42. Therefore, the semiconductor device 101 can achieve low inductance.

A preferred embodiment of the present disclosure has been described above. However, the present disclosure is not limited to the above embodiment, and various modifications are possible without departing from the spirit of the present disclosure. Below, modifications 1 and 2 are described as other forms of the present disclosure. The above embodiment and modifications 1 and 2 can each be implemented alone, but can also be implemented in appropriate combination. The present disclosure is not limited to the combinations shown in the embodiments, and can be implemented in various combinations.

(Variation 1)
A semiconductor device 102 according to the first modification will be described with reference to Fig. 6. Here, the differences between the semiconductor device 102 and the semiconductor device 101 will be mainly described. The semiconductor device 102 differs from the semiconductor device 101 in the configurations of the first mounting copper 51a and the second mounting copper 51b.

The first mounting copper 51a has a solder absorbing groove 55 capable of accommodating solder 73, 78 that has overflowed from the opposing area of the first terminal 61 and the joint terminal 63. The second mounting copper 51b has a solder absorbing groove 55 capable of accommodating solder 76 that has overflowed from the opposing area of the second terminal 62. The solder absorbing groove 55 is a portion that is recessed from the surrounding area. The solder absorbing groove 55 corresponds to a recess.

(Variation 2)
A semiconductor device 103 according to the second modification will be described with reference to Fig. 7. Here, the differences between the semiconductor device 103 and the semiconductor device 101 will be mainly described. The semiconductor device 103 differs from the semiconductor device 101 in the configuration of the first substrate 20.

The heat dissipation copper 22 is provided around the opposing area of the connection between the mounting copper 21 and the positive terminal 41. In other words, the insulating layer 23 has a non-formed portion 26 in which the heat dissipation copper 22 is formed in the opposing area.

When ultrasonically bonding the positive terminal 41 and the mounting copper 21 of the first substrate 20, cracks may occur in the insulating layer 23. Even if a crack occurs in the insulating layer 23 of the first substrate 20, the insulation between the mounting copper 21 and the heat dissipating copper 22 can be ensured.

Although the present disclosure has been described with reference to an embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, while various combinations and forms are shown in the present disclosure, other combinations and forms including only one element, more, or less are also within the scope and concept of the present disclosure.

11...High-side switch, 11a...Drain electrode, 11b...Source electrode, 12...Low-side switch, 12a...Drain electrode, 12b...Source electrode, 20...First substrate, 21...Mounting copper, 22...Heat dissipation copper, 23...Insulating layer, 24...V-cut portion, 25...Surface portion, 26...Non-formed portion, 30...Second substrate, 31...Mounting copper, 32...Heat dissipation copper, 33...Insulating layer, 34...V-cut portion, 35...Surface portion, 41...Positive electrode terminal, 42...Negative electrode terminal terminal, 43...output terminal, 44...signal terminal, 45...gate terminal, 411...through hole, 50...third substrate, 51a...first mounting copper, 51b...second mounting copper, 52...heat dissipation copper, 53...insulating layer, 54...V-cut portion, 55...solder absorption groove, 61...first terminal, 62...second terminal, 63...joint, 71-78...solder, 80...bonding wire, 90...sealing resin portion, 101-103...semiconductor device, 200...positioning pin

Claims (7)

A semiconductor element (11, 12) having a first electrode (11a, 12a) provided on one surface and a second electrode (11b, 12b) provided on an opposite surface of the first surface, the semiconductor element having two or more different potentials;
Two or more wiring boards (20, 30) on which semiconductor elements are individually mounted;
A wiring member (50) that electrically connects each semiconductor element;
a sealing resin portion (90) that integrally seals the semiconductor element, the wiring board, and the wiring member;
Each wiring board has a mounting metal plate (21, 31) which is a mounting portion of each semiconductor element and is connected to the first electrode, a heat dissipation metal plate (22, 32) which dissipates heat generated from the semiconductor element, and an insulating layer (23, 33) which is disposed between the mounting metal plate and the heat dissipation metal plate and which electrically insulates the mounting metal plate and the heat dissipation metal plate,
the heat dissipation metal plate has a surface opposite to a surface facing the insulating layer exposed from the sealing resin portion,
The mounting metal plate is thicker than the heat dissipation metal plate. The semiconductor device according to claim 1, wherein the heat dissipation metal plate is provided in a portion of the insulating layer excluding the edge portion. the wiring member is disposed opposite the second electrode of each semiconductor element, and a first wiring board (51a) connected to the second electrode of one of the semiconductor elements and a second wiring board (51b) connected to the second electrode of the other semiconductor element are provided as a single substrate;
The semiconductor device further includes a first main terminal (41) connected to the mounting metal plate on which the semiconductor element connected to the first wiring board is mounted, and a second main terminal (42) connected to the second wiring board,
The semiconductor device according to claim 1 , wherein the first main terminal and the second main terminal protrude in the same direction from the sealing resin portion. The semiconductor device according to claim 3, wherein the first wiring board and the second wiring board are connected to conductive terminals (61, 62) arranged opposite the second electrode via solder (73, 76), and a recess (55) capable of accommodating the solder that overflows from the opposite area is provided around the opposite area of the terminals. The semiconductor device according to any one of claims 1 to 3, wherein the mounting metal plate has a convex shape on the side, and the apex of the convex shape is located closer to the mounting surface of the semiconductor element than to the contact surface with the insulating layer. The semiconductor device according to claim 3, wherein the mounting metal plate and the first main terminal are connected by ultrasonic bonding. The semiconductor device according to claim 6, wherein the heat dissipation metal plate is provided around the opposing area of the connection between the mounting metal plate and the first main terminal.

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