JP2022070439A - Multi-channel receiver circuit and radio receiver - Google Patents

Abstract

To reduce the scale of a circuit which performs simultaneous multi-channel reception by a direct sampling method.SOLUTION: A multi-channel receiver circuit includes: a digital orthogonal detection section 12 which integrally performs orthogonal detection of a plurality of signal waves in a manner to convert the carrier frequency of one signal wave among the plurality of signal waves into each DC component; a first low-pass filter part 16A which extracts a base band signal corresponding to the one signal wave from the plurality of signal waves after the orthogonal detection; first and second complex multiplication sections 14B, 14C which perform frequency shift in a manner to have the center frequency of the carrier frequency of the signal wave other than the one signal wave of the plurality of signal waves after the orthogonal detection arranged to be 0 Hz; and second and third low-pass filter parts 16B, 16C which extract, from the signal wave being output from the first and second complex multiplication parts 14B, 14C, a baseband signal corresponding to the signal wave having the center frequency of the carrier frequency arranged to be 0 Hz.SELECTED DRAWING: Figure 1

Description

The present invention relates to a multi-channel receiving circuit and a wireless receiving device, and more particularly to a multi-channel receiving circuit for simultaneously receiving multi-channels by a direct sampling method and a wireless receiving device including the multi-channel receiving circuit.

Conventionally, as a digital wave receiving device that selectively receives only a specific band signal from among a plurality of broadcast waves in which a plurality of digitally modulated multicarrier signals exist within a predetermined bandwidth, for example, a plurality divided into a fixed bandwidth. It is a digital wave receiver that receives digitally modulated multi-carrier broadcast waves arranged in the frequency band of, and has an FFT circuit that collectively converts received signals in multiple frequency bands into frequency region signals, and a frequency arrangement with a fixed bandwidth. A storage device that stores the above in advance and a selection device that selects a band signal having only a certain bandwidth according to the storage content of the storage device from the frequency region signals obtained by the FFT circuit are known. (Patent Document 1).

Japanese Unexamined Patent Publication No. 2000-196558

By the way, in order to realize simultaneous multi-channel reception by the direct sampling method, we are trying to realize a circuit configuration in which each receiving channel is orthogonally detected and the channel is divided by a low-pass filter using FPGA (abbreviation of Field Programmable Gate Array). Then, there is a problem that the orthogonal detection unit is required for the number of channels and the circuit scale is increased. In particular, since the orthogonal detection unit in the direct sampling method generally has a high sampling rate, there is a problem that the circuit scale is significantly increased if the orthogonal detection unit is provided for the number of channels.

Therefore, an object of the present invention is to provide a multi-channel receiving circuit and a wireless receiving device including the multi-channel receiving circuit, which can reduce the scale of a circuit that performs multi-channel simultaneous reception by a direct sampling method. ..

In order to solve the above problems, the invention according to claim 1 is a circuit for simultaneously receiving a plurality of signal waves having different channels, and the carrier frequency of any one of the plurality of signal waves. A digital orthogonal detection unit that collectively performs orthogonal detection of the plurality of signal waves so as to convert the central frequency of the The center frequency of the carrier frequency of the low-pass filter unit for channel selection for extracting the corresponding baseband signal and the carrier frequency of the signal wave other than the signal wave among the plurality of signal waves after the orthogonal detection is arranged at 0 Hz. The center frequency of the carrier frequency is arranged at 0 Hz from the multiplication unit corresponding to each of the signal waves other than the above signal wave and the signal wave output from the multiplication unit. A multi-channel receiving circuit characterized by having a low-pass filter unit for channel selection corresponding to each of the signal waves other than any of the above-mentioned signal waves, which extracts a baseband signal corresponding to the existing signal wave. be.

The invention according to claim 2 further includes a decimeter unit which converts the sampling frequency of the signal output from the digital orthogonal detection unit and performs downsampling processing in the multi-channel receiving circuit according to claim 1. It is characterized by.

The invention according to claim 3 is the plurality of signal waves in which the sampling frequency of the signal output from the low-pass filter unit is converted and downsampling processing is performed in the multi-channel receiving circuit according to claim 1 or 2. It is characterized by further having a decimeter unit corresponding to each of the above.

The invention according to claim 4 is characterized in that, in the multi-channel receiving circuit according to any one of claims 1 to 3, the invention is composed of an FPGA.

The invention according to claim 5 is a wireless receiving device comprising the multi-channel receiving circuit according to any one of claims 1 to 4.

According to the first aspect of the present invention, although multi-channel simultaneous reception is possible, only one orthogonal detection unit is required, so that the circuit scale when realizing multi-channel simultaneous reception processing by, for example, FPGA is reduced. It becomes possible to do. According to the invention of claim 1, since one signal wave is converted into a baseband signal at the time of orthogonal detection, a circuit for frequency-shifting each of a plurality of signal waves. Can be omitted, and the circuit scale can be reduced.

According to the second and third aspects of the invention, since the decimeter portion is provided, the sampling rate can be reduced, and for example, the filtering performance sufficient to divide the channel in the low-pass filter portion. (That is, it is possible to reduce the circuit scale by avoiding an increase in the number of filter taps required to secure the attenuation amount in the desired attenuation region).

According to the fourth aspect of the present invention, since each part of the multi-channel receiving circuit is configured by FPGA, it is possible to realize a multi-channel receiving circuit that operates efficiently.

According to the fifth aspect of the present invention, it is possible to exert the above-mentioned effects in a wireless receiving device that simultaneously receives multi-channels by a direct sampling method.

It is a functional block diagram which shows the schematic structure of the multi-channel receiving circuit which concerns on embodiment of this invention. It is a figure which shows the arrangement of the signal corresponding to each channel in an embodiment. (A) is a figure which shows the arrangement of the signal corresponding to each channel input to the RF interface part. (B) is a figure which shows the arrangement of the signal corresponding to each channel after processing by a digital orthogonal detection part. It is a figure which shows the arrangement of the signal corresponding to each channel output from the decimeter part after detection in an embodiment. It is a figure explaining the process which concerns on the signal wave whose carrier frequency is f1 in embodiment. (A) is a figure which shows the arrangement of the signal corresponding to each channel after processing by the 1st complex multiplication part. (B) is a figure explaining the process in the 2nd low-pass filter part. (C) is a diagram showing a signal corresponding to a signal wave having a carrier frequency of f1 output from the second LPF post-decimator unit. It is a figure explaining the process which concerns on the signal wave whose carrier frequency is f2 in embodiment. (A) is a figure which shows the arrangement of the signal corresponding to each channel after processing by the 2nd complex multiplication part. (B) is a figure explaining the process in the 3rd low-pass filter part. (C) is a diagram showing a signal corresponding to a signal wave having a carrier frequency of f2 output from the third LPF post-decimator unit. It is a figure explaining the process which concerns on the signal wave whose carrier frequency is f3 in an embodiment. (A) is a figure which shows the arrangement of the signal corresponding to each channel after processing by a decimeter part after detection. (B) is a figure explaining the process in the 1st low-pass filter part. (C) is a diagram showing a signal corresponding to a signal wave having a carrier frequency of f3 output from the first LPF post-decimator unit.

Hereinafter, the present invention will be described based on the illustrated embodiment. In the following, the characteristic configuration of the present invention will be described, and the description of the conventional mechanism for performing wireless communication will be omitted. Further, the vertical axis of FIGS. 2 to 6 is an axis representing the signal level and is an axis corresponding to the amplitude (dB).

FIG. 1 is a functional block diagram showing a schematic configuration of a multi-channel receiving circuit 1 according to an embodiment of the present invention. The multi-channel receiving circuit 1 is a circuit that simultaneously receives multi-channels by a direct sampling method, and in this embodiment, it is configured by an FPGA and incorporated in a wireless receiving device.

The signal (signal wave) received by the antenna (not shown) is subjected to necessary processing (specifically, for example, a desired signal is selected and amplified by a low noise amplifier, or a bandpass filter is applied. (The signal wave in a desired frequency band is extracted, etc.), and the analog signal is converted into a digital signal by the A / D converter 10 (Analog-to-Digital converter). The signal input to the A / D conversion unit 10 (and output from the A / D conversion unit 10) is an RF signal (RF: an abbreviation for Radio Frequency).

The RF signal output from the A / D conversion unit 10 is input to the multi-channel receiving circuit 1 via the RF interface unit 11 (RF: an abbreviation for Radio Frequency).

The multi-channel receiving circuit 1 according to the embodiment is a circuit for simultaneously receiving a plurality of signal waves having different channels, and sets the center frequency of the carrier frequency of any one of the plurality of signal waves. A digital orthogonal detection unit 12 that collectively performs orthogonal detection of a plurality of signal waves so as to convert them into a DC component having a frequency of 0 Hz, and a baseband signal corresponding to any of the above signal waves from a plurality of signal waves after orthogonal detection. The frequency is such that the center frequency of the carrier frequency of the first low-pass filter unit 16A for channel selection to be extracted and the carrier frequency of the signal wave other than the above-mentioned signal wave among the plurality of signal waves after orthogonal detection is arranged at 0 Hz. Signals output from the first and second complex multiplication units 14B and 14C and the first and second complex multiplication units 14B and 14C corresponding to the signal waves other than any of the above signal waves to be shifted. The second and third channels for channel selection corresponding to each of the signal waves other than any of the above signal waves, which extract the baseband signal corresponding to the signal wave whose center frequency of the carrier frequency is arranged at 0 Hz from the wave. The low-pass filter portions 16B and 16C of the above are provided.

The multi-channel receiving circuit 1 according to the embodiment further includes a post-detection decimeter unit 13 that converts the sampling frequency of the signal output from the digital orthogonal detection unit 12 and performs downsampling processing, and a first to third low-pass filter. With the first to third LPF post-decimator units 17A, 17B, 17C corresponding to each of a plurality of signal waves, which convert the sampling frequency of the signal output from the filter units 16A, 16B, 16C and perform downsampling processing. I am trying to have.

The digital orthogonal detection unit 12 has a real axis signal (specifically, cos (ωt); It is provided with a multiplication unit for multiplying (t is time) and a multiplication unit for multiplying an imaginary axis signal (specifically, −sin (ωt)) whose phase is advanced by 90 ° from the real axis signal, and digital signal processing. By orthogonal detection by, a complex signal represented by orthogonal coordinates of the real number component (I signal) constituting the real part and the imaginary number component (Q signal) constituting the imaginary part is generated. In each figure, the signal line and the imaginary part (Q signal; in other words, the orthogonal component and the Q signal component) that transmit the real part (I signal; in other words, the in-phase component and the I signal component) constituting the complex signal are transmitted. ) Is displayed as one signal line together with the signal line to be transmitted.

In this embodiment, in the digital orthogonal detection unit 12, as shown in FIG. 2, the carrier frequency (occupied band) input to the RF interface unit 11 (and output from the RF interface unit 11) is f1, Of the three signal waves of f2 and f3 (however, f1 <f2 <f3) (see FIG. 2A), the carrier frequency (occupied band) of the signal wave is f3, and the center frequency of the carrier frequency f3 is 0 Hz. The three signal waves are collectively detected and converted at right angles (see FIG. 2B).

The digital orthogonal detection unit 12 converts the signal wave having the carrier frequency (occupied band) f1 into a complex signal having the carrier frequency (occupied band) f1', and the signal wave having the carrier frequency (occupied band) f2. The carrier frequency (occupied band) is converted into a complex signal having f2', and the signal wave having a carrier frequency (occupied band) f3 is converted into a complex signal having a carrier frequency (occupied band) of 0. Complex signals with frequencies (occupied bands) f1', f2', and f3' are generated and output (however, f3'= 0). In this embodiment, that is, the digital orthogonal detection unit 12 converts a signal wave having a carrier frequency (occupied band) of f3 into a baseband complex signal having a center frequency of 0 Hz. The complex signal output from the digital orthogonal detection unit 12 is a digital signal, and fs in FIG. 2 is the sampling rate of the signal output from the A / D conversion unit 10.

After detection, the decimeter unit 13 receives the input of the complex signal output from the digital orthogonal detection unit 12, and converts the sampling frequency of the digital signal to 1 / m times (where m is a natural number) with respect to the complex signal. Sampling frequency conversion (in other words, sampling rate conversion) processing is performed. Specifically, the decimator unit 13 after detection acquires sampling values one by one at intervals of [m-1], reduces the sampling rate to 1/m, and performs downsampling processing.

After detection, the decimeter unit 13 passes signals of all channels to be received as shown in FIG. By passing through the decimeter unit 13 after detection, a complex signal having a carrier frequency (occupied band) of f1'is output as a signal having a center frequency of f1d, and a complex signal having a carrier frequency (occupied band) of f2'is centered. A complex signal having a frequency of f2d and a carrier frequency (occupied band) of f3'is output as a signal having a center frequency of f3d (however, f3'= 0, f3d = 0). In FIG. 3, fsd is the sampling rate after processing in the post-detection decimeter unit 13 corresponding to the sampling rate fs of the signal output from the A / D conversion unit 10, that is, fsd = fs / m. be.

The natural number m (referred to as “thinning constant m”) in the above, which determines the degree of conversion of the sampling frequency by the decimator unit 13 after detection, is not limited to a specific value, but is output from the digital orthogonal detection unit 12. After the detection, the sampling frequency of the signal input to the decimator unit 13 and the appropriate sampling frequency in the processing in the circuit in the subsequent stage are taken into consideration, and the appropriate values are set appropriately. Specifically, the thinning constant m is set to a value such that the sampling rate of the complex signal output from the decimeter unit 13 after detection (that is, fsd in FIG. 3) is in the range of about 500 to 1100 kps. It is more preferable, it is more preferable to set it to a value in the range of about 500 to 900 kps, and it is further preferable to set it to a value in the range of about 600 to 800 kps (however, sps: sample / Seconds). The sampling rate fsd of the complex signal output from the post-detection decimeter unit 13 satisfies that the absolute value of the maximum bandwidth of all signal channels to be passed through the post-detection decimeter unit 13 is smaller than fsd / 2. Must be set to.

The signal output from the decimeter unit 13 after detection is transferred in parallel to each of the first low-pass filter unit 16A, the first complex multiplication unit 14B, and the second complex multiplication unit 14C.

The first complex multiplier unit 14B receives the input of the signal output from the decimeter unit 13 after detection, and functions as a complex multiplier corresponding to the signal wave (in other words, the channel) whose carrier frequency (occupied band) is f1d. , It has a function of relatively shifting a signal having a center frequency of f1d by a predetermined amount on the frequency axis. Specifically, the first complex multiplication unit 14B is a real number axis signal (specifically, cos) of a local signal generated from the first orthogonal carrier oscillation unit 15B whose oscillation frequency is the frequency of the absolute value of the frequency f1d. (Ωt)) and an imaginary axis signal (specifically, sin (ωt)) whose phase is delayed by 90 ° from the real axis signal are input to perform frequency shift.

The first complex multiplication unit 14B complexly multiplies the input signal with respect to the signal wave having the carrier frequency f1d on the negative side to realize the phase rotation corresponding to the desired frequency shift amount, and the frequency shift is performed. As shown in FIG. 4A, the central frequency of the carrier frequency f1d of the signal wave having the carrier frequency (occupied band) f1d is converted into a DC component having a frequency of 0 Hz. That is, the first complex multiplication unit 14B converts a signal wave having a carrier frequency (occupied band) of f1d into a baseband complex signal having a center frequency of 0 Hz, which is frequency-shifted and output. .. In FIG. 4, fsd is the sampling rate after processing in the post-detection decimeter unit 13 corresponding to the sampling rate fs of the signal output from the A / D conversion unit 10, that is, fsd = fs / m. be.

The second complex multiplier unit 14C receives the input of the signal output from the decimeter unit 13 after detection, and functions as a complex multiplier corresponding to the signal wave (in other words, the channel) whose carrier frequency (occupied band) is f2d. , It has a function of relatively shifting a signal having a center frequency of f2d by a predetermined amount on the frequency axis. Specifically, the second complex multiplication unit 14C is a real number axis signal (specifically, cos) of a local signal generated from the second orthogonal carrier oscillation unit 15C having the frequency of the absolute value of the frequency f2d as the oscillation frequency. (Ωt)) and an imaginary axis signal (specifically, sin (ωt)) whose phase is delayed by 90 ° from the real axis signal are input to perform frequency shift.

By the second complex multiplication unit 14C, the signal wave having the carrier frequency f2d on the negative side is complexly multiplied by the input signal to realize the phase rotation corresponding to the desired frequency shift amount, and the frequency shift is performed. As shown in FIG. 5A, the center frequency of the carrier frequency f2d of the signal wave having the carrier frequency (occupied band) of f2d is converted into a DC component having a frequency of 0 Hz. That is, the second complex multiplication unit 14C converts a signal wave having a carrier frequency (occupied band) of f2d into a baseband complex signal having a center frequency of 0 Hz, which is frequency-shifted and output. .. In FIG. 5, fsd is the sampling rate after processing in the post-detection decimeter unit 13 corresponding to the sampling rate fs of the signal output from the A / D conversion unit 10, that is, fsd = fs / m. be.

The first low-pass filter unit 16A is a low-pass filter for channel selection, receives an input of a signal output from the decimeter unit 13 after detection, and is a complex signal having a center frequency of 0 Hz as shown in FIG. 6B. Is subjected to a filtering process to extract a baseband complex signal corresponding to a signal wave (in other words, a channel) having a carrier frequency (occupied band) of f3. In FIG. 6, fsd is the sampling rate after processing in the post-detection decimeter unit 13 corresponding to the sampling rate fs of the signal output from the A / D conversion unit 10, that is, fsd = fs / m. be.

The second low-pass filter unit 16B is a low-pass filter for channel selection, receives an input of a signal output from the first complex multiplication unit 14B, and has a center frequency of 0 Hz as shown in FIG. 4B. The complex signal is filtered to extract a baseband complex signal corresponding to a signal wave (in other words, a channel) having a carrier frequency (occupied band) of f1.

The third low-pass filter unit 16C is a low-pass filter for channel selection, receives an input of a signal output from the second complex multiplication unit 14C, and has a center frequency of 0 Hz as shown in FIG. 5B. The complex signal is filtered to extract a baseband complex signal corresponding to a signal wave (in other words, a channel) having a carrier frequency (occupied band) of f2.

The first LPF post-decimator unit 17A (LPF: an abbreviation for Low Pass Filter) receives an input of a baseband complex signal output from the first low-pass filter unit 16A, and samples a digital signal with respect to the complex signal. Sampling frequency conversion (in other words, sampling rate conversion) processing for converting the frequency to 1 / n times (where n is a natural number) is performed. Specifically, the first LPF post-decimator unit 17A acquires sampling values one by one at intervals of [n-1], reduces the sampling rate to 1/n, and performs downsampling processing.

As described above, as shown in FIG. 6C from the first LPF post-decimator unit 17A, the baseband complex corresponding to the signal wave (in other words, the channel) having the carrier frequency (occupied band) of f3 after the sampling frequency conversion. A signal is output. In FIG. 6, fsdd is the sampling rate after processing in the first LPF post-decimator unit 17A corresponding to the sampling rate fsd of the signal output from the post-detection decimeter unit 13, that is, fsdd = fsd /. n.

The second LPF post-decimator unit 17B receives the input of the baseband complex signal output from the second low-pass filter unit 16B, and the sampling frequency of the digital signal is multiplied by 1 / n (however, with respect to the complex signal). A sampling frequency conversion (in other words, a sampling rate conversion) process for converting n into a natural number) is performed. Specifically, the second LPF post-decimator unit 17B acquires sampling values one by one at intervals of [n-1], reduces the sampling rate to 1/n, and performs downsampling processing.

As described above, as shown in FIG. 4C, the baseband complex corresponding to the signal wave (in other words, the channel) having the carrier frequency (occupied band) of f1 after the sampling frequency conversion from the second LPF post-decimator unit 17B. A signal is output. In FIG. 4, fsdd is the sampling rate after processing in the second LPF post-decimator unit 17B corresponding to the sampling rate fsd of the signal output from the post-detection decimeter unit 13, that is, fsdd = fsd /. n.

The third LPF post-decimator unit 17C receives the input of the baseband complex signal output from the third low-pass filter unit 16C, and the sampling frequency of the digital signal is multiplied by 1 / n (however, with respect to the complex signal). A sampling frequency conversion (in other words, a sampling rate conversion) process for converting n into a natural number) is performed. Specifically, the third LPF post-decimator unit 17C acquires sampling values one by one at intervals of [n-1], reduces the sampling rate to 1/n, and performs downsampling processing.

As described above, as shown in FIG. 5C from the third LPF post-decimator unit 17C, the baseband complex corresponding to the signal wave (in other words, the channel) having the carrier frequency (occupied band) of f2 after the sampling frequency conversion. A signal is output. In FIG. 5, fsdd is the sampling rate after processing in the third LPF post-decimator unit 17C corresponding to the sampling rate fsd of the signal output from the post-detection decimeter unit 13, that is, fsdd = fsd /. n.

The natural number n (referred to as “thinning constant n”) in the above, which determines the degree of conversion of the sampling frequency by the first to third LPF post-LPF decimeters 17A, 17B, 17C, is not limited to a specific value. , The sampling frequency of the signal output from each of the first to third low-pass filter units 16A, 16B, 16C and input to each of the first to third LPF post-decimator units 17A, 17B, 17C and the subsequent stage. It is set to an appropriate value after considering an appropriate sampling frequency in the processing in the circuit. Specifically, the thinning constant n is, for example, the sampling rate of the complex signal output from the first to third LPF post-decimator units 17A, 17B, 17C (that is, fsdd in FIGS. 4C, 5C, and 6C). Is preferably set to a value within the range of about 100 to 250 kps, more preferably set to a value within the range of about 100 to 200 kps, and to be within the range of about 150 to 200 kps. It is more preferable that the value is set to a high value. The sampling rate fsdd of the complex signal output from the first to third LPF post-decimator units 17A, 17B, 17C is the total signal to be passed through the first to third LPF post-decimator units 17A, 17B, 17C. It needs to be set to satisfy that the absolute value of the maximum bandwidth of the channel is less than fsdd / 2.

The signals output from each of the first to third LPF post-LPF decimeter units 17A, 17B, and 17C go to a circuit in the subsequent stage (not shown) that is required as a wireless receiver and performs various processes such as demodulation. Is supplied.

According to the multi-channel reception circuit according to this embodiment, although multi-channel simultaneous reception is possible, only one orthogonal detection unit is required. Therefore, a circuit for realizing multi-channel simultaneous reception processing by, for example, FPGA. It is possible to reduce the scale. According to the multi-channel receiving circuit according to this embodiment, one signal wave (that is, a signal wave having a carrier frequency (occupied band) of f3) is converted into a baseband signal at the time of orthogonal detection. Therefore, one set of circuits for frequency-shifting each of the plurality of signal waves can be omitted, and the circuit scale can be reduced.

According to the multi-channel receiving circuit according to this embodiment, since the decimeter unit 13 is provided after detection, the sampling rate can be reduced, and the first to third low-pass filter units 16A, It is possible to reduce the circuit scale by avoiding an increase in the number of filter taps required to secure sufficient filtering performance (that is, the amount of attenuation in the desired attenuation region) for dividing the channels in 16B and 16C. Become.

Although the embodiment of the present invention has been described above, the specific configuration is not limited to the above-described embodiment, and even if there is a design change or the like within a range that does not deviate from the gist of the present invention. Included in the invention.

Specifically, in the above embodiment, three signal waves are input to the digital orthogonal detection unit 12, but the number of signal waves input to the digital orthogonal detection unit 12 is three. It is not limited to, and may be two or four or more.

Further, in the above embodiment, the three signal waves arranged adjacent to each other are input to the digital orthogonal detection unit 12, but at least a part of the signal waves are arranged apart from each other. The signal wave to be generated may be input to the digital orthogonal detection unit 12.

Further, in the above embodiment, the center of the carrier frequency of the signal wave having the highest frequency f3 (occupied band) among the three signal waves (see FIG. 2A) whose carrier frequency (occupied band) is f1, f2, and f3. Although the frequency is converted into a DC component having a frequency of 0 Hz, the center frequency of the carrier frequency of the signal wave of another carrier frequency (occupied band) may be converted into a DC component having a frequency of 0 Hz.

Further, in the above embodiment, the post-detection decimeter unit 13 and the first to third LPF post-decimator units 17A, 17B, 17C are provided, but having the decimeter unit is an essential configuration in the present invention. No, the post-detection decimeter unit 13 is not provided, the first to third LPF post-decimator units 17A, 17B, 17C are not provided, or the post-detection decimeter unit 13 and the first to third units are not provided. It may be possible not to have the decimeters 17A, 17B, 17C after the LPF.

1 Multi-channel receiver circuit 10 A / D conversion unit 11 RF interface unit 12 Digital orthogonal detection unit 13 Post-detection decimeter unit 14B First complex multiplication unit 14C Second complex multiplication unit 15B First orthogonal carrier oscillation unit 15C Second Orthogonal carrier oscillator 16A 1st low-pass filter 16B 2nd low-pass filter 16C 3rd low-pass filter 17A 1st LPF post-decimator 17B 2nd LPF post-decimeter 17C 3rd LPF post-decimator

Claims (5)

It is a circuit for receiving multiple signal waves with different channels at the same time.
A digital orthogonal detection unit that collectively performs orthogonal detection of the plurality of signal waves so as to convert the center frequency of the carrier frequency of any of the plurality of signal waves into a DC component having a frequency of 0 Hz.
A low-pass filter unit for channel selection that extracts a baseband signal corresponding to any one of the signal waves from the plurality of signal waves after orthogonal detection.
A signal other than the above-mentioned signal wave, which is frequency-shifted so as to arrange the center frequency of the carrier frequency of the signal wave other than the above-mentioned one of the plurality of signal waves after the orthogonal detection at 0 Hz. The multiplication part corresponding to each wave and
Corresponds to each of the signal waves other than any of the above signal waves, which extracts the baseband signal corresponding to the signal wave whose center frequency of the carrier frequency is arranged at 0 Hz from the signal wave output from the multiplication unit. Has a low-pass filter unit for channel selection,
A multi-channel receiving circuit characterized by that. Further having a decimeter unit that converts the sampling frequency of the signal output from the digital orthogonal detection unit and performs downsampling processing.
The multi-channel receiving circuit according to claim 1. Further having a decimeter unit corresponding to each of the plurality of signal waves, which converts the sampling frequency of the signal output from the low-pass filter unit and performs downsampling processing.
The multi-channel receiving circuit according to claim 1 or 2. Consists of FPGA,
The multi-channel receiving circuit according to any one of claims 1 to 3. The multi-channel receiving circuit according to any one of claims 1 to 4 is provided.
A wireless receiver characterized by that.

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