JP2017162363A - Device for managing information on access to rom - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide information for simply and quickly identifying a cause of an error on access to a ROM.SOLUTION: An embodiment of this invention has a mechanism holding information on access to a ROM. For example, when writing, deleting, reading or the like of the information to the ROM starts or ends, since the mechanism holding the information on access to the ROM is implemented, with the held information, the embodiment of this invention can be useful for identification of a cause of an error on access to the ROM.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an apparatus for managing information related to access to a ROM.

  Conventionally, a processor for a gaming machine used in a pachinko machine or a pachislot machine also called a revolving game machine, and a device related thereto are related to memory access such as writing, erasing, and reading information in a built-in ROM. There is no configuration for holding information indicating access (for example, the number of accesses or a flag indicating access), information indicating that access has been completed normally, and the like.

  Therefore, in the prior art, when an error occurs when information is written to, erased from, or read from the ROM by the ROM writer, the cause of the error cannot be determined. Examples of the cause of the error include an error caused by access to the ROM and an error caused by a device or apparatus other than the ROM. That is, in the prior art, since the cause of the error cannot be determined, in order to identify the cause of the error, it is necessary to investigate all devices and devices other than ROM and ROM.

  In the prior art, since information indicating that the ROM has been accessed is not stored, it has been necessary to investigate all devices and devices other than the ROM and ROM in order to identify the cause of the error. Therefore, since the manufacturer conducts an investigation after taking all the devices from the purchaser, a lot of man-hours are required for error analysis.

  Provides information to more easily and quickly identify the cause of errors related to ROM access.

  Conventionally, information about access to ROM has not been held. The embodiment of the present invention has a configuration for holding information related to access to a ROM. For example, by having a mechanism for holding information related to access to the ROM at the start and end of writing, erasing, reading, etc. of information to the ROM, the embodiment of the present invention uses the held information. , Can help identify the cause of errors related to ROM access.

  An apparatus according to an embodiment of the present invention includes a processor core, a ROM, a ROM writer communication circuit that communicates with a ROM writer for accessing the ROM, and an access information memory. The ROM writer communication circuit is connected to the ROM writer. In response to receiving the command and / or data, the processor core can access the ROM based on the command and / or data and store information related to the access in the access information memory.

  In the embodiment of the present invention, the access information includes writing start information indicating that writing of data to the ROM has started and writing end information indicating that writing of data to the ROM has ended. A set of read information including a read start information indicating that reading of data from the ROM has started and a read end information indicating that reading of data from the ROM has been completed, and erasing of ROM data has started. A set of erase information including erase start information indicating that the erase of the ROM data has been completed, and indicating that verification has been started to confirm the validity of the data from the ROM writer and the ROM data. A set of verify information including verify start information and verify end information indicating completion of verify, and blank check start information and ROM indicating that ROM data blank check has started Includes at least one set of blank confirmation information including blank confirmation end information indicating that blank confirmation of data has been completed, and / or access information is received by the ROM writer communication circuit from the ROM writer. At least one of ROM writer communication (reception) end information indicating that the ROM writer communication circuit has transmitted information to the ROM writer.

  In the embodiment of the present invention, after the ROM writer tries to access the ROM and before the processor core accesses, the processor core may store information indicating that the access is started in the access information memory. it can.

  In the embodiment of the present invention, the information indicating that the access is started can include at least read start information, write start information, erase start information, verify start information, and blank check start information.

  In an embodiment of the present invention, after the processor core accesses the ROM, the processor core can store information indicating that the access is terminated in the access information memory.

  In the embodiment of the present invention, the information indicating that access is to be completed can include at least read end information, write end information, erase end information, verify end information, and blank check end information.

  In the embodiment of the present invention, after the ROM writer communication circuit receives information from the ROM writer, the processor core receives ROM writer communication (reception) end information indicating that the ROM writer communication circuit has received information from the ROM writer. It can be stored in the access information memory.

  In an embodiment of the present invention, the processor core transmits ROM writer communication (transmission) end information indicating that the ROM writer communication circuit has transmitted information to the ROM writer after the ROM writer communication circuit has transmitted information to the ROM writer. It can be stored in the access information memory.

  In an embodiment of the present invention, the device is a gaming machine device.

  In an embodiment of the present invention, the gaming machine chip may include a device.

  In an embodiment of the present invention, the gaming machine substrate may include a device or a chip.

  In an embodiment of the present invention, the gaming machine may include a gaming machine substrate.

1 shows an apparatus according to an embodiment of the present invention. The memory space which the access information memory 128 has is shown. 3 shows a processing flow according to an embodiment of the present invention. The mode switching of the apparatus 100 is shown.

Example Figure 1 of the present invention shows an apparatus according to an embodiment of the present invention. The device 100 is connected to the ROM writer 10 and includes a processor core 105, a bus controller 110, a ROM writer communication circuit 112, a program storage device 115, a user ROM 125, and a work RAM 135. The processor core 105 is connected to the ROM writer communication circuit 112, the program storage device 115, the user ROM 125, and the work RAM 135 via the bus controller 110. Device 100 may be implemented on a single chip. The device 100 may be a one-chip processor, a processor called a microcomputer, and the like mounted on one chip.

  The ROM writer 10 is connected to the ROM writer communication circuit 112 of the apparatus 100. The apparatus 100 can be detachably attached to the ROM writer 10. The ROM writer communication circuit 112 receives a command for writing to the ROM and / or data for performing the writing from the ROM writer 10, and the processor core 105 performs control stored in the program storage device 115. Based on the received program and / or data, the user ROM 125 is blank-checked and verified, and data is written to, read from, and erased from the user ROM 125 based on the program. Further, the processor core 105 stores information regarding execution of blank check and verification, and information regarding execution of data writing, reading, and erasing in the user ROM 125 in the access information memory 128 of the user ROM 125.

  The processor core 105 can perform blank check and verification of the user ROM 125 based on the command received by the ROM writer communication circuit 112. The blank check can confirm whether a part or all of the user ROM 125 is blank, and is used, for example, to confirm that the data has been erased after the data is erased from the user ROM 125. In the verification, for example, the data of the ROM writer 10 and the data of the user ROM 125 can be compared to confirm whether the data has been correctly written.

  Based on the command received by the ROM writer communication circuit 112, the processor core 105 writes the data received by the ROM writer communication circuit 112 into the area of the user program 127 in the user ROM 125. The data received from the ROM writer 10 can be a user program for operating the gaming machine, data used by the user program, or the like. Further, the processor core 105 can read and erase data in the area of the user program 127 in the user ROM 125 based on the command received by the ROM writer communication circuit 112.

  In the gaming machine device 100, a development device and a mass production device may be used. In this case, a plurality of times can be written in the user ROM 125 of the development device, and the user ROM 125 of the mass production device can be written. The device 100 may be controlled so that writing can be performed only once. In one embodiment, the development device is controlled so that the ROM contents can be erased, and the mass production device is controlled so that the ROM contents cannot be erased. In mass production devices, ROM can not be erased, so writing can only be performed once. In this case, the processor core 105 may control whether or not the contents of the ROM can be erased. For example, the processor core 105 can confirm a predetermined flag set in advance in the program storage device 115 and / or the user ROM 125, and can determine that the device is for development if the flag is on. . In another embodiment, the development device and the mass production device may be implemented by dedicated hardware, for example.

  The ROM writer 10 can access the user ROM 125 when the apparatus 100 is in a predetermined mode called a PROM mode. Switching to the PROM mode can be performed at a terminal in the apparatus 100. In a normal mode other than the PROM mode, the device 100 operates based on the control program 117 stored in the program storage device 115 and / or the user program 127 stored in the user ROM 125.

  FIG. 4 shows the mode switching of the device 100. A power-on reset, a system reset, or the like is performed in the apparatus 100 (state 405). The apparatus 100 determines whether the terminal input state is the PROM mode state. At this time, the terminal input state can be “LOW-level”, “HIGH-level”, “0”, “1”, or the like. When not in the PROM mode, for example, in the security mode (state 410), the ROM writer 10 cannot access the ROM of the device 100. In the security mode, the device 100 checks the rationality of the user program in the user ROM 125 to confirm whether the security of the device 100 has been established. If the security has been established, the device 100 enters the user mode and can start controlling the gaming machine (state 415). In the PROM mode (state 420), the ROM writer 10 can access the ROM of the device 100. Here, the rationality of the user program is checked by recalculating the security code (checksum, hash value, etc.) that has been calculated and stored in advance and comparing the recalculation with the security code. The

  The processor 105 further operates in the user mode based on user programs and data stored in the user ROM 125, and controls the work RAM 135 and other components to operate the gaming machine.

  Regarding the storage device and the memory, typically, the program storage device 115 is a ROM, and the program storage device 115 and the user ROM 125 may be realized by one ROM. In other embodiments, the program storage device 115 may be a non-volatile RAM.

  FIG. 2 shows a memory space included in the access information memory 128. The access information memory 128 includes a write start information area 205, a write end information area 210, a read start information area 215, a read end information area 220, an erase start information area 225, an erase end information area 230, a verify start information area 235, A verification end information area 240, a blank check start information area 245, a blank check end information area 250, a ROM writer communication (transmission) end information area 255, and a ROM writer communication (reception) end information area 260 may be included.

  Write start information area 205, write end information area 210, read start information area 215, read end information area 220, erase start information area 225, erase end information area 230, verify start information area 235, verify end information area 240 blank The confirmation start information area 245, the blank confirmation end information area 250, the ROM writer communication (transmission) end information area 255, and the ROM writer communication (reception) end information area 260 store access information to the user ROM 125.

  Regarding the access information, the write start information area 205 stores write start information that is information indicating that the ROM writer 10 starts writing data to the user ROM 125 (that is, data is about to be written). To do. As an example of the write start information, after the ROM writer 10 tries to write data to the user ROM 125, the write start information is stored in the write start information area 205 before the data is written to the user ROM 125. .

  The write end information area 210 stores write end information, which is information indicating that the ROM writer 10 finishes writing data to the user ROM 125 (that is, has written data). As an example of the write end information, the write end information is stored in the write end information area 210 after the ROM writer 10 writes data to the user ROM 125.

  Specifically, when the ROM writer 10 writes to the device 100 and starts writing data to the user ROM 125, the ROM writer communication circuit 112 receives a write command and data from the ROM writer 10. The processor core 105 determines that the command received by the ROM writer communication circuit 112 is writing, and stores the writing start information in the writing start information area 205 of the user ROM 125. Then, the processor core 105 once writes the data received by the ROM writer communication circuit 112 to the work RAM 135 and writes the data to the user program 127 area of the user ROM 125. Thereafter, the processor core 105 stores the write end information in the write end information area 210 of the user ROM 125. At this time, the reception result of the received data from the ROM writer 10 may be recorded in the write start information area 205, the write end information area 210, and / or another area, or another storage device. The reception result of the reception data may include a check result such as a check code of the reception data or received block information in the case where the write data is transmitted in a plurality of blocks. Further, the processor core 105 transmits the end of the write command and the result information to the ROM writer 10 through the ROM writer communication circuit 112.

  When the ROM writer 10 reads the device 100 and starts reading data from the user ROM 125, the ROM writer communication circuit 112 receives a read command from the ROM writer 10, and the processor core 105 is received by the ROM writer communication circuit 112. It is determined that the command is read, and the read start information is stored in the read start information area 215 of the user ROM 125. The processor core 105 once reads the user program 127 in the user ROM 125 to the work RAM 135, and the processor core 105 stores the read end information in the read end information area 220 of the user ROM 125, and the ROM writer communication circuit 112. The read data, the end of the read command and the result information are transmitted to the ROM writer 10.

  As another command, when the ROM writer 10 performs verification, erasure, and blank confirmation on the apparatus 100, the execution result of the command is transmitted to the ROM writer 10 by the ROM writer communication circuit 112 in the same manner as the above writing and reading.

  A set of erase start information area 225 and erase end information area 230, a set of verify start information area 235 and verify end information area 240, and a set of blank check start information area 245 and blank check end information area 250 are also included. Similarly to the set of the write start information area 205 and the write end information area 210 and the set of the read start information area 215 and the read end information area 220, respectively, the read start information, the read end information, and the erase start information In addition, erase end information, verify start information and verify end information, blank check start information and blank check end information are stored. Therefore, after the ROM writer 10 tries to access the user ROM 125 and before the processor core 105 accesses, the processor core 105 stores information indicating that the access is started in the access information memory 128. After the processor core 105 accesses the user ROM 125, the processor core 105 stores in the access information memory 128 information indicating that access is to be terminated. Here, the information indicating that access is started includes at least one of read start information, write start information, erase start information, verify start information, and blank check start information, and information indicating that access is completed is read It includes at least one of end information, write end information, erase end information, verify end information, and blank check end information.

  In the ROM writer communication (transmission) end information area 255, when the ROM writer communication circuit 112 transmits information to the ROM writer 10, the processor core 105 transmits the ROM writer communication (transmission) end information to the ROM writer communication (transmission). Saved in the end information area 255. As ROM writer communication (transmission) end information, a transmission command, arrival confirmation information (such as the number of retries), and / or an error code may be recorded. At this time, the transmission time or the like may be recorded. In the ROM writer communication (reception) end information area 260, when the ROM writer communication circuit 112 receives information from the ROM writer 10, the processor core 105 transmits the ROM writer communication (reception) end information to the ROM writer communication (reception). Saved in the end information area 260. As the ROM writer communication (reception) end information, information related to reception such as a reception command, the number of reception errors, and / or information for determining the communication quality of the communication path such as the number of command errors may be recorded. At this time, the reception information may include a reception time. As a result, information indicating whether or not information has been transmitted and received between the ROM writer 10 and the ROM writer communication circuit 112 is stored in the ROM writer communication (transmission) end information area 255 and the ROM writer communication (reception) end information area 260. It is saved and can be used for later error analysis.

  In the embodiment of the present invention, since information related to writing to the user ROM 125 is stored, the write start information in the write start information area 205 and the write end information in the write end information area 210 It is possible to specify whether or not an error has occurred during the writing of data to the user ROM 125. For example, assuming that the write start information and the write end information to be stored when writing to the ROM is performed normally have the same value, if the write start information is different from the write end information, Since the write start information or the write end information is not correctly stored, it is specified that an error has occurred during the writing of data to the user ROM 125. In another embodiment, when an error occurs, information indicating the error may be stored in the write start information and / or the write end information. Similarly, using the read start information and read end information, erase start information and erase end information, verify start information and verify end information, and blank check start information and blank check end information, reading and erasing to the user ROM 125 Thus, it can be confirmed whether the verification and the blank check are correctly performed.

  Regarding the contents of the access information, write start information, write end information, read start information, read end information, erase start information, erase end information, verify start information, verify end information, blank check start information, blank check end information, The ROM writer communication (transmission) end information and the ROM writer communication (reception) end information can be a flag or the number of times and / or a time. As will be understood by those skilled in the art, the information may be in other forms as long as it is information that can specify whether an error has occurred or the content of the error by referring to the information.

  In this embodiment, the stored access information 128 can be read out by executing an access information read command to the device 100 by the ROM writer 10 or a dedicated analysis device. In addition, the data can be read by an external device such as a tester directly accessing the access information memory 128 via a test circuit built in the device 100 (not shown).

  Regarding update of access information, write start information, write end information, read start information, read end information, erase start information, erase end information, verify start information, verify end information, blank check start information, blank check end information, When ROM writer communication (transmission) end information and ROM writer communication (reception) end information are flags, each write, read, erase, verify, blank check, ROM writer communication (transmission), ROM writer communication (reception) It is cleared before the process is performed or after the process is performed (for example, the flag is set to OFF). For example, writing start information and writing end information are cleared before writing or after writing is performed, and reading start information and reading end information are read before reading or reading is performed. The erase start information and the erase end information are cleared before the erase is performed or after the erase is performed, and the verify start information and the verify end information are performed before the verification or the verification is performed. The blank check start information and the blank check end information are cleared before the blank check is performed or after the blank check is performed, and the ROM writer communication (transmission) end information is stored in the ROM writer 10 as data. Is cleared before the data is transmitted or after the data is transmitted to the ROM writer 10, and the ROM writer communication (reception) end information is read from the ROM writer 10. Cleared from or ROM writer 10 before signal after receiving the data.

  Regarding update of access information, write start information, write end information, read start information, read end information, erase start information, erase end information, verify start information, verify end information, blank check start information, blank check end information, When the ROM writer communication (transmission) end information and the ROM writer communication (reception) end information are the number of times, the write start information and the write end information are incremented when the write start and the write end are performed, respectively. The read start information and the read end information are incremented when the read start and the read end are performed, respectively. The erase start information and the erase end information are incremented when the erase start and the erase end are performed, respectively. The start information and verify end information are respectively displayed when verify start and verify end are performed. Incremented, blank confirmation start information and blank confirmation end information are incremented when blank confirmation start and blank confirmation end are performed, respectively, ROM writer communication (transmission) end information and ROM writer communication (reception) end information, Each is incremented when transmission and reception of ROM writer communication is performed.

  Regarding update of access information, write start information, write end information, read start information, read end information, erase start information, erase end information, verify start information, verify end information, blank check start information, blank check end information, When the ROM writer communication (transmission) end information and the ROM writer communication (reception) end information are times, the writing start information and the writing end information are times when the writing start and the writing end are performed, respectively. Yes, read start information and read end information are times when read start and read end are performed, respectively. Erase start information and erase end information are times when erase start and erase end are performed, respectively. Yes, the verify start information and the verify end information are the times when the verify start and verify end are performed, respectively. Start information and blank check end information can be respectively, the time when the blank check start and a blank check completion is performed. Thereby, it is specified that an error has occurred by comparing the times of the start information and the end information. For example, compare the update time of the write start information with the update time of the write end information, and if the update time of the write start information is not earlier than the update time of the write end information, an error will occur when writing to the ROM. When it is identified that the update has occurred and the update time of the write start information is earlier than the update time of the write end information, it is specified that no error has occurred when writing to the ROM.

  The ROM writer communication (transmission) end information and the ROM writer communication (reception) end information can be times when the ROM writer communication (transmission) and the ROM writer communication (reception) are performed, respectively. As a result, the communication time with the ROM writer when an error occurs can be specified.

  In this embodiment, the time may be date information as well as time information. If the device 100 includes a circuit (eg, a timer circuit) having time information such as a timer, such a circuit can provide the time to the processor core 105. In another embodiment, when the device 100 does not include a circuit having time information such as a timer, the ROM writer 10 may transmit the time information to the ROM writer communication circuit 112. In this case, the processor core 105 uses the time information transmitted by the ROM writer 10 as the access start time for reading ROM data, and the access end time indicating the end time of processing such as reading ROM data is used as the access start time and the processor You may make it calculate based on the clock number of the core 100. FIG.

  In another embodiment, write start information, write end information, read start information, read end information, erase start information, erase end information, verify start information, verify end information, blank check start information, blank check end information, The ROM writer communication (transmission) end information and the ROM writer communication (reception) end information can be a combination of time and flag or number of times. This makes it possible to improve the accuracy of error determination and analysis of the cause of error because the determination of error occurrence is performed by two elements, update time and flag or number of times, and the time at which the error will occur is obtained. Can do.

  The non-volatile memory may have a write life, but in other embodiments, when the write end information is stored in the number of times, the number of times of writing can be managed, and the ROM writer 10 writes each time. If the number of times of writing is checked, the remaining number of times of writing can be displayed or the number of times of writing can be limited.

  In another embodiment, writing, reading, and erasing access to the user program may be performed in units of blocks (for example, 1024 bytes). In this case, writing start information, writing end information, and reading start information The read end information, erase start information, erase end information, verify start information, verify end information, blank check start information, and blank check end information may be information for each block.

  In another embodiment, the ROM writer communication (reception) end information includes a part or all of the information (for example, command and / or data) received by the ROM writer communication circuit 112 in combination with the above information or alone. It may be saved. In the ROM writer communication (transmission) end information, a part or all of the information transmitted by the ROM writer communication circuit 112 may be stored together with the above information or independently. As a result, the contents of communication when an error will occur can be obtained, so that the accuracy of error determination and error cause analysis can be further improved.

  In another embodiment, the access information has a ring buffer structure, and each command reception information, command start / end information, result transmission information, etc. are stored in the ring buffer as an execution history and accessed from a ROM writer or other analysis device. Can be read out and analyzed as a history.

  As will be appreciated by those skilled in the art regarding the updating of access information, the access information may be updated by other methods and other contents than those described above.

  FIG. 3 shows a processing flow according to an embodiment of the present invention. Processing is disclosed (step 310), and the ROM writer communication circuit 112 receives commands and / or data from the ROM writer 10 (step 312). The processor core 105 or the ROM writer communication circuit 112 determines whether or not there is an error in communication with the ROM writer 10 (step 314). If there is an error (step 314), the processor core 105 stores the communication error information in the access information memory 128 of the user ROM 125 (step 318). As an example of the communication error information, an error content, an error code indicating the error content, and a communication content when an error occurs can be one or a combination. When there is no communication error (step 314), the processor core 105 displays ROM writer communication (reception) end information indicating that the ROM writer communication (reception) has ended, in the ROM writer communication (reception) end information area. 260 (step 316).

  The processor core 105 determines whether the command to the user ROM 125 is a write (step 320). When the command is a write (step 320), the processor core 105 stores the write start information in the access information memory 128 (step 322). Thereafter, the processor core 105 writes the data received by the ROM writer communication circuit 112 into the user ROM 125 (step 324). The processor core 105 stores the write end information in the access information memory 128 (step 326).

  When the command processing is completed, the processor core 105 transmits the execution result of the command to the ROM writer 10 (step 328). The processor core 105 stores ROM writer communication (transmission) end information indicating that the ROM writer communication (transmission) has ended in the ROM writer communication (transmission) end information area 260 (step 330).

  In step 322 to step 326, if an error occurs during writing to the user ROM 125, information indicating the generated error is stored as write end information, and the access information memory 128 can be analyzed after the error has occurred. . In one embodiment, it may be determined that an error has occurred by performing comparison or calculation using both the write start information and the write end information.

  In one embodiment, the write start information and write end information can be flags, and the flags may be cleared before step 322. In another embodiment, if the writing is completed normally, the flag of the writing start information and the writing end information may be cleared after step 326.

  In one embodiment, when the write start information and the write end information are the number of times, the write start information and the write end information are given a space that can take a sufficiently large value in their memory space, It can be prevented from being cleared. In another embodiment, when the writing start information and the writing end information are the number of times, the writing start information and the writing end information may not be cleared, or numerical values that circulate in the same range (for example, , 0 to 7, and 0 to 127.

  When the access to the user ROM 125 of the ROM writer 10 is not writing (step 320) and the access to the user ROM 125 of the ROM writer 10 is reading (step 332), the processor core 105 displays the read start information. The access information is stored in the access information memory 128 (step 334). Thereafter, the processor core 105 reads data from the user ROM 125 to the work RAM (step 336). The processor 105 stores the read end information in the access information memory 128 (step 338). Thereafter, steps 328 and 330 are executed.

  In step 334 to step 338, if an error occurs when reading data from the user ROM 125, information indicating the generated error is stored as read end information, and the access information memory 128 can be analyzed after the error has occurred. In one embodiment, it may be determined that an error has occurred by performing comparison or calculation using both the read start information and the read end information.

  The ROM writer 10 does not write to the user ROM 125 (step 320), the ROM writer 10 does not access the user ROM 125 (step 332), and the ROM writer 10 has no access to the user ROM 125. In the case of confirmation (step 340), the processor core 105 stores blank confirmation start information in the access information memory 128 (step 342). Thereafter, the processor core 105 performs blank confirmation (also referred to as blank check) (step 344). The processor core 105 stores blank confirmation end information in the access information memory 128 (step 346). Thereafter, steps 328 and 330 are executed.

  In step 342 to step 346, if an error occurs during blank confirmation of the user ROM 125, information indicating the generated error is stored as blank confirmation end information, and the access information memory 128 can be analyzed after the error has occurred. In one embodiment, it may be specified that an error has occurred by performing comparison, calculation, or the like using both blank check start information and blank check end information.

  The ROM writer 10 does not write to the user ROM 125 (step 320), the ROM writer 10 does not access the user ROM 125 (step 332), and the ROM writer 10 has no access to the user ROM 125. When the access to the user ROM 125 of the ROM writer 10 is verification (step 348) instead of confirmation (step 340), the processor core 105 stores the verification start information in the access information memory 128 (step 350). Thereafter, the processor core 105 verifies the data in the user ROM 125 (step 352). The processor core 105 stores the verification end information in the access information memory 128 (step 354). Here, as an example of verification, it is compared whether the data in the user ROM 125 is the same as the data included in the ROM writer 10. In one embodiment, for verification, the processor core 105 receives a verification command and data from the ROM writer 10, and compares part or all of the data in the user ROM 125 with part or all of the data received from the ROM writer 10. To do. If the data in the user ROM 125 is the same as the data received from the ROM writer 10, the processor core 105 determines that the data in the user ROM 125 is valid, and if not, determines that the data in the user ROM 125 is not valid. The processor core 105 returns the result of determining whether it is valid or not to the ROM writer 10 (step 328). Thereafter, step 330 is executed.

  In step 350 to step 354, if an error occurs during verification of the user ROM 125, information indicating the generated error is stored as verification end information, and the access information memory 128 can be analyzed after the error has occurred. In one embodiment, it may be specified that an error has occurred by performing comparison or calculation using both the verification start information and the verification end information.

  The ROM writer 10 does not write to the user ROM 125 (step 320), the ROM writer 10 does not access the user ROM 125 (step 332), and the ROM writer 10 has no access to the user ROM 125. If it is not confirmed (step 340), access to the user ROM 125 of the ROM writer 10 is not verify (step 348), and access to the user ROM 125 of the ROM writer 10 is erasure (step 356), the processor core 105 Then, it is determined whether or not the apparatus 100 is for mass production (step 358).

  As described above, in one embodiment, the processor core 105 checks the predetermined mass production (0) / development (1) determination flag in the program storage device 115 and / or the user ROM 125, and the flag is on (1). , It can be determined that the device is for development. Further, the processor core 105 is provided by other means. It may be determined whether the device 100 is for development or mass production.

  When the apparatus 100 is for mass production (step 358), the processor core 105 returns a result indicating that erasure to the user ROM 125 is not permitted to the ROM writer 10 (step 328). If the device 100 is not for mass production (step 358) (eg, if it is a development device), the processor core 105 stores the erase start information in the access information memory 128 (step 360). Thereafter, the processor core 105 erases data in the user ROM 125 (step 362). The processor core 105 stores the erasure end information in the access information memory 128 (step 364). Thereafter, steps 328 and 330 are executed.

  In step 360 to step 364, if an error occurs during erasure of the user ROM 125, information indicating the generated error is stored as erasure end information, and the access information memory 128 can be analyzed after the error has occurred. In one embodiment, it may be specified that an error has occurred by performing comparison, calculation, or the like using both the erase start information and the erase end information.

  Read start information and read end information, blank check start information and blank check end information, verify start information and verify end information, and erase start information and erase end information are the same as the write start information and write end information. It can be a flag that is a cleared value, a number of times that it is not cleared, or a circulating numerical value.

  After processing related to reading of the user ROM 125 (after step 338), processing related to blank confirmation of the user ROM 125 (after step 346), processing related to verification of the user ROM 125 (after step 354), or user ROM 125 After the process related to erasure (after step 364), the process proceeds to step 328 where the processor core 105 returns the execution result to the ROM writer 10, and then step 330 is executed. However, with regard to the processing related to reading, the step 328 returned to the ROM writer 10 after the processing related to reading (after step 338) is to read the read data of the user program 127 in the user ROM once stored in the work RAM 135 into the ROM writer. The process which transmits to 10 is included.

  In one embodiment, the device 100 may be a gaming machine device that controls a gaming machine. In one embodiment, the device 100 shown in FIG. 1 may be implemented on a single chip. One such chip is referred to as a microcomputer, a microcomputer, a one-chip microcomputer, a processor chip, or the like. In this case, the processor 105 may be a processor core. In another embodiment, the device 100 mounted on one chip may be mounted on a substrate. In this case, in the gaming machine, a gaming machine using the board as a main board and a sub board may be configured. In the gaming machine, the main board mainly controls the lottery of the gaming machines, and the sub board controls the payout and / or effect of the gaming machine.

  In the above embodiment, some or all of some elements described to be realized by hardware can be realized by software, and some elements described to be realized by software It will be understood that some or all of can be implemented in hardware.

  As long as there is no inconsistency in the processing or processing order in the processing or processing order described above, such as using data that should not be used in that processing, the processing or processing order. Can be changed freely.

  Regarding each embodiment described above, a part or all of each embodiment may be combined and realized as one embodiment.

  Each Example described above is an illustration for explaining the present invention, and the present invention is not limited to these Examples. The present invention can be implemented in various forms without departing from the gist thereof.

100 device 105 processor 110 bus controller 112 ROM writer communication circuit 115 program storage device 117 control program 125 user ROM
127 User program 128 Access information memory 135 Work RAM
205 Write start information area 210 Write end information area 215 Read start information area 220 Read end information area 225 Erase start information area 230 Erase end information area 235 Verify start information area 240 Verify end information area 245 Blank confirmation start information area 250 Blank Confirmation end information area 255 ROM writer communication (transmission) end information area 260 ROM writer communication (reception) end information area

Claims (12)

A device,
A processor core;
ROM,
A ROM writer communication circuit for communicating with a ROM writer for accessing the ROM;
An access information memory,
In response to the ROM writer communication circuit receiving a command and / or data from the ROM writer, the processor core accesses the ROM based on the command and / or data and displays information related to the access. An apparatus for storing in the access information memory.   The access information is a set of write information including write start information indicating that writing of data to the ROM has started and write end information indicating that writing of data to the ROM has ended, A set of read information including read start information indicating that reading of data from the ROM has started and read end information indicating that reading of data from the ROM has been completed, and erasing of data in the ROM has started A set of erase information including erase start information indicating and erase end information indicating completion of erasure of the ROM data, and verification for confirming the validity of the data from the ROM writer and the ROM data was started. A verification start information indicating that the verification has been completed, a verification information set including verification end information indicating that the verification has been completed, and a block indicating that the blank check of the ROM data has started. Includes at least one of a set of blank confirmation information including blank confirmation start information and blank confirmation end information indicating completion of blank confirmation of data in the ROM, and / or the access information includes the ROM ROM writer communication (reception) end information indicating that the writer communication circuit has received information from the ROM writer, and ROM writer communication (transmission) end information indicating that the ROM writer communication circuit has transmitted information to the ROM writer. The apparatus of claim 1, comprising at least one.   The information stored in the access information memory is stored in the access information memory after the ROM writer tries to access the ROM and before the processor core accesses the ROM. The device described in 1.   4. The apparatus according to claim 3, wherein the information indicating that the access is started includes at least one of read start information, write start information, erase start information, verify start information, and blank check start information.   5. The apparatus according to claim 2, wherein after the processor core accesses the ROM, the processor core stores information indicating that the access is terminated in the access information memory. 6. .   6. The apparatus according to claim 5, wherein the information indicating that the access is ended includes at least one of read end information, write end information, erase end information, verify end information, and blank check end information.   After the ROM writer communication circuit receives information from the ROM writer, the processor core accesses the ROM writer communication (reception) end information indicating that the ROM writer communication circuit has received information from the ROM writer. Apparatus according to any one of claims 2 to 6, stored in an information memory.   After the ROM writer communication circuit transmits information to the ROM writer, the processor core transmits ROM writer communication (transmission) end information indicating that the ROM writer communication circuit has transmitted information to the ROM writer. 8. A device according to any one of claims 2 to 7, stored in an information memory.   The device according to claims 1 to 8 is a device for a gaming machine.   A gaming machine chip comprising the device according to claim 1.   A gaming machine substrate comprising the device according to claim 1 or the chip according to claim 10.   A gaming machine comprising the gaming machine board according to claim 11.

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