JP2017108132A - Semiconductor device, display element, display device, and system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that can be manufactured by a simple manufacturing step, and that has an excellent adhesion property between source and drain electrodes and a lower layer.SOLUTION: A semiconductor device comprises: a base material; a gate electrode for applying a gate voltage; a source electrode and a drain electrode for extracting a current in responce to the application of the gate voltage; a semiconductor layer formed of an oxide semiconductor; and a gate insulating layer provided between the gate electrode and the semiconductor layer. The semiconductor layer has a channel formation region and a non-channel formation region. The channel formation region and the non-channel formation region are respectively formed so as to be contacted with the source electrode and the drain electrode.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device, a display element, a display device, and a system.

  Liquid crystal display (LCD), organic EL (electroluminescence) display (OLED), flat and thin displays such as electronic paper (Flat Panel Display: FPD) use amorphous silicon or polycrystalline silicon for the semiconductor layer It is driven by a driving circuit including a thin film transistor (TFT).

In the development of FPD, a TFT including a field effect transistor using an oxide semiconductor film having high carrier mobility and small variation between elements in a channel formation region of a semiconductor layer is manufactured, and an electronic device, an optical device, or the like The technology applied to is attracting attention. For example, a field-effect transistor using zinc oxide (ZnO), In ₂ O ₃ , In—Ga—Zn—O, or the like as an oxide semiconductor film has been proposed.

  As a field-effect transistor, for example, it is easy to reduce the contact resistance between a source electrode and a drain electrode, which are metal films, and a semiconductor layer, and the semiconductor layer is sandwiched between a base material, a gate insulating layer, and a gate electrode. A top gate / top contact type having a structure advantageous for blocking moisture and oxygen is used (see, for example, Patent Document 1).

  By the way, in a semiconductor device such as a top gate / top contact type field effect transistor, the metal film constituting the source electrode and the drain electrode is directly formed on the base material. A high value is important in stabilizing the TFT manufacturing process and the TFT function.

  Therefore, in order to improve the adhesion between the substrate and the metal film, a laminated structure of different metals is often used, such as providing a metal with high adhesion as an adhesive layer. However, manufacturing a source electrode and a drain electrode with a laminated structure of different metals has problems such as an increase in manufacturing steps, difficulty in processes, and an increase in manufacturing costs.

  The same applies to a semiconductor device such as a bottom gate / top contact field effect transistor in which a metal film constituting a source electrode and a drain electrode is directly formed on a gate insulating layer.

  An object of the present invention is to provide a semiconductor device that can be manufactured by a simple manufacturing process and has excellent adhesion between a source electrode and a drain electrode and a lower layer.

  The semiconductor device includes a base material, a gate electrode for applying a gate voltage, a source electrode and a drain electrode for taking out a current in response to the application of the gate voltage, a semiconductor layer made of an oxide semiconductor, A semiconductor device comprising a gate electrode and a gate insulating layer provided between the semiconductor layer, wherein the semiconductor layer includes a channel formation region and a non-channel formation region, and the channel formation region And the non-channel forming region are formed in contact with the source electrode and the drain electrode, respectively.

  According to the disclosed technology, it is possible to provide a semiconductor device that can be manufactured by a simple manufacturing process and that has excellent adhesion between the source and drain electrodes and the lower layer.

1 is a cross-sectional view illustrating a field effect transistor according to a first embodiment. It is a figure which illustrates the manufacturing process of the field effect transistor which concerns on 1st Embodiment. It is sectional drawing which illustrates the field effect transistor which concerns on the modification of 1st Embodiment. 6 is a cross-sectional view illustrating a field effect transistor according to Comparative Example 1. FIG. It is a block diagram which shows the structure of the television apparatus in 2nd Embodiment. It is explanatory drawing (the 1) of the television apparatus in 2nd Embodiment. It is explanatory drawing (the 2) of the television apparatus in 2nd Embodiment. It is explanatory drawing (the 3) of the television apparatus in 2nd Embodiment. It is explanatory drawing of the display element in 2nd Embodiment. It is explanatory drawing of organic EL in 2nd Embodiment. Explanatory drawing of the television apparatus in 2nd Embodiment (the 4) It is explanatory drawing (the 1) of the other display element in 2nd Embodiment. It is explanatory drawing (the 2) of the other display element in 2nd Embodiment. It is a top view which illustrates the display element array which concerns on 3rd Embodiment. It is sectional drawing which follows the AA line of FIG. It is sectional drawing which follows the BB line of FIG. It is a top view which illustrates the formation area of the semiconductor layer in the display element array which concerns on 3rd Embodiment. It is a top view which illustrates the display element array which concerns on a comparative example.

  Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and redundant description may be omitted.

<First Embodiment>
[Structure of field effect transistor]
FIG. 1 is a cross-sectional view illustrating a field effect transistor according to the first embodiment. Referring to FIG. 1, the field effect transistor 10 includes a base material 11, a semiconductor layer 12, a source electrode 13, a drain electrode 14, a wiring 15, a gate insulating layer 16, and a gate electrode 17. This is a top gate / top contact type field effect transistor. The field effect transistor 10 is a typical example of a semiconductor device according to the present invention.

  In the field effect transistor 10, a semiconductor layer 12 is formed on an insulating base material 11, and a source electrode 13, a drain electrode 14, and a wiring 15 are formed on the semiconductor layer 12. Further, a gate insulating layer 16 is formed so as to cover the semiconductor layer 12, the source electrode 13, the drain electrode 14, and the wiring 15, and a gate electrode 17 is formed on the gate insulating layer 16. Hereinafter, each component of the field effect transistor 10 will be described in detail.

  In this embodiment, for the sake of convenience, the gate electrode 17 side is the upper side or one side, and the base material 11 side is the lower side or the other side. Further, the surface on the gate electrode 17 side of each part is the upper surface or one surface, and the surface on the substrate 11 side is the lower surface or the other surface. However, the field effect transistor 10 can be used upside down, or can be arranged at an arbitrary angle. Moreover, planar view refers to viewing the object from the normal direction of the upper surface of the base material 11, and planar shape refers to the shape of the object viewed from the normal direction of the upper surface of the base material 11. .

  The base material 11 is an insulating member serving as a base on which the semiconductor layer 12 and the like are formed. There is no restriction | limiting in particular as a shape of the base material 11, a structure, and a magnitude | size, According to the objective, it can select suitably. There is no restriction | limiting in particular as a material of the base material 11, Although it can select suitably according to the objective, For example, a glass base material, a plastic base material, etc. can be used. There is no restriction | limiting in particular as a glass base material, Although it can select suitably according to the objective, For example, an alkali free glass, a silica glass, etc. are mentioned. Moreover, there is no restriction | limiting in particular as a plastic base material, Although it can select suitably according to the objective, For example, a polycarbonate (PC), a polyimide (PI), a polyethylene terephthalate (PET), a polyethylene naphthalate (PEN) etc. Is mentioned.

The semiconductor layer 12 is made of an oxide semiconductor and is formed in a predetermined region on the base material 11. As the oxide semiconductor that forms the semiconductor layer 12, for example, an n-type oxide semiconductor can be used. The n-type oxide semiconductor is not particularly limited and may be appropriately selected depending on the intended purpose, for _{example, ZnO, SnO 2, In 2} O 3, TiO 2, Ga 2 O 3 and the like.

  In addition, as an n-type oxide semiconductor, an In—Zn-based oxide, an In—Sn-based oxide, an In—Ga-based oxide, a Sn—Zn-based oxide, a Sn—Ga-based oxide, a Zn—Ga-based oxide, or the like can be used. In-Zn-Sn-based oxide, In-Ga-Zn-based oxide, In-Sn-Ga-based oxide, Sn-Ga-Zn-based oxide, In-Al-Zn-based oxide, Al-Ga- An oxide containing a plurality of metals such as a Zn-based oxide, a Sn-Al-Zn-based oxide, an In-Hf-Zn-based oxide, and an In-Al-Ga-Zn-based oxide can also be used.

  An n-type oxide semiconductor has at least one of indium, zinc, tin, gallium, and titanium, an alkaline earth metal, and a point from which high field effect mobility can be obtained and the electron carrier concentration can be easily controlled. It is preferable to contain, and it is more preferable to contain indium and an alkaline earth metal. Examples of the alkaline earth metal include beryllium, magnesium, calcium, strontium, barium, and radium.

Indium oxide has an electron carrier concentration of about 10 ¹⁸ cm ⁻³ to 10 ²⁰ cm ⁻³ depending on the amount of oxygen deficiency. However, indium oxide has a property of easily causing oxygen vacancies, and there are cases where unintended oxygen vacancies may be formed in a later step after the formation of the oxide semiconductor film. Forming oxides from two metals, indium and an alkaline earth metal that is easier to bond with oxygen than indium, prevents unintentional oxygen vacancies and facilitates control of the composition. It is particularly preferable in terms of easy control.

  In the semiconductor layer 12, the electron carrier concentration can be controlled within an appropriate range by the elements constituting the semiconductor layer 12, the manufacturing process conditions, post-treatment after film formation, and the like. There is no restriction | limiting in particular as average thickness of the semiconductor layer 12, Although it can select suitably according to the objective, 1 nm-200 nm are preferable and 2 nm-100 nm are more preferable.

  The semiconductor layer 12 has a channel formation region 121 (active region) and a non-channel formation region 122 (inactive region). The channel formation region 121 and the non-channel formation region 122 are formed in contact with the source electrode 13, the drain electrode 14, and the wiring 15, respectively. All or part of the channel formation region 121 can function as a channel region. The non-channel formation region 122 can be arranged so as to surround the channel formation region 121 in a plan view, for example. The layer thickness of the channel formation region 121 and the layer thickness of the non-channel formation region 122 can be substantially the same.

  The source electrode 13 and the drain electrode 14 are formed in contact with the upper surface of the semiconductor layer 12. The source electrode 13 and the drain electrode 14 are partially overlapped with the channel formation region 121 of the semiconductor layer 12 and are formed with a predetermined interval as a channel region. The source electrode 13 and the drain electrode 14 are electrodes for taking out a current in response to application of a gate voltage.

  The material for the source electrode 13 and the drain electrode 14 is not particularly limited and may be appropriately selected depending on the intended purpose. Examples thereof include metals such as Mo, Al, Au, Ag, and Cu, and alloys thereof. It is done. There is no restriction | limiting in particular as average thickness of the source electrode 13 and the drain electrode 14, Although it can select suitably according to the objective, 40 nm-2 micrometers are preferable, and 70 nm-1 micrometer are more preferable.

  The wiring 15 is formed in the same layer as the source electrode 13 and the drain electrode 14 and is connected to the source electrode 13 and the drain electrode 14. The wiring 15 is formed in contact with the upper surface of the non-channel formation region 122.

  The wiring 15 is appropriately formed as necessary, and is a metal film that serves as a terminal for measuring the electrical characteristics of the semiconductor device, or a metal film that electrically connects between semiconductor devices included in a drive circuit described later, or And a metal film that electrically connects the drive circuit and the light control element, or a metal film that electrically connects the image data creation device and the drive circuit.

  There is no restriction | limiting in particular as a material of the wiring 15, Although it can select suitably according to the objective, For example, metals, such as Mo, Al, Au, Ag, Cu, these alloys, etc. are mentioned. The average thickness of the wiring 15 can be approximately the same as the average thickness of the source electrode 13 and the drain electrode 14.

  The gate insulating layer 16 is provided between the semiconductor layer 12 and the gate electrode 17 so as to cover the source electrode 13, the drain electrode 14, and the wiring 15. The gate insulating layer 16 is a layer for insulating the source electrode 13 and the drain electrode 14 from the gate electrode 17. There is no restriction | limiting in particular as a material of the gate insulating layer 16, Although it can select suitably according to the objective, For example, an inorganic insulating material, an organic insulating material, etc. are mentioned.

  Examples of the inorganic insulating material include silicon oxide, aluminum oxide, tantalum oxide, titanium oxide, yttrium oxide, lanthanum oxide, hafnium oxide, zirconium oxide, silicon nitride, aluminum nitride, and a mixture thereof. Examples of the organic insulating material include polyimide, polyamide, polyacrylate, polyvinyl alcohol, and novolak resin. There is no restriction | limiting in particular as average thickness of the gate insulating layer 16, Although it can select suitably according to the objective, 50 nm-1000 nm are preferable and 100 nm-500 nm are more preferable.

  The gate electrode 17 is formed in a predetermined region on the gate insulating layer 16. The gate electrode 17 is an electrode for applying a gate voltage. There is no restriction | limiting in particular as a material of the gate electrode 17, Although it can select suitably according to the objective, For example, platinum, palladium, gold | metal | money, silver, copper, zinc, aluminum, nickel, chromium, tantalum, molybdenum, titanium And the like, alloys thereof, mixtures of these metals, and the like.

Also, indium oxide, zinc oxide, tin oxide, gallium oxide, niobium oxide, In ₂ O ₃ (ITO) to which tin (Sn) is added, ZnO to which gallium (Ga) is added, and aluminum (Al) are added. Examples thereof include conductive oxides such as ZnO and SnO ₂ to which antimony (Sb) is added, composite compounds thereof, mixtures thereof, and the like. There is no restriction | limiting in particular as average thickness of the gate electrode 17, Although it can select suitably according to the objective, 10 nm-200 nm are preferable and 50 nm-100 nm are more preferable.

  As described above, in the field effect transistor 10, the channel formation region 121 and the non-channel formation region 122 constituting the semiconductor layer 12 are formed in contact with the source electrode 13, the drain electrode 14, and the wiring 15, respectively.

  That is, the source electrode 13, the drain electrode 14, and the wiring 15 are not in direct contact with the base material 11, and the channel formation region 121 made of an oxide semiconductor having excellent adhesion to glass, silicon, silicon oxide film, or the like is not used. It is in contact with the channel formation region 122 (adhesion layer).

  With such a structure, adhesion to the lower layer of the source electrode 13, the drain electrode 14, and the wiring 15 is improved, and excellent film stability (resistance to the manufacturing process) can be obtained.

[Method for Manufacturing Field Effect Transistor]
Next, a method for manufacturing the field effect transistor shown in FIG. 1 will be described. FIG. 2 is a diagram illustrating a manufacturing process of the field effect transistor according to the first embodiment.

  First, in the step shown in FIG. 2A, a base material 11 made of a glass base material or the like is prepared, and the semiconductor layer 12 is formed on the base material 11. The material and thickness of the base material 11 can be appropriately selected as described above. Further, from the viewpoint of cleaning the surface of the substrate 11 and improving adhesion, it is preferable to perform a pretreatment such as oxygen plasma, UV ozone, UV irradiation cleaning.

  The manufacturing method of the semiconductor layer 12 is not particularly limited and can be appropriately selected according to the purpose. For example, the sputtering method, the pulse laser deposition (PLD) method, the chemical vapor deposition (CVD) method, the atomic layer deposition After forming a film by a vacuum process such as the (ALD) method or a solution process such as dip coating, spin coating, or die coating, the desired shape is directly formed by a patterning method using photolithography, a printing method such as inkjet, nanoimprinting, or gravure. Examples include a film forming method.

  The semiconductor layer 12 is a continuous single layer formed in one process and is not divided into a plurality of regions at this time, but the channel is formed when the field effect transistor 10 is finally completed. The region including the formation region 121 and the non-channel formation region 122 is included. Therefore, here, for convenience, the semiconductor layer 12 is illustrated as being divided into a channel formation region 121 and a non-channel formation region 122.

  Next, in the step shown in FIG. 2B, the source electrode 13, the drain electrode 14, and the wiring 15 are formed on the semiconductor layer 12. There is no restriction | limiting in particular as a method of forming the source electrode 13, the drain electrode 14, and the wiring 15, According to the objective, it can select suitably, For example, (i) Sputtering method, vacuum evaporation method, dip coating method, Examples include a method of patterning by photolithography after film formation by a spin coating method, a die coating method, or the like, and (ii) a method of directly forming a desired shape by a printing process such as inkjet, nanoimprinting, or gravure.

  In the step shown in FIG. 2B, first, a metal film is formed on the base material 11 and the semiconductor layer 12 by a vacuum deposition method or the like. Then, by patterning the formed metal film by photolithography and etching, the source electrode 13, the drain electrode 14, and the wiring 15 having a predetermined shape can be formed. The materials and thicknesses of the source electrode 13, the drain electrode 14, and the wiring 15 can be appropriately selected as described above.

  Next, in the step shown in FIG. 2C, the gate insulating layer 16 that covers the source electrode 13, the drain electrode 14, and the wiring 15 is formed on the semiconductor layer 12. There is no restriction | limiting in particular as a manufacturing method of the gate insulating layer 16, According to the objective, it can select suitably, For example, (i) Sputtering method, a pulse laser deposition (PLD) method, chemical vapor deposition (CVD) After film formation by solution process such as vacuum process such as atomic layer deposition (ALD) method, dip coating method, spin coating method, die coating method, etc., patterning by photolithography, (ii) inkjet, nanoimprint, gravure, etc. Examples include a step of directly forming a desired shape by a printing process. The material and thickness of the gate insulating layer 16 can be appropriately selected as described above.

  Next, in the step shown in FIG. 2D, the gate electrode 17 is formed on the gate insulating layer 16. The method for forming the gate electrode 17 is not particularly limited and may be appropriately selected depending on the purpose. For example, (i) by sputtering, vacuum deposition, dip coating, spin coating, die coating, or the like. Examples include a method of patterning by photolithography after film formation, and (ii) a method of directly forming a desired shape by a printing process such as ink jet, nanoimprint, and gravure.

  In the step shown in FIG. 2D, first, a metal film is formed on the gate insulating layer 16 by a vacuum deposition method or the like. Then, by patterning the formed metal film by photolithography and etching, the gate electrode 17 having a predetermined shape can be formed. The material and thickness of the gate electrode 17 can be appropriately selected as described above.

  Through the above steps, the top-gate / top-contact field effect transistor 10 can be manufactured.

  As described above, the non-channel formation region 122 which is a layer for improving the film strength of the source electrode 13, the drain electrode 14, and the wiring 15 (a layer for improving the adhesion with the lower layer) has the semiconductor layer 12. In the forming step, the channel forming region 121 is formed by the same process. Therefore, in order to improve the film strength of the source electrode 13, the drain electrode 14, and the wiring 15 (in order to improve the adhesion with the lower layer), to improve the film strength separately from the step of forming the semiconductor layer 12. There is no need to provide a step of forming a layer (a layer for improving adhesion to the lower layer). As a result, the field effect transistor 10 having high adhesion to the lower layer of the source electrode 13, the drain electrode 14, and the wiring 15 and having excellent film stability (resistance to the manufacturing process) can be realized by a simple manufacturing process. Can do.

Further, as a conventional technique, there is a method of increasing the adhesion of electrodes and wirings by introducing other elements into the metal film that becomes the electrodes and wirings for wiring to the SiO ₂ surface and the like. According to the manufacturing method of the field effect transistor 10 according to the present embodiment, it is not necessary to add another element to the source electrode 13, the drain electrode 14, and the wiring 15, and pure metal can be used. Compared to the above, it is possible to obtain an electrode or wiring having a lower resistance.

<Modification of First Embodiment>
In the modification of the first embodiment, an example of a bottom gate / top contact field effect transistor is shown. In the modification of the first embodiment, the description of the same components as those of the already described embodiments may be omitted.

  FIG. 3 is a cross-sectional view illustrating a field effect transistor according to a modification of the first embodiment. Referring to FIG. 3, the field effect transistor 10A is a bottom gate / top contact field effect transistor. The field effect transistor 10A is a typical example of a semiconductor device according to the present invention.

  The field effect transistor 10A has a layer structure different from that of the field effect transistor 10 (see FIG. 1). Specifically, in the field effect transistor 10A, the gate electrode 17 is formed on the insulating base material 11, and the gate insulating layer 16 is formed on the base material 11 so as to cover the gate electrode 17. Further, the semiconductor layer 12 is formed on the gate insulating layer 16, and the source electrode 13, the drain electrode 14, and the wiring 15 are formed on the semiconductor layer 12.

  That is, in the field effect transistor 10A, the source electrode 13, the drain electrode 14, and the wiring 15 are not in direct contact with the gate insulating layer 16, and are an oxide semiconductor having excellent adhesion to glass, silicon, silicon oxide film, or the like. In contact with the channel formation region 121 or the non-channel formation region 122 (adhesion layer).

  With such a structure, as with the field-effect transistor 10, the adhesion to the lower layer of the source electrode 13, the drain electrode 14, and the wiring 15 is improved, and excellent film stability (resistance to the manufacturing process) can be obtained. it can.

  Thus, the layer structure of the field effect transistor according to the present invention is not particularly limited, and the structure shown in FIGS. 1 and 3 can be appropriately selected according to the purpose.

  Note that the bottom-gate / top-contact field effect transistor can be manufactured by appropriately changing the order of the steps shown in FIG.

<Example 1>
In Example 1, the top gate / top contact type field effect transistor shown in FIG. 1 was fabricated.

(Formation of semiconductor layer 12)
First, a semiconductor layer 12 having a predetermined shape was formed on the substrate 11. Specifically, first, an alkali-free glass was used as the base material 11, and an Mg—In-based oxide semiconductor film was formed on the base material 11 by a sputtering method. A polycrystalline fired body having a composition of In ₂ MgO ₄ (size: 4 inches in diameter) was used as a target. The ultimate vacuum in the sputtering chamber was 2 × 10 ⁻⁵ Pa. The flow rates of argon gas and oxygen gas flowing during sputtering were adjusted, and the total pressure was 0.3 Pa.

  During sputtering, the temperature of the base material 11 was controlled within the range of 15 to 35 degrees by cooling the holder holding the base material 11 with water cooling. A sputtering power was 150 W, a sputtering time was 30 minutes, and a 50 nm thick Mg—In-based oxide semiconductor film was formed. Thereafter, photolithography and etching were performed on the Mg—In-based oxide semiconductor film to form a semiconductor layer 12 having a predetermined shape.

(Formation of source electrode 13, drain electrode 14, and wiring 15)
Next, an Au film was formed on the substrate 11 and the semiconductor layer 12 using a vacuum deposition method. Thereafter, the Au film was subjected to photolithography and etching to form the source electrode 13 and the drain electrode 14 and the wiring 15 connected to the source electrode 13 and the drain electrode 14 on the semiconductor layer 12.

(Formation of the gate insulating layer 16)
Next, a gate insulating layer 16 was formed by depositing SiO ₂ to a thickness of 200 nm by plasma CVD.

(Formation of gate electrode 17)
Next, an Al film was formed on the gate insulating layer 16 by vacuum evaporation. Then, photolithography and etching were performed on the Al film to form a gate electrode 17 having a predetermined shape. Thus, the top gate / top contact type field effect transistor shown in FIG. 1 was manufactured.

(Transistor performance evaluation)
About the obtained field effect transistor, transistor performance evaluation was implemented using the semiconductor parameter analyzer apparatus (Agilent Technology company make, semiconductor parameter analyzer B1500). Specifically, the current / voltage characteristics were evaluated by changing the source / drain voltage Vds to 20 V and changing the gate voltage from Vg = −30 V to +30 V. Field effect mobility was calculated in the saturation region. Further, the ratio (on / off ratio) of the source / drain current Ids between the on state (for example, Vg = 20 V) and the off state (for example, Vg = −20 V) of the transistor was calculated.

<Comparative example 1>
A top-gate / top-contact field effect transistor 10L shown in FIG. 4 was produced in the same manner as in Example 1 except that the “formation of the semiconductor layer 12” was changed to the following method in Example 1. The same evaluation as in Example 1 was performed.

(Formation of semiconductor layer 12)
An Mg—In-based oxide semiconductor film was formed on the substrate 11 by the same method as in Example 1 by a sputtering method. After that, photolithography and etching were performed on the Mg—In-based oxide semiconductor film, so that the semiconductor layer 12 was formed only in a region to be a channel formation region (active region). That is, as shown in FIG. 4, a top-gate / top-contact field effect transistor 10L in which a layer corresponding to the non-channel formation region 122 in FIG.

<Summary of Example 1 and Comparative Example 1>
The results of Example 1 and Comparative Example 1 are shown in Table 1.

表１より、実施例１では、基材と、ソース電極、ドレイン電極、及び配線との密着層として酸化物半導体（半導体層１２の一部）を用いていることで、電極が剥れることなく電界効果型トランジスタを形成することができている。又、高いトランジスタ特性（電界効果移動度、オン／オフ比）を得ることができている。

From Table 1, in Example 1, the oxide semiconductor (part of the semiconductor layer 12) is used as an adhesion layer between the base material, the source electrode, the drain electrode, and the wiring, so that the electrode does not peel off. A field effect transistor can be formed. Further, high transistor characteristics (field effect mobility, on / off ratio) can be obtained.

  On the other hand, in Comparative Example 1, since there is no adhesion layer between the base material, the source electrode, the drain electrode, and the wiring, there is much film peeling of the electrode made of Au, and a field effect transistor can be manufactured with a high yield. There wasn't. Therefore, the field effect mobility and the on / off ratio could not be calculated.

<Example 2>
In Example 2, the bottom gate / top contact type field effect transistor shown in FIG. 3 was produced.

(Formation of gate electrode 17)
First, a gate electrode 17 having a predetermined shape was formed on the substrate 11. Specifically, first, a non-alkali glass was used as the base material 11, and a laminated film of a Cr film and an Au film was formed on the base material 11 using a vacuum deposition method. Thereafter, the laminated film of the Cr film and the Au film was subjected to photolithography and etching to form a gate electrode 17 having a predetermined shape.

(Formation of gate insulating layer 16, semiconductor layer 12, source electrode 13, etc.)
Next, a gate insulating layer 16 that covers the gate electrode 17 was formed on the substrate 11 by the same method as in Example 1. Thereafter, the semiconductor layer 12 was formed on the gate insulating layer 16 by the same method as in Example 1. Further, the source electrode 13, the drain electrode 14, and the wiring 15 were formed on the semiconductor layer 12 by the same method as in Example 1. Thus, the bottom gate / top contact type field effect transistor shown in FIG. 3 was manufactured.

(Transistor performance evaluation)
Next, the field effect mobility and the on / off ratio were calculated by the same method as in Example 1.

<Comparative example 2>
In Example 2, a bottom-gate / top-contact field effect transistor was fabricated in the same manner as in Example 2 except that the “formation of the semiconductor layer 12” was changed to the following method. The same evaluation as in Example 2 was performed.

(Formation of semiconductor layer 12)
An Mg—In-based oxide semiconductor film was formed on the gate insulating layer 16 by the same method as in Example 2 by a sputtering method. After that, photolithography and etching were performed on the Mg—In-based oxide semiconductor film, so that the semiconductor layer 12 was formed only in a region to be a channel formation region (active region). That is, a bottom gate / top contact type field effect transistor in which a layer corresponding to the non-channel formation region 122 in FIG. 3 was not formed over the gate insulating layer 16 was manufactured.

<Summary of Example 2 and Comparative Example 2>
The results of Example 2 and Comparative Example 2 are shown in Table 2.

表２より、実施例２では、ゲート絶縁層と、ソース電極、ドレイン電極、及び配線との密着層として酸化物半導体（半導体層１２の一部）を用いていることで、電極が剥れることなく電界効果型トランジスタを形成することができている。又、高いトランジスタ特性（電界効果移動度、オン／オフ比）を得ることができている。

From Table 2, in Example 2, the electrode is peeled off by using an oxide semiconductor (part of the semiconductor layer 12) as an adhesion layer between the gate insulating layer, the source electrode, the drain electrode, and the wiring. Thus, a field effect transistor can be formed. Further, high transistor characteristics (field effect mobility, on / off ratio) can be obtained.

  On the other hand, in Comparative Example 2, since there is no adhesion layer between the gate insulating layer and the source electrode, the drain electrode, and the wiring, the film of the electrode made of Au is often peeled off, and a field effect transistor is manufactured with a high yield. could not. Therefore, the field effect mobility and the on / off ratio could not be calculated.

<Example 3>
A bottom gate / top contact type field effect transistor was fabricated in the same manner as in Example 2 except that Cu was used instead of Au as the material of the source electrode 13, the drain electrode 14, and the wiring 15. The same evaluation as in Example 2 was performed.

<Comparative Example 3>
A bottom gate / top contact type field effect transistor was fabricated in the same manner as in Comparative Example 2 except that Cu was used instead of Au as the material of the source electrode 13, the drain electrode 14, and the wiring 15. The same evaluation as in Example 2 was performed.

<Summary of Example 3 and Comparative Example 3>
The results of Example 3 and Comparative Example 3 are shown in Table 3.

表３より、実施例３では、ゲート絶縁層と、ソース電極、ドレイン電極、及び配線との密着層として酸化物半導体（半導体層１２の一部）を用いていることで、電極が剥れることなく電界効果型トランジスタを形成することができている。又、高いトランジスタ特性（電界効果移動度、オン／オフ比）を得ることができている。

From Table 3, in Example 3, an oxide semiconductor (part of the semiconductor layer 12) is used as an adhesion layer between the gate insulating layer, the source electrode, the drain electrode, and the wiring, so that the electrode is peeled off. Thus, a field effect transistor can be formed. Further, high transistor characteristics (field effect mobility, on / off ratio) can be obtained.

  On the other hand, in Comparative Example 3, since there is no adhesion layer between the gate insulating layer and the source electrode, the drain electrode, and the wiring, the electrode made of Cu is often peeled off, and a field effect transistor is manufactured with high yield. could not. Further, in an element having transistor characteristics, high transistor characteristics could not be obtained. This is presumably because the source electrode, the drain electrode, and the wiring are not stable as a film and the function as an electrode is not sufficient.

<Examples 4 to 6>
In Example 2, a bottom-gate / top-contact field effect transistor was fabricated in the same manner as in Example 2 except that the “formation of the semiconductor layer 12” was changed to the following method. The same evaluation as in Example 2 was performed.

(Formation of semiconductor layer 12)
In a beaker, weigh out 3.55 g of indium nitrate (In (NO ₃ ) ₃ .3H ₂ O) and 0.139 g of strontium chloride (SrCl ₂ .6H ₂ O), 20 mL of 1,2-propanediol and ethylene glycol 20 mL of monomethyl ether was added and mixed and dissolved at room temperature to prepare a coating solution 1 for forming an n-type oxide semiconductor film used in Example 4.

Similarly, 3.55 g of indium nitrate (In (NO ₃ ) ₃ .3H ₂ O) and 0.125 g of calcium nitrate (Ca (NO ₃ ) ₂ .4H ₂ O) are weighed in a beaker. -20 mL of propanediol and 20 mL of ethylene glycol monomethyl ether were added, mixed and dissolved at room temperature, and the coating liquid 2 for forming an n-type oxide semiconductor film used in Example 5 was produced.

Similarly, 3.55 g of indium nitrate (In (NO ₃ ) ₃ .3H ₂ O) and 0.125 g of barium chloride (BaCl ₂ .2H ₂ O) were weighed in a beaker, and 20 ml of 1,2-ethanediol was measured. And 20 ml of ethylene glycol monomethyl ether were added and mixed and dissolved at room temperature to prepare n-type oxide semiconductor film-forming coating solution 3 used in Example 6.

  On the gate insulating layer, the coating liquids 1 to 3 for forming an oxide semiconductor film were applied in a predetermined pattern using an inkjet apparatus. The substrate was dried on a hot plate heated to 120 ° C. for 10 minutes, and then fired at 400 ° C. for 1 hour in an air atmosphere to obtain an In—Sr-based oxide film, an In—Ca-based oxide film, and an In— Ba-based oxide films were formed respectively.

<Comparative Examples 4-6>
In the same manner as in Examples 4 to 6, the coating liquids 1 to 3 for forming an oxide semiconductor film were each applied in a predetermined pattern on the gate insulating layer using an inkjet device. The substrate was dried on a hot plate heated to 120 ° C. for 10 minutes, and then fired at 400 ° C. for 1 hour in an air atmosphere to obtain an In—Sr-based oxide film, an In—Ca-based oxide film, and an In— Ba-based oxide films were formed respectively.

  However, each oxide film was formed only in a region to be a channel formation region (active region). That is, a bottom gate / top contact field effect transistor in which a layer corresponding to the non-channel formation region 122 was not formed was manufactured.

<Summary of Examples 4 to 6 and Comparative Examples 4 to 6>
Table 4 shows the results of Examples 4 to 6 and Comparative Examples 4 to 6.

表４より、実施例４〜６では、ゲート絶縁層と、ソース電極、ドレイン電極、及び配線との密着層として酸化物半導体（半導体層１２の一部）を用いていることで、電極が剥れることなく電界効果型トランジスタを形成することができている。又、高いトランジスタ特性（電界効果移動度、オン／オフ比）を得ることができている。

From Table 4, in Examples 4-6, an oxide semiconductor (a part of the semiconductor layer 12) is used as an adhesion layer between the gate insulating layer, the source electrode, the drain electrode, and the wiring. Thus, a field effect transistor can be formed. Further, high transistor characteristics (field effect mobility, on / off ratio) can be obtained.

  On the other hand, in Comparative Examples 4 to 6, since there is no adhesion layer between the gate insulating layer and the source electrode, the drain electrode, and the wiring, the film made of the electrode made of Au is often peeled off, and the field effect transistor is obtained. It couldn't be manufactured well. Further, in an element having transistor characteristics, high transistor characteristics could not be obtained. This is presumably because the source electrode, the drain electrode, and the wiring are not stable as a film and the function as an electrode is not sufficient.

<Second Embodiment>
In the second embodiment, an example of a display element, an image display device, and a system using the field effect transistor according to the first embodiment is shown. In the second embodiment, description of the same components as those of the already described embodiments may be omitted.

(Display element)
The display element according to the second embodiment includes at least a light control element and a drive circuit that drives the light control element, and further includes other members as necessary. The light control element is not particularly limited as long as it is an element that controls the light output according to the drive signal, and can be appropriately selected according to the purpose. For example, an electroluminescence (EL) element, an electrochromic (EC) ) Elements, liquid crystal elements, electrophoretic elements, electrowetting elements and the like.

  The drive circuit is not particularly limited as long as it has the field effect transistor according to the first embodiment, and can be appropriately selected according to the purpose. There is no restriction | limiting in particular as another member, According to the objective, it can select suitably.

  Since the display element according to the second embodiment includes the field effect transistor according to the first embodiment, the display element according to the second embodiment has excellent adhesion between electrodes and wirings and a lower layer, and has a high field effect. Mobility and high on / off ratio can be obtained. As a result, high quality display can be performed.

(Image display device)
The image display device according to the second embodiment includes at least a plurality of display elements according to the second embodiment, a plurality of wirings, and a display control device. It has a member. The plurality of display elements are not particularly limited as long as they are the display elements according to the plurality of second embodiments arranged in a matrix, and can be appropriately selected according to the purpose.

  The plurality of wirings are not particularly limited and can be appropriately selected depending on the purpose as long as the gate voltage and the image data signal can be individually applied to each field effect transistor in the plurality of display elements.

  The display control device is not particularly limited as long as the gate voltage and signal voltage of each field effect transistor can be individually controlled via a plurality of wirings according to image data, and is appropriately selected according to the purpose. can do. There is no restriction | limiting in particular as another member, According to the objective, it can select suitably.

  Since the image display device according to the second embodiment includes the display element including the field effect transistor according to the first embodiment, it is possible to display a high-quality image.

(system)
The system according to the second embodiment includes at least an image display device according to the second embodiment and an image data creation device. The image data creation device creates image data based on the image information to be displayed, and outputs the image data to the image display device.

  Since the system includes the image display device according to the second embodiment, the image information can be displayed with high definition.

  Hereinafter, the display element, the image display apparatus, and the system according to the second embodiment will be specifically described.

  FIG. 5 shows a schematic configuration of a television device 500 as a system according to the second embodiment. In addition, the connection line in FIG. 5 shows the flow of a typical signal and information, and does not represent all the connection relationships of each block.

  A television apparatus 500 according to the second embodiment includes a main controller 501, a tuner 503, an AD converter (ADC) 504, a demodulation circuit 505, a TS (Transport Stream) decoder 506, an audio decoder 511, and a DA converter (DAC). 512, audio output circuit 513, speaker 514, video decoder 521, video / OSD synthesis circuit 522, video output circuit 523, image display device 524, OSD drawing circuit 525, memory 531, operation device 532, drive interface (drive IF) 541 A hard disk device 542, an optical disk device 543, an IR light receiver 551, a communication control device 552, and the like.

  The main control device 501 controls the entire television device 500 and includes a CPU, a flash ROM, a RAM, and the like. The flash ROM stores a program written in a code readable by the CPU, various data used for processing by the CPU, and the like. The RAM is a working memory.

  The tuner 503 selects a preset channel broadcast from the broadcast waves received by the antenna 610. The ADC 504 converts the output signal (analog information) of the tuner 503 into digital information. The demodulation circuit 505 demodulates the digital information from the ADC 504.

  The TS decoder 506 performs TS decoding on the output signal of the demodulation circuit 505 and separates audio information and video information. The audio decoder 511 decodes the audio information from the TS decoder 506. The DA converter (DAC) 512 converts the output signal of the audio decoder 511 into an analog signal.

  The audio output circuit 513 outputs the output signal of the DA converter (DAC) 512 to the speaker 514. The video decoder 521 decodes the video information from the TS decoder 506. The video / OSD synthesis circuit 522 synthesizes the output signal of the video decoder 521 and the output signal of the OSD drawing circuit 525.

  The video output circuit 523 outputs the output signal of the video / OSD synthesis circuit 522 to the image display device 524. The OSD drawing circuit 525 includes a character generator for displaying characters and figures on the screen of the image display device 524, and a signal including display information in response to an instruction from the operation device 532 or the IR light receiver 551. Generate.

  The memory 531 temporarily stores AV (Audio-Visual) data and the like. The operating device 532 includes an input medium (not shown) such as a control panel, for example, and notifies the main controller 501 of various information input by the user. The drive IF 541 is a bi-directional communication interface, and is compliant with ATAPI (AT Attachment Packet Interface) as an example.

  The hard disk device 542 includes a hard disk and a drive device for driving the hard disk. The drive device records data on the hard disk and reproduces data recorded on the hard disk. The optical disk device 543 records data on an optical disk (for example, DVD) and reproduces data recorded on the optical disk.

  The IR light receiver 551 receives the optical signal from the remote control transmitter 620 and notifies the main controller 501 of it. The communication control device 552 controls communication with the Internet. Various information can be acquired via the Internet.

  The image display device 524 includes a display 700 and a display control device 780 as shown in FIG. 6 as an example. As an example, the display 700 includes a display 710 in which a plurality of (here, n × m) display elements 702 are arranged in a matrix, as shown in FIG.

  In addition, as shown in FIG. 8 as an example, the display 710 includes n scanning lines (X0, X1, X2, X3,..., Xn) arranged at equal intervals along the X-axis direction. -2, Xn-1), m data lines (Y0, Y1, Y2, Y3, ..., Ym-1) arranged at equal intervals along the Y-axis direction, in the Y-axis direction M current supply lines (Y0i, Y1i, Y2i, Y3i,..., Ym-1i) arranged at equal intervals along the line. The display element 702 can be specified by the scan line and the data line.

  As shown in FIG. 9 as an example, each display element 702 has an organic EL (electroluminescence) element 750 and a drive circuit 720 for causing the organic EL element 750 to emit light. That is, the display 710 is a so-called active matrix type organic EL display. The display 710 is a color-compatible 32-inch display. The size is not limited to this.

  As an example, the organic EL element 750 includes an organic EL thin film layer 740, a cathode 712, and an anode 714, as shown in FIG.

The organic EL element 750 can be disposed beside a field effect transistor, for example. In this case, the organic EL element 750 and the field effect transistor can be formed on the same substrate. However, it is not limited to this, For example, the organic EL element 750 may be arrange | positioned on a field effect transistor. In this case, since transparency is required for the gate electrode, ITO, In ₂ O ₃ , SnO ₂ , ZnO, ZnO to which Ga is added, ZnO to which Al is added, and Sb are added to the gate electrode. A transparent oxide having conductivity such as SnO ₂ is used.

In the organic EL element 750, aluminum (Al) is used for the cathode 712. A magnesium (Mg) -silver (Ag) alloy, an aluminum (Al) -lithium (Li) alloy, ITO (Indium Tin Oxide), or the like may be used. ITO is used for the anode 714. Note that a conductive oxide such as In ₂ O ₃ , SnO ₂ , or ZnO, a silver (Ag) -neodymium (Nd) alloy, or the like may be used.

  The organic EL thin film layer 740 includes an electron transport layer 742, a light emitting layer 744, and a hole transport layer 746. A cathode 712 is connected to the electron transport layer 742, and an anode 714 is connected to the hole transport layer 746. When a predetermined voltage is applied between the anode 714 and the cathode 712, the light emitting layer 744 emits light.

  As shown in FIG. 9, the drive circuit 720 includes two field effect transistors 810 and 820 and a capacitor 830. The field effect transistor 810 operates as a switch element. The gate electrode G is connected to a predetermined scanning line, and the source electrode S is connected to a predetermined data line. The drain electrode D is connected to one terminal of the capacitor 830.

  The capacitor 830 is for storing the state of the field effect transistor 810, that is, data. The other terminal of the capacitor 830 is connected to a predetermined current supply line.

  The field effect transistor 820 is for supplying a large current to the organic EL element 750. The gate electrode G is connected to the drain electrode D of the field effect transistor 810. The drain electrode D is connected to the anode 714 of the organic EL element 750, and the source electrode S is connected to a predetermined current supply line.

  Therefore, when the field effect transistor 810 is turned on, the organic EL element 750 is driven by the field effect transistor 820.

  As an example, the display control device 780 includes an image data processing circuit 782, a scanning line driving circuit 784, and a data line driving circuit 786, as shown in FIG.

  The image data processing circuit 782 determines the brightness of the plurality of display elements 702 in the display 710 based on the output signal of the video output circuit 523. The scanning line driving circuit 784 individually applies voltages to the n scanning lines in accordance with an instruction from the image data processing circuit 782. The data line driving circuit 786 individually applies voltages to the m data lines in accordance with an instruction from the image data processing circuit 782.

  As is clear from the above description, in the television apparatus 500 according to the present embodiment, the video decoder 521, the video / OSD synthesis circuit 522, the video output circuit 523, and the OSD drawing circuit 525 constitute an image data creation apparatus. ing.

  In the above description, the light control element is an organic EL element. However, the present invention is not limited to this, and a liquid crystal element, an electrochromic element, an electrophoretic element, or an electrowetting element may be used.

  For example, when the light control element is a liquid crystal element, a liquid crystal display is used as the display 710. In this case, as shown in FIG. 12, the current supply line in the display element 703 is not necessary.

  Further, in this case, as shown in FIG. 13 as an example, the drive circuit 730 is configured by only one field effect transistor 840 similar to the field effect transistor (810, 820) shown in FIG. Can do. In the field effect transistor 840, the gate electrode G is connected to a predetermined scanning line, and the source electrode S is connected to a predetermined data line. Further, the drain electrode D is connected to the pixel electrode of the liquid crystal element 770 and the capacitor 760. Note that reference numerals 762 and 772 in FIG. 13 denote a counter electrode (common electrode) of the capacitor 760 and the liquid crystal element 770, respectively.

  In the above embodiment, the case where the system is a television apparatus has been described. However, the present invention is not limited to this. In short, the image display device 524 may be provided as a device for displaying images and information. For example, a computer system in which a computer (including a personal computer) and an image display device 524 are connected may be used.

  In addition, an image display device 524 is provided as a display means in a portable information device such as a mobile phone, a portable music player, a portable video player, an electronic BOOK, a PDA (Personal Digital Assistant), or an imaging device such as a still camera or a video camera. Can be used. Further, the image display device 524 can be used as a display unit for various information in a mobile system such as a car, an aircraft, a train, and a ship. Furthermore, the image display device 524 can be used as a display unit for various information in a measurement device, an analysis device, a medical device, and an advertising medium.

<Third Embodiment>
In the third embodiment, an example of a display element array using field effect transistors according to a modification of the first embodiment will be described. Note that in the third embodiment, description of the same components as those of the already described embodiments may be omitted.

  FIG. 14 is a plan view illustrating a display element array according to the third embodiment. 15 is a cross-sectional view taken along line AA in FIG. 16 is a cross-sectional view taken along line BB in FIG.

  As shown in FIGS. 14 to 16, the display element array 20 according to the third embodiment includes a plurality of light control elements 21 and drive circuits 22 that drive the light control elements 21. The display element array 20 may have other members as necessary.

  The light control element 21 is not particularly limited as long as it is an element that controls light output in accordance with a drive signal, and can be appropriately selected according to the purpose. For example, an electroluminescence (EL) element, electrochromic ( EC) element, liquid crystal element, electrophoretic element, electrowetting element and the like.

The driving circuit 22, is used here two field effect transistors 10A according to a modification of the first embodiment as an example (for convenience, the field effect transistors 10A ₁ and 10A _2). Needless to say, the field-effect transistor 10 according to the first embodiment may be used as the drive circuit 22.

Field effect transistors 10A ₁ and 10A ₂ are formed on the same substrate 11 so as to be adjacent in the Y direction. The light control element 21 is formed on the same substrate 11 so as to be adjacent to the field effect transistor 10A ₂ and Y directions. However, not limited thereto. For example, the light control element 21 may be disposed on the field effect transistor 10A _2. Reference numeral 30 denotes a pixel electrode of the light control element 21.

  The display element array 20 includes scanning lines 41 arranged at equal intervals along the X-axis direction, data lines 42 arranged at equal intervals along the Y-axis direction, and equal intervals along the X-axis direction. And a current supply line 43 disposed in the line. The scanning lines 41 and the data lines 42 can define one display element including the light control element 21 and the drive circuit 22, and each display element is arranged in a matrix to form the display element array 20. Yes. The number of scanning lines 41, data lines 42, and current supply lines 43 can be determined as appropriate.

In the drive circuit 22, field effect transistor 10A ₁ operates as a switching element. In the field effect transistor 10A _1, the gate electrode 17 is connected to a predetermined scan line 41, the source electrode 13 is connected to a predetermined data line 42 via the wiring 15, the drain electrode 14 is a field effect through the wire 15 It is connected to the gate electrode 17 of the type transistors 10A _2.

Field effect transistor 10A ₂ is for supplying a large current to the light control device 21. In the field effect transistor 10 </ _b > A ₂ , the source electrode 13 is connected to a predetermined current supply line 43 through a wiring 15, and the drain electrode 14 is connected to the pixel electrode 30 of the light control element 21 through the wiring 15.

When the field effect transistor 10A ₁ is "on" state, the light control element 21 by an electric field effect type transistor 10A ₂ is driven.

FIG. 17 is a plan view illustrating the formation region of the semiconductor layer in the display element array according to the third embodiment. As described above, the semiconductor layer 12 of the field effect transistors 10A ₁ and 10A ₂ includes a channel forming region 121, and a non-channel-forming region 122.

  As can be seen by comparing FIG. 17 and FIG. 14, in the display element array 20, a part of the non-channel formation region 122 is formed in a region that does not overlap any of the source electrode 13, the drain electrode 14, and the gate electrode 17. Has been.

Some non-channel-forming region 122, for example, the wiring 15 for connecting the source electrode 13 and the current supply line 43 of the field effect transistor 10A _2, and a drain electrode 14 and the pixel electrode 30 of the field effect transistor 10A ₂ it can be formed in a region which overlaps with the wiring 15 and the data line 42, line 15, for connecting the field effect transistor 10A ₁ and the field effect transistor 10A ₂ to be connected.

  In this manner, a part of the non-channel formation region 122 may be formed in a region that does not overlap any of the source electrode 13, the drain electrode 14, and the gate electrode 17 as necessary.

  FIG. 18 is a plan view illustrating a display element array according to a comparative example. In the display element array 20X shown in FIG. 18, the semiconductor layer 12X is provided only in the vicinity of a region sandwiched between the source electrode 13 and the drain electrode 14 in plan view. That is, the semiconductor layer 12X is provided only in a region corresponding to the channel formation region 121 of the semiconductor layer 12 of the display element array 20 shown in FIG. 14, and is provided in a region corresponding to the non-channel formation region 122. Absent.

  In the display element array 20, unlike the display element array 20 </ b> X according to the comparative example, the non-channel formation region 122 which is a part of the semiconductor layer 12 is not limited to the lower layer of the source electrode 13 and the drain electrode 14, but the wiring 15 It is also provided below the line 42 to function as an adhesion layer. Thereby, the adhesiveness with respect to the lower layer of each metal film which comprises the source electrode 13 grade | etc., Improves, and the outstanding film | membrane stability (resistance with respect to a manufacturing process) can be obtained.

  The preferred embodiments and the like have been described in detail above, but the present invention is not limited to the above-described embodiments and the like, and various modifications can be made to the above-described embodiments and the like without departing from the scope described in the claims. Variations and substitutions can be added.

_10,10A, 10A _1, 10A ₂ field effect transistor 11 substrate 12 semiconductor layer 13 source electrode 14 drain electrode 15 wiring 16 gate insulating layer 17 a gate electrode 20 display element array 21 an optical control device 22 drive circuit 30 pixel electrode 41 scan Line 42 Data line 43 Current supply line 121 Channel formation region 122 Non-channel formation region

Patent No. 5118811

Claims (7)

A substrate;
A gate electrode for applying a gate voltage;
A source electrode and a drain electrode for extracting current in response to application of the gate voltage;
A semiconductor layer made of an oxide semiconductor;
A gate insulating layer provided between the gate electrode and the semiconductor layer, and a semiconductor device comprising:
The semiconductor layer has a channel formation region and a non-channel formation region,
A semiconductor device, wherein the channel formation region and the non-channel formation region are formed in contact with a source electrode and a drain electrode, respectively.   The semiconductor device according to claim 1, wherein the non-channel formation region is formed in contact with a wiring connected to the source electrode or the drain electrode.   3. The semiconductor device according to claim 1, wherein the semiconductor device is a top contact type field effect transistor. A drive circuit;
A light control element whose light output is controlled in accordance with a drive signal from the drive circuit;
Have
4. The display element, wherein the drive circuit drives the light control element by the semiconductor device according to claim 1.   The display device according to claim 4, wherein the light control element is an electroluminescence element, an electrochromic element, a liquid crystal element, an electrophoretic element, or an electrowetting element. A display in which a plurality of display elements according to claim 4 or 5 are arranged in a matrix,
A display control device for individually controlling each of the display elements;
A display device comprising: A display device according to claim 6;
An image data creation device for supplying image data to the display device;
The system characterized by having.

Images